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src/hotspot/cpu/x86/assembler_x86.cpp
changeset 54022 ff399127078a
parent 52992 4bb6e0871bf7
child 54519 a2795025f417
equal deleted inserted replaced
54021:6347ffe2c3c7 54022:ff399127078a 
     1 /*
 
     1 /*
 
     2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
 
     2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
 
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 
     4  *
 
     4  *
 
     5  * This code is free software; you can redistribute it and/or modify it
 
     5  * This code is free software; you can redistribute it and/or modify it
 
     6  * under the terms of the GNU General Public License version 2 only, as
 
     6  * under the terms of the GNU General Public License version 2 only, as
 
     7  * published by the Free Software Foundation.
 
     7  * published by the Free Software Foundation.
 
  7763     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
 
  7763     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
 
  7764     return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
 
  7764     return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
 
  7765   }
 
  7765   }
 
  7766 }
 
  7766 }
 
  7767 
  7767 
       
  7768 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 
       
  7769   assert(VM_Version::supports_avx(), "");
 
       
  7770   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  7771   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 
       
  7772   emit_int8(0x5F);
 
       
  7773   emit_int8((unsigned char)(0xC0 | encode));
 
       
  7774 }
 
       
  7775 
       
  7776 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 
       
  7777   assert(VM_Version::supports_avx(), "");
 
       
  7778   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  7779   attributes.set_rex_vex_w_reverted();
 
       
  7780   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 
       
  7781   emit_int8(0x5F);
 
       
  7782   emit_int8((unsigned char)(0xC0 | encode));
 
       
  7783 }
 
       
  7784 
       
  7785 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 
       
  7786   assert(VM_Version::supports_avx(), "");
 
       
  7787   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  7788   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 
       
  7789   emit_int8(0x5D);
 
       
  7790   emit_int8((unsigned char)(0xC0 | encode));
 
       
  7791 }
 
       
  7792 
       
  7793 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 
       
  7794   assert(VM_Version::supports_avx(), "");
 
       
  7795   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 
       
  7796   attributes.set_rex_vex_w_reverted();
 
       
  7797   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 
       
  7798   emit_int8(0x5D);
 
       
  7799   emit_int8((unsigned char)(0xC0 | encode));
 
       
  7800 }
 
       
  7801 
  7768 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
 
  7802 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
 
  7769   assert(VM_Version::supports_avx(), "");
 
  7803   assert(VM_Version::supports_avx(), "");
 
  7770   assert(!VM_Version::supports_evex(), "");
 
  7804   assert(vector_len <= AVX_256bit, "");
 
  7771   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7805   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7772   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
  7806   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 
  7773   emit_int8((unsigned char)0xC2);
 
  7807   emit_int8((unsigned char)0xC2);
 
  7774   emit_int8((unsigned char)(0xC0 | encode));
 
  7808   emit_int8((unsigned char)(0xC0 | encode));
 
  7775   emit_int8((unsigned char)(0xF & cop));
 
  7809   emit_int8((unsigned char)(0xF & cop));
 
  7776 }
 
  7810 }
 
  7777 
  7811 
  7778 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
 
  7812 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
 
  7779   assert(VM_Version::supports_avx(), "");
 
  7813   assert(VM_Version::supports_avx(), "");
 
  7780   assert(!VM_Version::supports_evex(), "");
 
  7814   assert(vector_len <= AVX_256bit, "");
 
  7781   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7815   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7782   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  7816   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  7783   emit_int8((unsigned char)0x4B);
 
  7817   emit_int8((unsigned char)0x4B);
 
  7784   emit_int8((unsigned char)(0xC0 | encode));
 
  7818   emit_int8((unsigned char)(0xC0 | encode));
 
  7785   int src2_enc = src2->encoding();
 
  7819   int src2_enc = src2->encoding();
 
  7786   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
 
  7820   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
 
  7787 }
 
  7821 }
 
  7788 
  7822 
  7789 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
 
  7823 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
 
  7790   assert(VM_Version::supports_avx(), "");
 
  7824   assert(VM_Version::supports_avx(), "");
 
  7791   assert(!VM_Version::supports_evex(), "");
 
  7825   assert(vector_len <= AVX_256bit, "");
 
  7792   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7826   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7793   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 
  7827   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 
  7794   emit_int8((unsigned char)0xC2);
 
  7828   emit_int8((unsigned char)0xC2);
 
  7795   emit_int8((unsigned char)(0xC0 | encode));
 
  7829   emit_int8((unsigned char)(0xC0 | encode));
 
  7796   emit_int8((unsigned char)(0xF & cop));
 
  7830   emit_int8((unsigned char)(0xF & cop));
 
  7797 }
 
  7831 }
 
  7798 
  7832 
  7799 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
 
  7833 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
 
  7800   assert(VM_Version::supports_avx(), "");
 
  7834   assert(VM_Version::supports_avx(), "");
 
  7801   assert(!VM_Version::supports_evex(), "");
 
  7835   assert(vector_len <= AVX_256bit, "");
 
  7802   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7836   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 
  7803   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  7837   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 
  7804   emit_int8((unsigned char)0x4A);
 
  7838   emit_int8((unsigned char)0x4A);
 
  7805   emit_int8((unsigned char)(0xC0 | encode));
 
  7839   emit_int8((unsigned char)(0xC0 | encode));
 
  7806   int src2_enc = src2->encoding();
 
  7840   int src2_enc = src2->encoding();
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