src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp
changeset 48807 fd8ccb37fce9
parent 48120 bb957f109a1f
child 48856 c866eaca24cb
equal deleted inserted replaced
48806:51fc22e5fb00 48807:fd8ccb37fce9
     1 /*
     1 /*
     2  * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
     2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  *
     4  *
     5  * This code is free software; you can redistribute it and/or modify it
     5  * This code is free software; you can redistribute it and/or modify it
     6  * under the terms of the GNU General Public License version 2 only, as
     6  * under the terms of the GNU General Public License version 2 only, as
     7  * published by the Free Software Foundation.
     7  * published by the Free Software Foundation.
   989   LIR_Address* addr     = dest->as_address_ptr();
   989   LIR_Address* addr     = dest->as_address_ptr();
   990   Register base = addr->base()->as_pointer_register();
   990   Register base = addr->base()->as_pointer_register();
   991   int offset = -1;
   991   int offset = -1;
   992 
   992 
   993   switch (c->type()) {
   993   switch (c->type()) {
       
   994     case T_FLOAT: type = T_INT; // Float constants are stored by int store instructions.
   994     case T_INT:
   995     case T_INT:
   995     case T_FLOAT:
       
   996     case T_ADDRESS: {
   996     case T_ADDRESS: {
   997       LIR_Opr tmp = FrameMap::O7_opr;
   997       LIR_Opr tmp = FrameMap::O7_opr;
   998       int value = c->as_jint_bits();
   998       int value = c->as_jint_bits();
   999       if (value == 0) {
   999       if (value == 0) {
  1000         tmp = FrameMap::G0_opr;
  1000         tmp = FrameMap::G0_opr;
  1200       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
  1200       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
  1201       __ lduw(from.base(), from.disp(), tmp);
  1201       __ lduw(from.base(), from.disp(), tmp);
  1202       __ stw(tmp, to.base(), to.disp());
  1202       __ stw(tmp, to.base(), to.disp());
  1203       break;
  1203       break;
  1204     }
  1204     }
       
  1205     case T_ADDRESS:
  1205     case T_OBJECT: {
  1206     case T_OBJECT: {
  1206       Register tmp = O7;
  1207       Register tmp = O7;
  1207       Address from = frame_map()->address_for_slot(src->single_stack_ix());
  1208       Address from = frame_map()->address_for_slot(src->single_stack_ix());
  1208       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
  1209       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
  1209       __ ld_ptr(from.base(), from.disp(), tmp);
  1210       __ ld_ptr(from.base(), from.disp(), tmp);
  1352   }
  1353   }
  1353   if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
  1354   if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
  1354     __ verify_oop(to_reg->as_register());
  1355     __ verify_oop(to_reg->as_register());
  1355   }
  1356   }
  1356 }
  1357 }
  1357 
       
  1358 
  1358 
  1359 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
  1359 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
  1360                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
  1360                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
  1361                             bool wide, bool unaligned) {
  1361                             bool wide, bool unaligned) {
  1362   assert(type != T_METADATA, "store of metadata ptr not supported");
  1362   assert(type != T_METADATA, "store of metadata ptr not supported");
  2263          op->tmp2()->as_register()  == G3 &&
  2263          op->tmp2()->as_register()  == G3 &&
  2264          op->tmp3()->as_register()  == G4 &&
  2264          op->tmp3()->as_register()  == G4 &&
  2265          op->obj()->as_register()   == O0 &&
  2265          op->obj()->as_register()   == O0 &&
  2266          op->klass()->as_register() == G5, "must be");
  2266          op->klass()->as_register() == G5, "must be");
  2267   if (op->init_check()) {
  2267   if (op->init_check()) {
       
  2268     add_debug_info_for_null_check_here(op->stub()->info());
  2268     __ ldub(op->klass()->as_register(),
  2269     __ ldub(op->klass()->as_register(),
  2269           in_bytes(InstanceKlass::init_state_offset()),
  2270           in_bytes(InstanceKlass::init_state_offset()),
  2270           op->tmp1()->as_register());
  2271           op->tmp1()->as_register());
  2271     add_debug_info_for_null_check_here(op->stub()->info());
       
  2272     __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
  2272     __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
  2273     __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
  2273     __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
  2274     __ delayed()->nop();
  2274     __ delayed()->nop();
  2275   }
  2275   }
  2276   __ allocate_object(op->obj()->as_register(),
  2276   __ allocate_object(op->obj()->as_register(),