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src/hotspot/cpu/sparc/vm_version_sparc.hpp
changeset 47562 f789ccebcfe4
parent 47216 71c04702a3d5
child 52904 d2f118d3f8e7
equal deleted inserted replaced
47561:f59f0e51ef8a 47562:f789ccebcfe4 
    65     ISA_XMPMUL,
 
    65     ISA_XMPMUL,
 
    66     ISA_XMONT,
 
    66     ISA_XMONT,
 
    67     ISA_PAUSE_NSEC,
 
    67     ISA_PAUSE_NSEC,
 
    68     ISA_VAMASK,
 
    68     ISA_VAMASK,
 
    69 
    69 
       
    70     ISA_SPARC6,
 
       
    71     ISA_DICTUNP,
 
       
    72     ISA_FPCMPSHL,
 
       
    73     ISA_RLE,
 
       
    74     ISA_SHA3,
 
       
    75     ISA_FJATHPLUS2,
 
       
    76     ISA_VIS3C,
 
       
    77     ISA_SPARC5B,
 
       
    78     ISA_MME,
 
       
    79 
    70     // Synthesised properties:
 
    80     // Synthesised properties:
 
    71 
    81 
    72     CPU_FAST_IDIV,
 
    82     CPU_FAST_IDIV,
 
    73     CPU_FAST_RDPC,
 
    83     CPU_FAST_RDPC,
 
    74     CPU_FAST_BIS,
 
    84     CPU_FAST_BIS,
 
    77     CPU_FAST_IND_BR,
 
    87     CPU_FAST_IND_BR,
 
    78     CPU_BLK_ZEROING
 
    88     CPU_BLK_ZEROING
 
    79   };
 
    89   };
 
    80 
    90 
    81 private:
 
    91 private:
 
    82   enum { ISA_last_feature = ISA_VAMASK,
 
    92   enum { ISA_last_feature = ISA_MME,
 
    83          CPU_last_feature = CPU_BLK_ZEROING };
 
    93          CPU_last_feature = CPU_BLK_ZEROING };
 
    84 
    94 
    85   enum {
 
    95   enum {
 
    86     ISA_unknown_msk     = 0,
 
    96     ISA_unknown_msk     = 0,
 
    87 
    97 
   117     ISA_xmpmul_msk      = UINT64_C(1) << ISA_XMPMUL,
 
   127     ISA_xmpmul_msk      = UINT64_C(1) << ISA_XMPMUL,
 
   118     ISA_xmont_msk       = UINT64_C(1) << ISA_XMONT,
 
   128     ISA_xmont_msk       = UINT64_C(1) << ISA_XMONT,
 
   119     ISA_pause_nsec_msk  = UINT64_C(1) << ISA_PAUSE_NSEC,
 
   129     ISA_pause_nsec_msk  = UINT64_C(1) << ISA_PAUSE_NSEC,
 
   120     ISA_vamask_msk      = UINT64_C(1) << ISA_VAMASK,
 
   130     ISA_vamask_msk      = UINT64_C(1) << ISA_VAMASK,
 
   121 
   131 
       
   132     ISA_sparc6_msk      = UINT64_C(1) << ISA_SPARC6,
 
       
   133     ISA_dictunp_msk     = UINT64_C(1) << ISA_DICTUNP,
 
       
   134     ISA_fpcmpshl_msk    = UINT64_C(1) << ISA_FPCMPSHL,
 
       
   135     ISA_rle_msk         = UINT64_C(1) << ISA_RLE,
 
       
   136     ISA_sha3_msk        = UINT64_C(1) << ISA_SHA3,
 
       
   137     ISA_fjathplus2_msk  = UINT64_C(1) << ISA_FJATHPLUS2,
 
       
   138     ISA_vis3c_msk       = UINT64_C(1) << ISA_VIS3C,
 
       
   139     ISA_sparc5b_msk     = UINT64_C(1) << ISA_SPARC5B,
 
       
   140     ISA_mme_msk         = UINT64_C(1) << ISA_MME,
 
       
   141 
   122     CPU_fast_idiv_msk   = UINT64_C(1) << CPU_FAST_IDIV,
 
   142     CPU_fast_idiv_msk   = UINT64_C(1) << CPU_FAST_IDIV,
 
   123     CPU_fast_rdpc_msk   = UINT64_C(1) << CPU_FAST_RDPC,
 
   143     CPU_fast_rdpc_msk   = UINT64_C(1) << CPU_FAST_RDPC,
 
   124     CPU_fast_bis_msk    = UINT64_C(1) << CPU_FAST_BIS,
 
   144     CPU_fast_bis_msk    = UINT64_C(1) << CPU_FAST_BIS,
 
   125     CPU_fast_ld_msk     = UINT64_C(1) << CPU_FAST_LD,
 
   145     CPU_fast_ld_msk     = UINT64_C(1) << CPU_FAST_LD,
 
   126     CPU_fast_cmove_msk  = UINT64_C(1) << CPU_FAST_CMOVE,
 
   146     CPU_fast_cmove_msk  = UINT64_C(1) << CPU_FAST_CMOVE,
 
   151  *  UltraSPARC T2:     (Niagara-2)
 
   171  *  UltraSPARC T2:     (Niagara-2)
 
   152  *    SPARC-V9, VIS, ASI_BIS, POPC          (Crypto/hash in SPU)
 
   172  *    SPARC-V9, VIS, ASI_BIS, POPC          (Crypto/hash in SPU)
 
   153  *  UltraSPARC T2+:    (Victoria Falls, etc.)
 
   173  *  UltraSPARC T2+:    (Victoria Falls, etc.)
 
   154  *    SPARC-V9, VIS, VIS2, ASI_BIS, POPC    (Crypto/hash in SPU)
 
   174  *    SPARC-V9, VIS, VIS2, ASI_BIS, POPC    (Crypto/hash in SPU)
 
   155  *
 
   175  *
 
   156  *  UltraSPARC T3:     (Rainbow Falls/S2)
 
   176  *  UltraSPARC T3:     (Rainbow Falls/C2)
 
   157  *    SPARC-V9, VIS, VIS2, ASI_BIS, POPC    (Crypto/hash in SPU)
 
   177  *    SPARC-V9, VIS, VIS2, ASI_BIS, POPC    (Crypto/hash in SPU)
 
   158  *
 
   178  *
 
   159  *  Oracle SPARC T4/T5/M5:  (Core S3)
 
   179  *  Oracle SPARC T4/T5/M5:  (Core C3)
 
   160  *    SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
 
   180  *    SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
 
   161  *    AES, DES, Kasumi, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL
 
   181  *    AES, DES, Kasumi, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL
 
   162  *
 
   182  *
 
   163  *  Oracle SPARC M7:   (Core S4)
 
   183  *  Oracle SPARC M7:   (Core C4)
 
   164  *    SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
 
   184  *    SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
 
   165  *    AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
 
   185  *    AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
 
   166  *    ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK
 
   186  *    ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK
 
   167  *
 
   187  *
 
       
   188  *  Oracle SPARC M8:   (Core C5)
 
       
   189  *    SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
 
       
   190  *    AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
 
       
   191  *    ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK, SPARC6, FPCMPSHL,
 
       
   192  *    DICTUNP, RLE, SHA3, MME
 
       
   193  *
 
       
   194  *    NOTE: Oracle Number support ignored.
 
   168  */
 
   195  */
 
   169   enum {
 
   196   enum {
 
   170     niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk,
 
   197     niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk,
 
   171     niagara2_msk = niagara1_msk | ISA_popc_msk,
 
   198     niagara2_msk = niagara1_msk | ISA_popc_msk,
 
   172 
   199 
   173     core_S2_msk  = niagara2_msk | ISA_vis2_msk,
 
   200     core_C2_msk  = niagara2_msk | ISA_vis2_msk,
 
   174 
   201 
   175     core_S3_msk  = core_S2_msk | ISA_fmaf_msk | ISA_vis3_msk | ISA_hpc_msk |
 
   202     core_C3_msk  = core_C2_msk | ISA_fmaf_msk | ISA_vis3_msk | ISA_hpc_msk |
 
   176         ISA_ima_msk | ISA_aes_msk | ISA_des_msk | ISA_kasumi_msk |
 
   203         ISA_ima_msk | ISA_aes_msk | ISA_des_msk | ISA_kasumi_msk |
 
   177         ISA_camellia_msk | ISA_md5_msk | ISA_sha1_msk | ISA_sha256_msk |
 
   204         ISA_camellia_msk | ISA_md5_msk | ISA_sha1_msk | ISA_sha256_msk |
 
   178         ISA_sha512_msk | ISA_mpmul_msk | ISA_mont_msk | ISA_pause_msk |
 
   205         ISA_sha512_msk | ISA_mpmul_msk | ISA_mont_msk | ISA_pause_msk |
 
   179         ISA_cbcond_msk | ISA_crc32c_msk,
 
   206         ISA_cbcond_msk | ISA_crc32c_msk,
 
   180 
   207 
   181     core_S4_msk  = core_S3_msk - ISA_kasumi_msk |
 
   208     core_C4_msk  = core_C3_msk - ISA_kasumi_msk |
 
   182         ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk |
 
   209         ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk |
 
   183         ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk,
 
   210         ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk,
 
   184 
   211 
       
   212     core_C5_msk = core_C4_msk | ISA_sparc6_msk | ISA_dictunp_msk |
 
       
   213         ISA_fpcmpshl_msk | ISA_rle_msk | ISA_sha3_msk | ISA_mme_msk,
 
       
   214 
   185     ultra_sparc_t1_msk = niagara1_msk,
 
   215     ultra_sparc_t1_msk = niagara1_msk,
 
   186     ultra_sparc_t2_msk = niagara2_msk,
 
   216     ultra_sparc_t2_msk = niagara2_msk,
 
   187     ultra_sparc_t3_msk = core_S2_msk,
 
   217     ultra_sparc_t3_msk = core_C2_msk,
 
   188     ultra_sparc_m5_msk = core_S3_msk,   // NOTE: First out-of-order pipeline.
 
   218     ultra_sparc_m5_msk = core_C3_msk,   // NOTE: First out-of-order pipeline.
 
   189     ultra_sparc_m7_msk = core_S4_msk
 
   219     ultra_sparc_m7_msk = core_C4_msk,
 
       
   220     ultra_sparc_m8_msk = core_C5_msk
 
   190   };
 
   221   };
 
   191 
   222 
   192   static uint _L2_data_cache_line_size;
 
   223   static uint _L2_data_cache_line_size;
 
   193   static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; }
 
   224   static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; }
 
   194 
   225 
   245   static bool has_xmpmul()       { return (_features & ISA_xmpmul_msk) != 0; }
 
   276   static bool has_xmpmul()       { return (_features & ISA_xmpmul_msk) != 0; }
 
   246   static bool has_xmont()        { return (_features & ISA_xmont_msk) != 0; }
 
   277   static bool has_xmont()        { return (_features & ISA_xmont_msk) != 0; }
 
   247   static bool has_pause_nsec()   { return (_features & ISA_pause_nsec_msk) != 0; }
 
   278   static bool has_pause_nsec()   { return (_features & ISA_pause_nsec_msk) != 0; }
 
   248   static bool has_vamask()       { return (_features & ISA_vamask_msk) != 0; }
 
   279   static bool has_vamask()       { return (_features & ISA_vamask_msk) != 0; }
 
   249 
   280 
       
   281   static bool has_sparc6()       { return (_features & ISA_sparc6_msk) != 0; }
 
       
   282   static bool has_dictunp()      { return (_features & ISA_dictunp_msk) != 0; }
 
       
   283   static bool has_fpcmpshl()     { return (_features & ISA_fpcmpshl_msk) != 0; }
 
       
   284   static bool has_rle()          { return (_features & ISA_rle_msk) != 0; }
 
       
   285   static bool has_sha3()         { return (_features & ISA_sha3_msk) != 0; }
 
       
   286   static bool has_athena_plus2() { return (_features & ISA_fjathplus2_msk) != 0; }
 
       
   287   static bool has_vis3c()        { return (_features & ISA_vis3c_msk) != 0; }
 
       
   288   static bool has_sparc5b()      { return (_features & ISA_sparc5b_msk) != 0; }
 
       
   289   static bool has_mme()          { return (_features & ISA_mme_msk) != 0; }
 
       
   290 
   250   static bool has_fast_idiv()    { return (_features & CPU_fast_idiv_msk) != 0; }
 
   291   static bool has_fast_idiv()    { return (_features & CPU_fast_idiv_msk) != 0; }
 
   251   static bool has_fast_rdpc()    { return (_features & CPU_fast_rdpc_msk) != 0; }
 
   292   static bool has_fast_rdpc()    { return (_features & CPU_fast_rdpc_msk) != 0; }
 
   252   static bool has_fast_bis()     { return (_features & CPU_fast_bis_msk) != 0; }
 
   293   static bool has_fast_bis()     { return (_features & CPU_fast_bis_msk) != 0; }
 
   253   static bool has_fast_ld()      { return (_features & CPU_fast_ld_msk) != 0; }
 
   294   static bool has_fast_ld()      { return (_features & CPU_fast_ld_msk) != 0; }
 
   254   static bool has_fast_cmove()   { return (_features & CPU_fast_cmove_msk) != 0; }
 
   295   static bool has_fast_cmove()   { return (_features & CPU_fast_cmove_msk) != 0; }
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