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1 // |
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2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 // Copyright 2012, 2013 SAP AG. All rights reserved. |
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4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 // |
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6 // This code is free software; you can redistribute it and/or modify it |
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7 // under the terms of the GNU General Public License version 2 only, as |
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8 // published by the Free Software Foundation. |
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9 // |
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10 // This code is distributed in the hope that it will be useful, but WITHOUT |
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11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 // version 2 for more details (a copy is included in the LICENSE file that |
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14 // accompanied this code). |
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15 // |
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16 // You should have received a copy of the GNU General Public License version |
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17 // 2 along with this work; if not, write to the Free Software Foundation, |
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18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 // |
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20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 // or visit www.oracle.com if you need additional information or have any |
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22 // questions. |
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23 // |
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24 // |
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25 |
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26 // |
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27 // PPC64 Architecture Description File |
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28 // |
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29 |
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30 //----------REGISTER DEFINITION BLOCK------------------------------------------ |
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31 // This information is used by the matcher and the register allocator to |
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32 // describe individual registers and classes of registers within the target |
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33 // architecture. |
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34 register %{ |
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35 //----------Architecture Description Register Definitions---------------------- |
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36 // General Registers |
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37 // "reg_def" name (register save type, C convention save type, |
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38 // ideal register type, encoding); |
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39 // |
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40 // Register Save Types: |
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41 // |
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42 // NS = No-Save: The register allocator assumes that these registers |
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43 // can be used without saving upon entry to the method, & |
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44 // that they do not need to be saved at call sites. |
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45 // |
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46 // SOC = Save-On-Call: The register allocator assumes that these registers |
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47 // can be used without saving upon entry to the method, |
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48 // but that they must be saved at call sites. |
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49 // These are called "volatiles" on ppc. |
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50 // |
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51 // SOE = Save-On-Entry: The register allocator assumes that these registers |
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52 // must be saved before using them upon entry to the |
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53 // method, but they do not need to be saved at call |
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54 // sites. |
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55 // These are called "nonvolatiles" on ppc. |
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56 // |
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57 // AS = Always-Save: The register allocator assumes that these registers |
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58 // must be saved before using them upon entry to the |
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59 // method, & that they must be saved at call sites. |
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60 // |
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61 // Ideal Register Type is used to determine how to save & restore a |
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62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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64 // |
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65 // The encoding number is the actual bit-pattern placed into the opcodes. |
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66 // |
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67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI |
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68 // Supplement Version 1.7 as of 2003-10-29. |
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69 // |
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70 // For each 64-bit register we must define two registers: the register |
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71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', |
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72 // e.g. R3_H, which is needed by the allocator, but is not used |
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73 // for stores, loads, etc. |
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74 |
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75 // ---------------------------- |
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76 // Integer/Long Registers |
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77 // ---------------------------- |
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78 |
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79 // PPC64 has 32 64-bit integer registers. |
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80 |
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81 // types: v = volatile, nv = non-volatile, s = system |
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82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs |
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83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); |
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84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP |
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85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); |
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86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC |
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87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); |
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88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret |
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89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); |
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90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 |
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91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); |
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92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 |
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93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); |
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94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 |
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95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); |
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96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 |
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97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); |
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98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 |
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99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); |
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100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 |
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101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); |
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102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 |
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103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); |
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104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch |
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105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); |
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106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch |
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107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); |
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108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id |
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109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); |
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110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv |
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111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); |
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112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv |
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113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); |
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114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv |
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115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); |
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116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv |
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117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); |
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118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv |
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119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); |
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120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv |
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121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); |
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122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv |
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123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); |
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124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv |
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125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); |
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126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv |
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127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); |
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128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv |
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129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); |
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130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv |
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131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); |
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132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv |
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133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); |
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134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv |
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135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); |
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136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv |
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137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); |
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138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv |
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139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); |
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140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv |
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141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); |
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142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv |
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143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); |
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144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv |
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145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); |
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146 |
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147 |
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148 // ---------------------------- |
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149 // Float/Double Registers |
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150 // ---------------------------- |
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151 |
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152 // Double Registers |
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153 // The rules of ADL require that double registers be defined in pairs. |
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154 // Each pair must be two 32-bit values, but not necessarily a pair of |
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155 // single float registers. In each pair, ADLC-assigned register numbers |
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156 // must be adjacent, with the lower number even. Finally, when the |
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157 // CPU stores such a register pair to memory, the word associated with |
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158 // the lower ADLC-assigned number must be stored to the lower address. |
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159 |
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160 // PPC64 has 32 64-bit floating-point registers. Each can store a single |
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161 // or double precision floating-point value. |
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162 |
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163 // types: v = volatile, nv = non-volatile, s = system |
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164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch |
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165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); |
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166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret |
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167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); |
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168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 |
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169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); |
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170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 |
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171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); |
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172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 |
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173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); |
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174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 |
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175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); |
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176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 |
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177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); |
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178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 |
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179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); |
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180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 |
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181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); |
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182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 |
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183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); |
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184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 |
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185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); |
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186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 |
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187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); |
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188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 |
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189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); |
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190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 |
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191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); |
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192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv |
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193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); |
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194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv |
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195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); |
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196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv |
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197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); |
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198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv |
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199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); |
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200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv |
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201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); |
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202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv |
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203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); |
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204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv |
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205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); |
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206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv |
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207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); |
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208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv |
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209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); |
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210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv |
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211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); |
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212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv |
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213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); |
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214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv |
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215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); |
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216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv |
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217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); |
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218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv |
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219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); |
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220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv |
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221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); |
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222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv |
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223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); |
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224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv |
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225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); |
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226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv |
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227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); |
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228 |
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229 // ---------------------------- |
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230 // Special Registers |
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231 // ---------------------------- |
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232 |
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233 // Condition Codes Flag Registers |
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234 |
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235 // PPC64 has 8 condition code "registers" which are all contained |
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236 // in the CR register. |
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237 |
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238 // types: v = volatile, nv = non-volatile, s = system |
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239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v |
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240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v |
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241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv |
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242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv |
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243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv |
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244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v |
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245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v |
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246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v |
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247 |
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248 // Special registers of PPC64 |
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249 |
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250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v |
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251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v |
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252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v |
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253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v |
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254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v |
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255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v |
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256 |
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257 |
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258 // ---------------------------- |
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259 // Specify priority of register selection within phases of register |
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260 // allocation. Highest priority is first. A useful heuristic is to |
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261 // give registers a low priority when they are required by machine |
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262 // instructions, like EAX and EDX on I486, and choose no-save registers |
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263 // before save-on-call, & save-on-call before save-on-entry. Registers |
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264 // which participate in fixed calling sequences should come last. |
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265 // Registers which are used as pairs must fall on an even boundary. |
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266 |
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267 // It's worth about 1% on SPEC geomean to get this right. |
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268 |
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269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration |
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270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g. |
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271 // R3_num. Therefore, R3_num may not be (and in reality is not) |
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272 // the same as R3->encoding()! Furthermore, we cannot make any |
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273 // assumptions on ordering, e.g. R3_num may be less than R2_num. |
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274 // Additionally, the function |
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275 // static enum RC rc_class(OptoReg::Name reg ) |
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276 // maps a given <register>_num value to its chunk type (except for flags) |
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277 // and its current implementation relies on chunk0 and chunk1 having a |
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278 // size of 64 each. |
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279 |
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280 // If you change this allocation class, please have a look at the |
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281 // default values for the parameters RoundRobinIntegerRegIntervalStart |
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282 // and RoundRobinFloatRegIntervalStart |
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283 |
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284 alloc_class chunk0 ( |
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285 // Chunk0 contains *all* 64 integer registers halves. |
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286 |
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287 // "non-volatile" registers |
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288 R14, R14_H, |
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289 R15, R15_H, |
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290 R17, R17_H, |
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291 R18, R18_H, |
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292 R19, R19_H, |
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293 R20, R20_H, |
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294 R21, R21_H, |
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295 R22, R22_H, |
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296 R23, R23_H, |
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297 R24, R24_H, |
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298 R25, R25_H, |
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299 R26, R26_H, |
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300 R27, R27_H, |
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301 R28, R28_H, |
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302 R29, R29_H, |
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303 R30, R30_H, |
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304 R31, R31_H, |
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305 |
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306 // scratch/special registers |
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307 R11, R11_H, |
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308 R12, R12_H, |
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309 |
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310 // argument registers |
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311 R10, R10_H, |
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312 R9, R9_H, |
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313 R8, R8_H, |
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314 R7, R7_H, |
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315 R6, R6_H, |
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316 R5, R5_H, |
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317 R4, R4_H, |
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318 R3, R3_H, |
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319 |
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320 // special registers, not available for allocation |
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321 R16, R16_H, // R16_thread |
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322 R13, R13_H, // system thread id |
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323 R2, R2_H, // may be used for TOC |
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324 R1, R1_H, // SP |
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325 R0, R0_H // R0 (scratch) |
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326 ); |
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327 |
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328 // If you change this allocation class, please have a look at the |
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329 // default values for the parameters RoundRobinIntegerRegIntervalStart |
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330 // and RoundRobinFloatRegIntervalStart |
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331 |
|
332 alloc_class chunk1 ( |
|
333 // Chunk1 contains *all* 64 floating-point registers halves. |
|
334 |
|
335 // scratch register |
|
336 F0, F0_H, |
|
337 |
|
338 // argument registers |
|
339 F13, F13_H, |
|
340 F12, F12_H, |
|
341 F11, F11_H, |
|
342 F10, F10_H, |
|
343 F9, F9_H, |
|
344 F8, F8_H, |
|
345 F7, F7_H, |
|
346 F6, F6_H, |
|
347 F5, F5_H, |
|
348 F4, F4_H, |
|
349 F3, F3_H, |
|
350 F2, F2_H, |
|
351 F1, F1_H, |
|
352 |
|
353 // non-volatile registers |
|
354 F14, F14_H, |
|
355 F15, F15_H, |
|
356 F16, F16_H, |
|
357 F17, F17_H, |
|
358 F18, F18_H, |
|
359 F19, F19_H, |
|
360 F20, F20_H, |
|
361 F21, F21_H, |
|
362 F22, F22_H, |
|
363 F23, F23_H, |
|
364 F24, F24_H, |
|
365 F25, F25_H, |
|
366 F26, F26_H, |
|
367 F27, F27_H, |
|
368 F28, F28_H, |
|
369 F29, F29_H, |
|
370 F30, F30_H, |
|
371 F31, F31_H |
|
372 ); |
|
373 |
|
374 alloc_class chunk2 ( |
|
375 // Chunk2 contains *all* 8 condition code registers. |
|
376 |
|
377 CCR0, |
|
378 CCR1, |
|
379 CCR2, |
|
380 CCR3, |
|
381 CCR4, |
|
382 CCR5, |
|
383 CCR6, |
|
384 CCR7 |
|
385 ); |
|
386 |
|
387 alloc_class chunk3 ( |
|
388 // special registers |
|
389 // These registers are not allocated, but used for nodes generated by postalloc expand. |
|
390 SR_XER, |
|
391 SR_LR, |
|
392 SR_CTR, |
|
393 SR_VRSAVE, |
|
394 SR_SPEFSCR, |
|
395 SR_PPR |
|
396 ); |
|
397 |
|
398 //-------Architecture Description Register Classes----------------------- |
|
399 |
|
400 // Several register classes are automatically defined based upon |
|
401 // information in this architecture description. |
|
402 |
|
403 // 1) reg_class inline_cache_reg ( as defined in frame section ) |
|
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) |
|
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) |
|
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) |
|
407 // |
|
408 |
|
409 // ---------------------------- |
|
410 // 32 Bit Register Classes |
|
411 // ---------------------------- |
|
412 |
|
413 // We specify registers twice, once as read/write, and once read-only. |
|
414 // We use the read-only registers for source operands. With this, we |
|
415 // can include preset read only registers in this class, as a hard-coded |
|
416 // '0'-register. (We used to simulate this on ppc.) |
|
417 |
|
418 // 32 bit registers that can be read and written i.e. these registers |
|
419 // can be dest (or src) of normal instructions. |
|
420 reg_class bits32_reg_rw( |
|
421 /*R0*/ // R0 |
|
422 /*R1*/ // SP |
|
423 R2, // TOC |
|
424 R3, |
|
425 R4, |
|
426 R5, |
|
427 R6, |
|
428 R7, |
|
429 R8, |
|
430 R9, |
|
431 R10, |
|
432 R11, |
|
433 R12, |
|
434 /*R13*/ // system thread id |
|
435 R14, |
|
436 R15, |
|
437 /*R16*/ // R16_thread |
|
438 R17, |
|
439 R18, |
|
440 R19, |
|
441 R20, |
|
442 R21, |
|
443 R22, |
|
444 R23, |
|
445 R24, |
|
446 R25, |
|
447 R26, |
|
448 R27, |
|
449 R28, |
|
450 /*R29*/ // global TOC |
|
451 /*R30*/ // Narrow Oop Base |
|
452 R31 |
|
453 ); |
|
454 |
|
455 // 32 bit registers that can only be read i.e. these registers can |
|
456 // only be src of all instructions. |
|
457 reg_class bits32_reg_ro( |
|
458 /*R0*/ // R0 |
|
459 /*R1*/ // SP |
|
460 R2 // TOC |
|
461 R3, |
|
462 R4, |
|
463 R5, |
|
464 R6, |
|
465 R7, |
|
466 R8, |
|
467 R9, |
|
468 R10, |
|
469 R11, |
|
470 R12, |
|
471 /*R13*/ // system thread id |
|
472 R14, |
|
473 R15, |
|
474 /*R16*/ // R16_thread |
|
475 R17, |
|
476 R18, |
|
477 R19, |
|
478 R20, |
|
479 R21, |
|
480 R22, |
|
481 R23, |
|
482 R24, |
|
483 R25, |
|
484 R26, |
|
485 R27, |
|
486 R28, |
|
487 /*R29*/ |
|
488 /*R30*/ // Narrow Oop Base |
|
489 R31 |
|
490 ); |
|
491 |
|
492 // Complement-required-in-pipeline operands for narrow oops. |
|
493 reg_class bits32_reg_ro_not_complement ( |
|
494 /*R0*/ // R0 |
|
495 R1, // SP |
|
496 R2, // TOC |
|
497 R3, |
|
498 R4, |
|
499 R5, |
|
500 R6, |
|
501 R7, |
|
502 R8, |
|
503 R9, |
|
504 R10, |
|
505 R11, |
|
506 R12, |
|
507 /*R13,*/ // system thread id |
|
508 R14, |
|
509 R15, |
|
510 R16, // R16_thread |
|
511 R17, |
|
512 R18, |
|
513 R19, |
|
514 R20, |
|
515 R21, |
|
516 R22, |
|
517 /*R23, |
|
518 R24, |
|
519 R25, |
|
520 R26, |
|
521 R27, |
|
522 R28,*/ |
|
523 /*R29,*/ // TODO: let allocator handle TOC!! |
|
524 /*R30,*/ |
|
525 R31 |
|
526 ); |
|
527 |
|
528 // Complement-required-in-pipeline operands for narrow oops. |
|
529 // See 64-bit declaration. |
|
530 reg_class bits32_reg_ro_complement ( |
|
531 R23, |
|
532 R24, |
|
533 R25, |
|
534 R26, |
|
535 R27, |
|
536 R28 |
|
537 ); |
|
538 |
|
539 reg_class rscratch1_bits32_reg(R11); |
|
540 reg_class rscratch2_bits32_reg(R12); |
|
541 reg_class rarg1_bits32_reg(R3); |
|
542 reg_class rarg2_bits32_reg(R4); |
|
543 reg_class rarg3_bits32_reg(R5); |
|
544 reg_class rarg4_bits32_reg(R6); |
|
545 |
|
546 // ---------------------------- |
|
547 // 64 Bit Register Classes |
|
548 // ---------------------------- |
|
549 // 64-bit build means 64-bit pointers means hi/lo pairs |
|
550 |
|
551 reg_class rscratch1_bits64_reg(R11_H, R11); |
|
552 reg_class rscratch2_bits64_reg(R12_H, R12); |
|
553 reg_class rarg1_bits64_reg(R3_H, R3); |
|
554 reg_class rarg2_bits64_reg(R4_H, R4); |
|
555 reg_class rarg3_bits64_reg(R5_H, R5); |
|
556 reg_class rarg4_bits64_reg(R6_H, R6); |
|
557 // Thread register, 'written' by tlsLoadP, see there. |
|
558 reg_class thread_bits64_reg(R16_H, R16); |
|
559 |
|
560 reg_class r19_bits64_reg(R19_H, R19); |
|
561 |
|
562 // 64 bit registers that can be read and written i.e. these registers |
|
563 // can be dest (or src) of normal instructions. |
|
564 reg_class bits64_reg_rw( |
|
565 /*R0_H, R0*/ // R0 |
|
566 /*R1_H, R1*/ // SP |
|
567 R2_H, R2, // TOC |
|
568 R3_H, R3, |
|
569 R4_H, R4, |
|
570 R5_H, R5, |
|
571 R6_H, R6, |
|
572 R7_H, R7, |
|
573 R8_H, R8, |
|
574 R9_H, R9, |
|
575 R10_H, R10, |
|
576 R11_H, R11, |
|
577 R12_H, R12, |
|
578 /*R13_H, R13*/ // system thread id |
|
579 R14_H, R14, |
|
580 R15_H, R15, |
|
581 /*R16_H, R16*/ // R16_thread |
|
582 R17_H, R17, |
|
583 R18_H, R18, |
|
584 R19_H, R19, |
|
585 R20_H, R20, |
|
586 R21_H, R21, |
|
587 R22_H, R22, |
|
588 R23_H, R23, |
|
589 R24_H, R24, |
|
590 R25_H, R25, |
|
591 R26_H, R26, |
|
592 R27_H, R27, |
|
593 R28_H, R28, |
|
594 /*R29_H, R29*/ |
|
595 /*R30_H, R30*/ |
|
596 R31_H, R31 |
|
597 ); |
|
598 |
|
599 // 64 bit registers used excluding r2, r11 and r12 |
|
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses |
|
601 // r2, r11 and r12 internally. |
|
602 reg_class bits64_reg_leaf_call( |
|
603 /*R0_H, R0*/ // R0 |
|
604 /*R1_H, R1*/ // SP |
|
605 /*R2_H, R2*/ // TOC |
|
606 R3_H, R3, |
|
607 R4_H, R4, |
|
608 R5_H, R5, |
|
609 R6_H, R6, |
|
610 R7_H, R7, |
|
611 R8_H, R8, |
|
612 R9_H, R9, |
|
613 R10_H, R10, |
|
614 /*R11_H, R11*/ |
|
615 /*R12_H, R12*/ |
|
616 /*R13_H, R13*/ // system thread id |
|
617 R14_H, R14, |
|
618 R15_H, R15, |
|
619 /*R16_H, R16*/ // R16_thread |
|
620 R17_H, R17, |
|
621 R18_H, R18, |
|
622 R19_H, R19, |
|
623 R20_H, R20, |
|
624 R21_H, R21, |
|
625 R22_H, R22, |
|
626 R23_H, R23, |
|
627 R24_H, R24, |
|
628 R25_H, R25, |
|
629 R26_H, R26, |
|
630 R27_H, R27, |
|
631 R28_H, R28, |
|
632 /*R29_H, R29*/ |
|
633 /*R30_H, R30*/ |
|
634 R31_H, R31 |
|
635 ); |
|
636 |
|
637 // 64 bit registers used excluding r19. |
|
638 // Used to hold the TOC to avoid collisions with expanded DynamicCall |
|
639 // which uses r19 as inline cache internally and expanded LeafCall which uses |
|
640 // r2, r11 and r12 internally. |
|
641 reg_class bits64_constant_table_base( |
|
642 /*R0_H, R0*/ // R0 |
|
643 /*R1_H, R1*/ // SP |
|
644 /*R2_H, R2*/ // TOC |
|
645 R3_H, R3, |
|
646 R4_H, R4, |
|
647 R5_H, R5, |
|
648 R6_H, R6, |
|
649 R7_H, R7, |
|
650 R8_H, R8, |
|
651 R9_H, R9, |
|
652 R10_H, R10, |
|
653 /*R11_H, R11*/ |
|
654 /*R12_H, R12*/ |
|
655 /*R13_H, R13*/ // system thread id |
|
656 R14_H, R14, |
|
657 R15_H, R15, |
|
658 /*R16_H, R16*/ // R16_thread |
|
659 R17_H, R17, |
|
660 R18_H, R18, |
|
661 /*R19_H, R19*/ |
|
662 R20_H, R20, |
|
663 R21_H, R21, |
|
664 R22_H, R22, |
|
665 R23_H, R23, |
|
666 R24_H, R24, |
|
667 R25_H, R25, |
|
668 R26_H, R26, |
|
669 R27_H, R27, |
|
670 R28_H, R28, |
|
671 /*R29_H, R29*/ |
|
672 /*R30_H, R30*/ |
|
673 R31_H, R31 |
|
674 ); |
|
675 |
|
676 // 64 bit registers that can only be read i.e. these registers can |
|
677 // only be src of all instructions. |
|
678 reg_class bits64_reg_ro( |
|
679 /*R0_H, R0*/ // R0 |
|
680 R1_H, R1, |
|
681 R2_H, R2, // TOC |
|
682 R3_H, R3, |
|
683 R4_H, R4, |
|
684 R5_H, R5, |
|
685 R6_H, R6, |
|
686 R7_H, R7, |
|
687 R8_H, R8, |
|
688 R9_H, R9, |
|
689 R10_H, R10, |
|
690 R11_H, R11, |
|
691 R12_H, R12, |
|
692 /*R13_H, R13*/ // system thread id |
|
693 R14_H, R14, |
|
694 R15_H, R15, |
|
695 R16_H, R16, // R16_thread |
|
696 R17_H, R17, |
|
697 R18_H, R18, |
|
698 R19_H, R19, |
|
699 R20_H, R20, |
|
700 R21_H, R21, |
|
701 R22_H, R22, |
|
702 R23_H, R23, |
|
703 R24_H, R24, |
|
704 R25_H, R25, |
|
705 R26_H, R26, |
|
706 R27_H, R27, |
|
707 R28_H, R28, |
|
708 /*R29_H, R29*/ // TODO: let allocator handle TOC!! |
|
709 /*R30_H, R30,*/ |
|
710 R31_H, R31 |
|
711 ); |
|
712 |
|
713 // Complement-required-in-pipeline operands. |
|
714 reg_class bits64_reg_ro_not_complement ( |
|
715 /*R0_H, R0*/ // R0 |
|
716 R1_H, R1, // SP |
|
717 R2_H, R2, // TOC |
|
718 R3_H, R3, |
|
719 R4_H, R4, |
|
720 R5_H, R5, |
|
721 R6_H, R6, |
|
722 R7_H, R7, |
|
723 R8_H, R8, |
|
724 R9_H, R9, |
|
725 R10_H, R10, |
|
726 R11_H, R11, |
|
727 R12_H, R12, |
|
728 /*R13_H, R13*/ // system thread id |
|
729 R14_H, R14, |
|
730 R15_H, R15, |
|
731 R16_H, R16, // R16_thread |
|
732 R17_H, R17, |
|
733 R18_H, R18, |
|
734 R19_H, R19, |
|
735 R20_H, R20, |
|
736 R21_H, R21, |
|
737 R22_H, R22, |
|
738 /*R23_H, R23, |
|
739 R24_H, R24, |
|
740 R25_H, R25, |
|
741 R26_H, R26, |
|
742 R27_H, R27, |
|
743 R28_H, R28,*/ |
|
744 /*R29_H, R29*/ // TODO: let allocator handle TOC!! |
|
745 /*R30_H, R30,*/ |
|
746 R31_H, R31 |
|
747 ); |
|
748 |
|
749 // Complement-required-in-pipeline operands. |
|
750 // This register mask is used for the trap instructions that implement |
|
751 // the null checks on AIX. The trap instruction first computes the |
|
752 // complement of the value it shall trap on. Because of this, the |
|
753 // instruction can not be scheduled in the same cycle as an other |
|
754 // instruction reading the normal value of the same register. So we |
|
755 // force the value to check into 'bits64_reg_ro_not_complement' |
|
756 // and then copy it to 'bits64_reg_ro_complement' for the trap. |
|
757 reg_class bits64_reg_ro_complement ( |
|
758 R23_H, R23, |
|
759 R24_H, R24, |
|
760 R25_H, R25, |
|
761 R26_H, R26, |
|
762 R27_H, R27, |
|
763 R28_H, R28 |
|
764 ); |
|
765 |
|
766 |
|
767 // ---------------------------- |
|
768 // Special Class for Condition Code Flags Register |
|
769 |
|
770 reg_class int_flags( |
|
771 /*CCR0*/ // scratch |
|
772 /*CCR1*/ // scratch |
|
773 /*CCR2*/ // nv! |
|
774 /*CCR3*/ // nv! |
|
775 /*CCR4*/ // nv! |
|
776 CCR5, |
|
777 CCR6, |
|
778 CCR7 |
|
779 ); |
|
780 |
|
781 reg_class int_flags_CR0(CCR0); |
|
782 reg_class int_flags_CR1(CCR1); |
|
783 reg_class int_flags_CR6(CCR6); |
|
784 reg_class ctr_reg(SR_CTR); |
|
785 |
|
786 // ---------------------------- |
|
787 // Float Register Classes |
|
788 // ---------------------------- |
|
789 |
|
790 reg_class flt_reg( |
|
791 /*F0*/ // scratch |
|
792 F1, |
|
793 F2, |
|
794 F3, |
|
795 F4, |
|
796 F5, |
|
797 F6, |
|
798 F7, |
|
799 F8, |
|
800 F9, |
|
801 F10, |
|
802 F11, |
|
803 F12, |
|
804 F13, |
|
805 F14, // nv! |
|
806 F15, // nv! |
|
807 F16, // nv! |
|
808 F17, // nv! |
|
809 F18, // nv! |
|
810 F19, // nv! |
|
811 F20, // nv! |
|
812 F21, // nv! |
|
813 F22, // nv! |
|
814 F23, // nv! |
|
815 F24, // nv! |
|
816 F25, // nv! |
|
817 F26, // nv! |
|
818 F27, // nv! |
|
819 F28, // nv! |
|
820 F29, // nv! |
|
821 F30, // nv! |
|
822 F31 // nv! |
|
823 ); |
|
824 |
|
825 // Double precision float registers have virtual `high halves' that |
|
826 // are needed by the allocator. |
|
827 reg_class dbl_reg( |
|
828 /*F0, F0_H*/ // scratch |
|
829 F1, F1_H, |
|
830 F2, F2_H, |
|
831 F3, F3_H, |
|
832 F4, F4_H, |
|
833 F5, F5_H, |
|
834 F6, F6_H, |
|
835 F7, F7_H, |
|
836 F8, F8_H, |
|
837 F9, F9_H, |
|
838 F10, F10_H, |
|
839 F11, F11_H, |
|
840 F12, F12_H, |
|
841 F13, F13_H, |
|
842 F14, F14_H, // nv! |
|
843 F15, F15_H, // nv! |
|
844 F16, F16_H, // nv! |
|
845 F17, F17_H, // nv! |
|
846 F18, F18_H, // nv! |
|
847 F19, F19_H, // nv! |
|
848 F20, F20_H, // nv! |
|
849 F21, F21_H, // nv! |
|
850 F22, F22_H, // nv! |
|
851 F23, F23_H, // nv! |
|
852 F24, F24_H, // nv! |
|
853 F25, F25_H, // nv! |
|
854 F26, F26_H, // nv! |
|
855 F27, F27_H, // nv! |
|
856 F28, F28_H, // nv! |
|
857 F29, F29_H, // nv! |
|
858 F30, F30_H, // nv! |
|
859 F31, F31_H // nv! |
|
860 ); |
|
861 |
|
862 %} |
|
863 |
|
864 //----------DEFINITION BLOCK--------------------------------------------------- |
|
865 // Define name --> value mappings to inform the ADLC of an integer valued name |
|
866 // Current support includes integer values in the range [0, 0x7FFFFFFF] |
|
867 // Format: |
|
868 // int_def <name> ( <int_value>, <expression>); |
|
869 // Generated Code in ad_<arch>.hpp |
|
870 // #define <name> (<expression>) |
|
871 // // value == <int_value> |
|
872 // Generated code in ad_<arch>.cpp adlc_verification() |
|
873 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); |
|
874 // |
|
875 definitions %{ |
|
876 // The default cost (of an ALU instruction). |
|
877 int_def DEFAULT_COST_LOW ( 30, 30); |
|
878 int_def DEFAULT_COST ( 100, 100); |
|
879 int_def HUGE_COST (1000000, 1000000); |
|
880 |
|
881 // Memory refs |
|
882 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); |
|
883 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); |
|
884 |
|
885 // Branches are even more expensive. |
|
886 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); |
|
887 int_def CALL_COST ( 1300, DEFAULT_COST * 13); |
|
888 %} |
|
889 |
|
890 |
|
891 //----------SOURCE BLOCK------------------------------------------------------- |
|
892 // This is a block of C++ code which provides values, functions, and |
|
893 // definitions necessary in the rest of the architecture description. |
|
894 source_hpp %{ |
|
895 // Returns true if Node n is followed by a MemBar node that |
|
896 // will do an acquire. If so, this node must not do the acquire |
|
897 // operation. |
|
898 bool followed_by_acquire(const Node *n); |
|
899 %} |
|
900 |
|
901 source %{ |
|
902 |
|
903 // Optimize load-acquire. |
|
904 // |
|
905 // Check if acquire is unnecessary due to following operation that does |
|
906 // acquire anyways. |
|
907 // Walk the pattern: |
|
908 // |
|
909 // n: Load.acq |
|
910 // | |
|
911 // MemBarAcquire |
|
912 // | | |
|
913 // Proj(ctrl) Proj(mem) |
|
914 // | | |
|
915 // MemBarRelease/Volatile |
|
916 // |
|
917 bool followed_by_acquire(const Node *load) { |
|
918 assert(load->is_Load(), "So far implemented only for loads."); |
|
919 |
|
920 // Find MemBarAcquire. |
|
921 const Node *mba = NULL; |
|
922 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { |
|
923 const Node *out = load->fast_out(i); |
|
924 if (out->Opcode() == Op_MemBarAcquire) { |
|
925 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. |
|
926 mba = out; |
|
927 break; |
|
928 } |
|
929 } |
|
930 if (!mba) return false; |
|
931 |
|
932 // Find following MemBar node. |
|
933 // |
|
934 // The following node must be reachable by control AND memory |
|
935 // edge to assure no other operations are in between the two nodes. |
|
936 // |
|
937 // So first get the Proj node, mem_proj, to use it to iterate forward. |
|
938 Node *mem_proj = NULL; |
|
939 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { |
|
940 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found |
|
941 assert(mem_proj->is_Proj(), "only projections here"); |
|
942 ProjNode *proj = mem_proj->as_Proj(); |
|
943 if (proj->_con == TypeFunc::Memory && |
|
944 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only |
|
945 break; |
|
946 } |
|
947 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); |
|
948 |
|
949 // Search MemBar behind Proj. If there are other memory operations |
|
950 // behind the Proj we lost. |
|
951 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { |
|
952 Node *x = mem_proj->fast_out(j); |
|
953 // Proj might have an edge to a store or load node which precedes the membar. |
|
954 if (x->is_Mem()) return false; |
|
955 |
|
956 // On PPC64 release and volatile are implemented by an instruction |
|
957 // that also has acquire semantics. I.e. there is no need for an |
|
958 // acquire before these. |
|
959 int xop = x->Opcode(); |
|
960 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { |
|
961 // Make sure we're not missing Call/Phi/MergeMem by checking |
|
962 // control edges. The control edge must directly lead back |
|
963 // to the MemBarAcquire |
|
964 Node *ctrl_proj = x->in(0); |
|
965 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { |
|
966 return true; |
|
967 } |
|
968 } |
|
969 } |
|
970 |
|
971 return false; |
|
972 } |
|
973 |
|
974 #define __ _masm. |
|
975 |
|
976 // Tertiary op of a LoadP or StoreP encoding. |
|
977 #define REGP_OP true |
|
978 |
|
979 // **************************************************************************** |
|
980 |
|
981 // REQUIRED FUNCTIONALITY |
|
982 |
|
983 // !!!!! Special hack to get all type of calls to specify the byte offset |
|
984 // from the start of the call to the point where the return address |
|
985 // will point. |
|
986 |
|
987 // PPC port: Removed use of lazy constant construct. |
|
988 |
|
989 int MachCallStaticJavaNode::ret_addr_offset() { |
|
990 // It's only a single branch-and-link instruction. |
|
991 return 4; |
|
992 } |
|
993 |
|
994 int MachCallDynamicJavaNode::ret_addr_offset() { |
|
995 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use |
|
996 // postalloc expanded calls if we use inline caches and do not update method data. |
|
997 if (UseInlineCaches) |
|
998 return 4; |
|
999 |
|
1000 int vtable_index = this->_vtable_index; |
|
1001 if (vtable_index < 0) { |
|
1002 // Must be invalid_vtable_index, not nonvirtual_vtable_index. |
|
1003 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
|
1004 return 12; |
|
1005 } else { |
|
1006 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
1007 return 24; |
|
1008 } |
|
1009 } |
|
1010 |
|
1011 int MachCallRuntimeNode::ret_addr_offset() { |
|
1012 return 40; |
|
1013 } |
|
1014 |
|
1015 //============================================================================= |
|
1016 |
|
1017 // condition code conversions |
|
1018 |
|
1019 static int cc_to_boint(int cc) { |
|
1020 return Assembler::bcondCRbiIs0 | (cc & 8); |
|
1021 } |
|
1022 |
|
1023 static int cc_to_inverse_boint(int cc) { |
|
1024 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); |
|
1025 } |
|
1026 |
|
1027 static int cc_to_biint(int cc, int flags_reg) { |
|
1028 return (flags_reg << 2) | (cc & 3); |
|
1029 } |
|
1030 |
|
1031 //============================================================================= |
|
1032 |
|
1033 // Compute padding required for nodes which need alignment. The padding |
|
1034 // is the number of bytes (not instructions) which will be inserted before |
|
1035 // the instruction. The padding must match the size of a NOP instruction. |
|
1036 |
|
1037 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { |
|
1038 return (3*4-current_offset)&31; |
|
1039 } |
|
1040 |
|
1041 int string_indexOf_imm1Node::compute_padding(int current_offset) const { |
|
1042 return (2*4-current_offset)&31; |
|
1043 } |
|
1044 |
|
1045 int string_indexOf_immNode::compute_padding(int current_offset) const { |
|
1046 return (3*4-current_offset)&31; |
|
1047 } |
|
1048 |
|
1049 int string_indexOfNode::compute_padding(int current_offset) const { |
|
1050 return (1*4-current_offset)&31; |
|
1051 } |
|
1052 |
|
1053 int string_compareNode::compute_padding(int current_offset) const { |
|
1054 return (4*4-current_offset)&31; |
|
1055 } |
|
1056 |
|
1057 int string_equals_immNode::compute_padding(int current_offset) const { |
|
1058 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). |
|
1059 return (2*4-current_offset)&31; |
|
1060 } |
|
1061 |
|
1062 int string_equalsNode::compute_padding(int current_offset) const { |
|
1063 return (7*4-current_offset)&31; |
|
1064 } |
|
1065 |
|
1066 int inlineCallClearArrayNode::compute_padding(int current_offset) const { |
|
1067 return (2*4-current_offset)&31; |
|
1068 } |
|
1069 |
|
1070 //============================================================================= |
|
1071 |
|
1072 // Indicate if the safepoint node needs the polling page as an input. |
|
1073 bool SafePointNode::needs_polling_address_input() { |
|
1074 // The address is loaded from thread by a seperate node. |
|
1075 return true; |
|
1076 } |
|
1077 |
|
1078 //============================================================================= |
|
1079 |
|
1080 // Emit an interrupt that is caught by the debugger (for debugging compiler). |
|
1081 void emit_break(CodeBuffer &cbuf) { |
|
1082 MacroAssembler _masm(&cbuf); |
|
1083 __ illtrap(); |
|
1084 } |
|
1085 |
|
1086 #ifndef PRODUCT |
|
1087 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1088 st->print("BREAKPOINT"); |
|
1089 } |
|
1090 #endif |
|
1091 |
|
1092 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1093 emit_break(cbuf); |
|
1094 } |
|
1095 |
|
1096 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { |
|
1097 return MachNode::size(ra_); |
|
1098 } |
|
1099 |
|
1100 //============================================================================= |
|
1101 |
|
1102 void emit_nop(CodeBuffer &cbuf) { |
|
1103 MacroAssembler _masm(&cbuf); |
|
1104 __ nop(); |
|
1105 } |
|
1106 |
|
1107 static inline void emit_long(CodeBuffer &cbuf, int value) { |
|
1108 *((int*)(cbuf.insts_end())) = value; |
|
1109 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); |
|
1110 } |
|
1111 |
|
1112 //============================================================================= |
|
1113 |
|
1114 // Emit a trampoline stub for a call to a target which is too far away. |
|
1115 // |
|
1116 // code sequences: |
|
1117 // |
|
1118 // call-site: |
|
1119 // branch-and-link to <destination> or <trampoline stub> |
|
1120 // |
|
1121 // Related trampoline stub for this call-site in the stub section: |
|
1122 // load the call target from the constant pool |
|
1123 // branch via CTR (LR/link still points to the call-site above) |
|
1124 |
|
1125 const uint trampoline_stub_size = 6 * BytesPerInstWord; |
|
1126 |
|
1127 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { |
|
1128 // Start the stub. |
|
1129 address stub = __ start_a_stub(Compile::MAX_stubs_size/2); |
|
1130 if (stub == NULL) { |
|
1131 Compile::current()->env()->record_out_of_memory_failure(); |
|
1132 return; |
|
1133 } |
|
1134 |
|
1135 // For java_to_interp stubs we use R11_scratch1 as scratch register |
|
1136 // and in call trampoline stubs we use R12_scratch2. This way we |
|
1137 // can distinguish them (see is_NativeCallTrampolineStub_at()). |
|
1138 Register reg_scratch = R12_scratch2; |
|
1139 |
|
1140 // Create a trampoline stub relocation which relates this trampoline stub |
|
1141 // with the call instruction at insts_call_instruction_offset in the |
|
1142 // instructions code-section. |
|
1143 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); |
|
1144 const int stub_start_offset = __ offset(); |
|
1145 |
|
1146 // Now, create the trampoline stub's code: |
|
1147 // - load the TOC |
|
1148 // - load the call target from the constant pool |
|
1149 // - call |
|
1150 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); |
|
1151 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); |
|
1152 __ mtctr(reg_scratch); |
|
1153 __ bctr(); |
|
1154 |
|
1155 const address stub_start_addr = __ addr_at(stub_start_offset); |
|
1156 |
|
1157 // FIXME: Assert that the trampoline stub can be identified and patched. |
|
1158 |
|
1159 // Assert that the encoded destination_toc_offset can be identified and that it is correct. |
|
1160 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), |
|
1161 "encoded offset into the constant pool must match"); |
|
1162 // Trampoline_stub_size should be good. |
|
1163 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); |
|
1164 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); |
|
1165 |
|
1166 // End the stub. |
|
1167 __ end_a_stub(); |
|
1168 } |
|
1169 |
|
1170 // Size of trampoline stub, this doesn't need to be accurate but it must |
|
1171 // be larger or equal to the real size of the stub. |
|
1172 // Used for optimization in Compile::Shorten_branches. |
|
1173 uint size_call_trampoline() { |
|
1174 return trampoline_stub_size; |
|
1175 } |
|
1176 |
|
1177 // Number of relocation entries needed by trampoline stub. |
|
1178 // Used for optimization in Compile::Shorten_branches. |
|
1179 uint reloc_call_trampoline() { |
|
1180 return 5; |
|
1181 } |
|
1182 |
|
1183 //============================================================================= |
|
1184 |
|
1185 // Emit an inline branch-and-link call and a related trampoline stub. |
|
1186 // |
|
1187 // code sequences: |
|
1188 // |
|
1189 // call-site: |
|
1190 // branch-and-link to <destination> or <trampoline stub> |
|
1191 // |
|
1192 // Related trampoline stub for this call-site in the stub section: |
|
1193 // load the call target from the constant pool |
|
1194 // branch via CTR (LR/link still points to the call-site above) |
|
1195 // |
|
1196 |
|
1197 typedef struct { |
|
1198 int insts_call_instruction_offset; |
|
1199 int ret_addr_offset; |
|
1200 } EmitCallOffsets; |
|
1201 |
|
1202 // Emit a branch-and-link instruction that branches to a trampoline. |
|
1203 // - Remember the offset of the branch-and-link instruction. |
|
1204 // - Add a relocation at the branch-and-link instruction. |
|
1205 // - Emit a branch-and-link. |
|
1206 // - Remember the return pc offset. |
|
1207 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { |
|
1208 EmitCallOffsets offsets = { -1, -1 }; |
|
1209 const int start_offset = __ offset(); |
|
1210 offsets.insts_call_instruction_offset = __ offset(); |
|
1211 |
|
1212 // No entry point given, use the current pc. |
|
1213 if (entry_point == NULL) entry_point = __ pc(); |
|
1214 |
|
1215 if (!Compile::current()->in_scratch_emit_size()) { |
|
1216 // Put the entry point as a constant into the constant pool. |
|
1217 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); |
|
1218 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); |
|
1219 |
|
1220 // Emit the trampoline stub which will be related to the branch-and-link below. |
|
1221 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); |
|
1222 __ relocate(rtype); |
|
1223 } |
|
1224 |
|
1225 // Note: At this point we do not have the address of the trampoline |
|
1226 // stub, and the entry point might be too far away for bl, so __ pc() |
|
1227 // serves as dummy and the bl will be patched later. |
|
1228 __ bl((address) __ pc()); |
|
1229 |
|
1230 offsets.ret_addr_offset = __ offset() - start_offset; |
|
1231 |
|
1232 return offsets; |
|
1233 } |
|
1234 |
|
1235 //============================================================================= |
|
1236 |
|
1237 // Factory for creating loadConL* nodes for large/small constant pool. |
|
1238 |
|
1239 static inline jlong replicate_immF(float con) { |
|
1240 // Replicate float con 2 times and pack into vector. |
|
1241 int val = *((int*)&con); |
|
1242 jlong lval = val; |
|
1243 lval = (lval << 32) | (lval & 0xFFFFFFFFl); |
|
1244 return lval; |
|
1245 } |
|
1246 |
|
1247 //============================================================================= |
|
1248 |
|
1249 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); |
|
1250 int Compile::ConstantTable::calculate_table_base_offset() const { |
|
1251 return 0; // absolute addressing, no offset |
|
1252 } |
|
1253 |
|
1254 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } |
|
1255 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
|
1256 Compile *C = ra_->C; |
|
1257 |
|
1258 iRegPdstOper *op_dst = new (C) iRegPdstOper(); |
|
1259 MachNode *m1 = new (C) loadToc_hiNode(); |
|
1260 MachNode *m2 = new (C) loadToc_loNode(); |
|
1261 |
|
1262 m1->add_req(NULL); |
|
1263 m2->add_req(NULL, m1); |
|
1264 m1->_opnds[0] = op_dst; |
|
1265 m2->_opnds[0] = op_dst; |
|
1266 m2->_opnds[1] = op_dst; |
|
1267 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
1268 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
1269 nodes->push(m1); |
|
1270 nodes->push(m2); |
|
1271 } |
|
1272 |
|
1273 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
|
1274 // Is postalloc expanded. |
|
1275 ShouldNotReachHere(); |
|
1276 } |
|
1277 |
|
1278 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { |
|
1279 return 0; |
|
1280 } |
|
1281 |
|
1282 #ifndef PRODUCT |
|
1283 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
|
1284 st->print("-- \t// MachConstantBaseNode (empty encoding)"); |
|
1285 } |
|
1286 #endif |
|
1287 |
|
1288 //============================================================================= |
|
1289 |
|
1290 #ifndef PRODUCT |
|
1291 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1292 Compile* C = ra_->C; |
|
1293 const long framesize = C->frame_slots() << LogBytesPerInt; |
|
1294 |
|
1295 st->print("PROLOG\n\t"); |
|
1296 if (C->need_stack_bang(framesize)) { |
|
1297 st->print("stack_overflow_check\n\t"); |
|
1298 } |
|
1299 |
|
1300 if (!false /* TODO: PPC port C->is_frameless_method()*/) { |
|
1301 st->print("save return pc\n\t"); |
|
1302 st->print("push frame %d\n\t", -framesize); |
|
1303 } |
|
1304 } |
|
1305 #endif |
|
1306 |
|
1307 // Macro used instead of the common __ to emulate the pipes of PPC. |
|
1308 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the |
|
1309 // micro scheduler to cope with "hand written" assembler like in the prolog. Though |
|
1310 // still no scheduling of this code is possible, the micro scheduler is aware of the |
|
1311 // code and can update its internal data. The following mechanism is used to achieve this: |
|
1312 // The micro scheduler calls size() of each compound node during scheduling. size() does a |
|
1313 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. |
|
1314 #if 0 // TODO: PPC port |
|
1315 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ |
|
1316 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ |
|
1317 _masm. |
|
1318 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ |
|
1319 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) |
|
1320 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ |
|
1321 C->hb_scheduling()->_pdScheduling->advance_offset |
|
1322 #else |
|
1323 #define ___(op) if (UsePower6SchedulerPPC64) \ |
|
1324 Unimplemented(); \ |
|
1325 _masm. |
|
1326 #define ___stop if (UsePower6SchedulerPPC64) \ |
|
1327 Unimplemented() |
|
1328 #define ___advance if (UsePower6SchedulerPPC64) \ |
|
1329 Unimplemented() |
|
1330 #endif |
|
1331 |
|
1332 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1333 Compile* C = ra_->C; |
|
1334 MacroAssembler _masm(&cbuf); |
|
1335 |
|
1336 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; |
|
1337 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); |
|
1338 |
|
1339 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; |
|
1340 |
|
1341 const Register return_pc = R20; // Must match return_addr() in frame section. |
|
1342 const Register callers_sp = R21; |
|
1343 const Register push_frame_temp = R22; |
|
1344 const Register toc_temp = R23; |
|
1345 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); |
|
1346 |
|
1347 if (method_is_frameless) { |
|
1348 // Add nop at beginning of all frameless methods to prevent any |
|
1349 // oop instructions from getting overwritten by make_not_entrant |
|
1350 // (patching attempt would fail). |
|
1351 ___(nop) nop(); |
|
1352 } else { |
|
1353 // Get return pc. |
|
1354 ___(mflr) mflr(return_pc); |
|
1355 } |
|
1356 |
|
1357 // Calls to C2R adapters often do not accept exceptional returns. |
|
1358 // We require that their callers must bang for them. But be |
|
1359 // careful, because some VM calls (such as call site linkage) can |
|
1360 // use several kilobytes of stack. But the stack safety zone should |
|
1361 // account for that. See bugs 4446381, 4468289, 4497237. |
|
1362 if (C->need_stack_bang(framesize) && UseStackBanging) { |
|
1363 // Unfortunately we cannot use the function provided in |
|
1364 // assembler.cpp as we have to emulate the pipes. So I had to |
|
1365 // insert the code of generate_stack_overflow_check(), see |
|
1366 // assembler.cpp for some illuminative comments. |
|
1367 const int page_size = os::vm_page_size(); |
|
1368 int bang_end = StackShadowPages*page_size; |
|
1369 |
|
1370 // This is how far the previous frame's stack banging extended. |
|
1371 const int bang_end_safe = bang_end; |
|
1372 |
|
1373 if (framesize > page_size) { |
|
1374 bang_end += framesize; |
|
1375 } |
|
1376 |
|
1377 int bang_offset = bang_end_safe; |
|
1378 |
|
1379 while (bang_offset <= bang_end) { |
|
1380 // Need at least one stack bang at end of shadow zone. |
|
1381 |
|
1382 // Again I had to copy code, this time from assembler_ppc64.cpp, |
|
1383 // bang_stack_with_offset - see there for comments. |
|
1384 |
|
1385 // Stack grows down, caller passes positive offset. |
|
1386 assert(bang_offset > 0, "must bang with positive offset"); |
|
1387 |
|
1388 long stdoffset = -bang_offset; |
|
1389 |
|
1390 if (Assembler::is_simm(stdoffset, 16)) { |
|
1391 // Signed 16 bit offset, a simple std is ok. |
|
1392 if (UseLoadInstructionsForStackBangingPPC64) { |
|
1393 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); |
|
1394 } else { |
|
1395 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); |
|
1396 } |
|
1397 } else if (Assembler::is_simm(stdoffset, 31)) { |
|
1398 // Use largeoffset calculations for addis & ld/std. |
|
1399 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); |
|
1400 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); |
|
1401 |
|
1402 Register tmp = R11; |
|
1403 ___(addis) addis(tmp, R1_SP, hi); |
|
1404 if (UseLoadInstructionsForStackBangingPPC64) { |
|
1405 ___(ld) ld(R0, lo, tmp); |
|
1406 } else { |
|
1407 ___(std) std(R0, lo, tmp); |
|
1408 } |
|
1409 } else { |
|
1410 ShouldNotReachHere(); |
|
1411 } |
|
1412 |
|
1413 bang_offset += page_size; |
|
1414 } |
|
1415 // R11 trashed |
|
1416 } // C->need_stack_bang(framesize) && UseStackBanging |
|
1417 |
|
1418 unsigned int bytes = (unsigned int)framesize; |
|
1419 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); |
|
1420 ciMethod *currMethod = C -> method(); |
|
1421 |
|
1422 // Optimized version for most common case. |
|
1423 if (UsePower6SchedulerPPC64 && |
|
1424 !method_is_frameless && Assembler::is_simm((int)(-(_abi(lr) + offset)), 16) && |
|
1425 !(false /* ConstantsALot TODO: PPC port*/)) { |
|
1426 ___(or) mr(callers_sp, R1_SP); |
|
1427 ___(addi) addi(R1_SP, R1_SP, -offset); |
|
1428 ___stop; // Emulator won't recognize dependency. |
|
1429 ___(std) std(return_pc, _abi(lr) + offset, R1_SP); |
|
1430 ___(std) std(callers_sp, 0, R1_SP); |
|
1431 return; |
|
1432 } |
|
1433 |
|
1434 if (!method_is_frameless) { |
|
1435 // Get callers sp. |
|
1436 ___(or) mr(callers_sp, R1_SP); |
|
1437 |
|
1438 // Push method's frame, modifies SP. |
|
1439 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); |
|
1440 // The ABI is already accounted for in 'framesize' via the |
|
1441 // 'out_preserve' area. |
|
1442 Register tmp = push_frame_temp; |
|
1443 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). |
|
1444 if (Assembler::is_simm(-offset, 16)) { |
|
1445 ___(stdu) stdu(R1_SP, -offset, R1_SP); |
|
1446 } else { |
|
1447 long x = -offset; |
|
1448 // Had to insert load_const(tmp, -offset). |
|
1449 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); |
|
1450 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); |
|
1451 ___(rldicr) sldi(tmp, tmp, 32); |
|
1452 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); |
|
1453 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); |
|
1454 |
|
1455 ___(stdux) stdux(R1_SP, R1_SP, tmp); |
|
1456 } |
|
1457 } |
|
1458 #if 0 // TODO: PPC port |
|
1459 // For testing large constant pools, emit a lot of constants to constant pool. |
|
1460 // "Randomize" const_size. |
|
1461 if (ConstantsALot) { |
|
1462 const int num_consts = const_size(); |
|
1463 for (int i = 0; i < num_consts; i++) { |
|
1464 __ long_constant(0xB0B5B00BBABE); |
|
1465 } |
|
1466 } |
|
1467 #endif |
|
1468 if (!method_is_frameless) { |
|
1469 // Save return pc. |
|
1470 ___(std) std(return_pc, _abi(lr), callers_sp); |
|
1471 } |
|
1472 } |
|
1473 #undef ___ |
|
1474 #undef ___stop |
|
1475 |
|
1476 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { |
|
1477 // Variable size. determine dynamically. |
|
1478 return MachNode::size(ra_); |
|
1479 } |
|
1480 |
|
1481 int MachPrologNode::reloc() const { |
|
1482 // Return number of relocatable values contained in this instruction. |
|
1483 return 1; // 1 reloc entry for load_const(toc). |
|
1484 } |
|
1485 |
|
1486 //============================================================================= |
|
1487 |
|
1488 #ifndef PRODUCT |
|
1489 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1490 Compile* C = ra_->C; |
|
1491 |
|
1492 st->print("EPILOG\n\t"); |
|
1493 st->print("restore return pc\n\t"); |
|
1494 st->print("pop frame\n\t"); |
|
1495 |
|
1496 if (do_polling() && C->is_method_compilation()) { |
|
1497 st->print("touch polling page\n\t"); |
|
1498 } |
|
1499 } |
|
1500 #endif |
|
1501 |
|
1502 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1503 Compile* C = ra_->C; |
|
1504 MacroAssembler _masm(&cbuf); |
|
1505 |
|
1506 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; |
|
1507 assert(framesize >= 0, "negative frame-size?"); |
|
1508 |
|
1509 const bool method_needs_polling = do_polling() && C->is_method_compilation(); |
|
1510 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; |
|
1511 const Register return_pc = R11; |
|
1512 const Register polling_page = R12; |
|
1513 |
|
1514 if (!method_is_frameless) { |
|
1515 // Restore return pc relative to callers' sp. |
|
1516 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); |
|
1517 } |
|
1518 |
|
1519 if (method_needs_polling) { |
|
1520 if (LoadPollAddressFromThread) { |
|
1521 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); |
|
1522 Unimplemented(); |
|
1523 } else { |
|
1524 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() |
|
1525 } |
|
1526 } |
|
1527 |
|
1528 if (!method_is_frameless) { |
|
1529 // Move return pc to LR. |
|
1530 __ mtlr(return_pc); |
|
1531 // Pop frame (fixed frame-size). |
|
1532 __ addi(R1_SP, R1_SP, (int)framesize); |
|
1533 } |
|
1534 |
|
1535 if (method_needs_polling) { |
|
1536 // We need to mark the code position where the load from the safepoint |
|
1537 // polling page was emitted as relocInfo::poll_return_type here. |
|
1538 __ relocate(relocInfo::poll_return_type); |
|
1539 __ load_from_polling_page(polling_page); |
|
1540 } |
|
1541 } |
|
1542 |
|
1543 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { |
|
1544 // Variable size. Determine dynamically. |
|
1545 return MachNode::size(ra_); |
|
1546 } |
|
1547 |
|
1548 int MachEpilogNode::reloc() const { |
|
1549 // Return number of relocatable values contained in this instruction. |
|
1550 return 1; // 1 for load_from_polling_page. |
|
1551 } |
|
1552 |
|
1553 const Pipeline * MachEpilogNode::pipeline() const { |
|
1554 return MachNode::pipeline_class(); |
|
1555 } |
|
1556 |
|
1557 // This method seems to be obsolete. It is declared in machnode.hpp |
|
1558 // and defined in all *.ad files, but it is never called. Should we |
|
1559 // get rid of it? |
|
1560 int MachEpilogNode::safepoint_offset() const { |
|
1561 assert(do_polling(), "no return for this epilog node"); |
|
1562 return 0; |
|
1563 } |
|
1564 |
|
1565 #if 0 // TODO: PPC port |
|
1566 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
|
1567 MacroAssembler _masm(&cbuf); |
|
1568 if (LoadPollAddressFromThread) { |
|
1569 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); |
|
1570 } else { |
|
1571 _masm.nop(); |
|
1572 } |
|
1573 } |
|
1574 |
|
1575 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { |
|
1576 if (LoadPollAddressFromThread) { |
|
1577 return 4; |
|
1578 } else { |
|
1579 return 4; |
|
1580 } |
|
1581 } |
|
1582 |
|
1583 #ifndef PRODUCT |
|
1584 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
|
1585 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); |
|
1586 } |
|
1587 #endif |
|
1588 |
|
1589 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { |
|
1590 return RSCRATCH1_BITS64_REG_mask(); |
|
1591 } |
|
1592 #endif // PPC port |
|
1593 |
|
1594 // ============================================================================= |
|
1595 |
|
1596 // Figure out which register class each belongs in: rc_int, rc_float or |
|
1597 // rc_stack. |
|
1598 enum RC { rc_bad, rc_int, rc_float, rc_stack }; |
|
1599 |
|
1600 static enum RC rc_class(OptoReg::Name reg) { |
|
1601 // Return the register class for the given register. The given register |
|
1602 // reg is a <register>_num value, which is an index into the MachRegisterNumbers |
|
1603 // enumeration in adGlobals_ppc64.hpp. |
|
1604 |
|
1605 if (reg == OptoReg::Bad) return rc_bad; |
|
1606 |
|
1607 // We have 64 integer register halves, starting at index 0. |
|
1608 if (reg < 64) return rc_int; |
|
1609 |
|
1610 // We have 64 floating-point register halves, starting at index 64. |
|
1611 if (reg < 64+64) return rc_float; |
|
1612 |
|
1613 // Between float regs & stack are the flags regs. |
|
1614 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); |
|
1615 |
|
1616 return rc_stack; |
|
1617 } |
|
1618 |
|
1619 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, |
|
1620 bool do_print, Compile* C, outputStream *st) { |
|
1621 |
|
1622 assert(opcode == Assembler::LD_OPCODE || |
|
1623 opcode == Assembler::STD_OPCODE || |
|
1624 opcode == Assembler::LWZ_OPCODE || |
|
1625 opcode == Assembler::STW_OPCODE || |
|
1626 opcode == Assembler::LFD_OPCODE || |
|
1627 opcode == Assembler::STFD_OPCODE || |
|
1628 opcode == Assembler::LFS_OPCODE || |
|
1629 opcode == Assembler::STFS_OPCODE, |
|
1630 "opcode not supported"); |
|
1631 |
|
1632 if (cbuf) { |
|
1633 int d = |
|
1634 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? |
|
1635 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) |
|
1636 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. |
|
1637 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); |
|
1638 } |
|
1639 #ifndef PRODUCT |
|
1640 else if (do_print) { |
|
1641 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", |
|
1642 op_str, |
|
1643 Matcher::regName[reg], |
|
1644 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); |
|
1645 } |
|
1646 #endif |
|
1647 return 4; // size |
|
1648 } |
|
1649 |
|
1650 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { |
|
1651 Compile* C = ra_->C; |
|
1652 |
|
1653 // Get registers to move. |
|
1654 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); |
|
1655 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); |
|
1656 OptoReg::Name dst_hi = ra_->get_reg_second(this); |
|
1657 OptoReg::Name dst_lo = ra_->get_reg_first(this); |
|
1658 |
|
1659 enum RC src_hi_rc = rc_class(src_hi); |
|
1660 enum RC src_lo_rc = rc_class(src_lo); |
|
1661 enum RC dst_hi_rc = rc_class(dst_hi); |
|
1662 enum RC dst_lo_rc = rc_class(dst_lo); |
|
1663 |
|
1664 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); |
|
1665 if (src_hi != OptoReg::Bad) |
|
1666 assert((src_lo&1)==0 && src_lo+1==src_hi && |
|
1667 (dst_lo&1)==0 && dst_lo+1==dst_hi, |
|
1668 "expected aligned-adjacent pairs"); |
|
1669 // Generate spill code! |
|
1670 int size = 0; |
|
1671 |
|
1672 if (src_lo == dst_lo && src_hi == dst_hi) |
|
1673 return size; // Self copy, no move. |
|
1674 |
|
1675 // -------------------------------------- |
|
1676 // Memory->Memory Spill. Use R0 to hold the value. |
|
1677 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { |
|
1678 int src_offset = ra_->reg2offset(src_lo); |
|
1679 int dst_offset = ra_->reg2offset(dst_lo); |
|
1680 if (src_hi != OptoReg::Bad) { |
|
1681 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, |
|
1682 "expected same type of move for high parts"); |
|
1683 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); |
|
1684 if (!cbuf && !do_size) st->print("\n\t"); |
|
1685 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); |
|
1686 } else { |
|
1687 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); |
|
1688 if (!cbuf && !do_size) st->print("\n\t"); |
|
1689 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); |
|
1690 } |
|
1691 return size; |
|
1692 } |
|
1693 |
|
1694 // -------------------------------------- |
|
1695 // Check for float->int copy; requires a trip through memory. |
|
1696 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { |
|
1697 Unimplemented(); |
|
1698 } |
|
1699 |
|
1700 // -------------------------------------- |
|
1701 // Check for integer reg-reg copy. |
|
1702 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { |
|
1703 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); |
|
1704 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); |
|
1705 size = (Rsrc != Rdst) ? 4 : 0; |
|
1706 |
|
1707 if (cbuf) { |
|
1708 MacroAssembler _masm(cbuf); |
|
1709 if (size) { |
|
1710 __ mr(Rdst, Rsrc); |
|
1711 } |
|
1712 } |
|
1713 #ifndef PRODUCT |
|
1714 else if (!do_size) { |
|
1715 if (size) { |
|
1716 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
1717 } else { |
|
1718 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
1719 } |
|
1720 } |
|
1721 #endif |
|
1722 return size; |
|
1723 } |
|
1724 |
|
1725 // Check for integer store. |
|
1726 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { |
|
1727 int dst_offset = ra_->reg2offset(dst_lo); |
|
1728 if (src_hi != OptoReg::Bad) { |
|
1729 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, |
|
1730 "expected same type of move for high parts"); |
|
1731 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1732 } else { |
|
1733 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1734 } |
|
1735 return size; |
|
1736 } |
|
1737 |
|
1738 // Check for integer load. |
|
1739 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { |
|
1740 int src_offset = ra_->reg2offset(src_lo); |
|
1741 if (src_hi != OptoReg::Bad) { |
|
1742 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, |
|
1743 "expected same type of move for high parts"); |
|
1744 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1745 } else { |
|
1746 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1747 } |
|
1748 return size; |
|
1749 } |
|
1750 |
|
1751 // Check for float reg-reg copy. |
|
1752 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { |
|
1753 if (cbuf) { |
|
1754 MacroAssembler _masm(cbuf); |
|
1755 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); |
|
1756 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); |
|
1757 __ fmr(Rdst, Rsrc); |
|
1758 } |
|
1759 #ifndef PRODUCT |
|
1760 else if (!do_size) { |
|
1761 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
|
1762 } |
|
1763 #endif |
|
1764 return 4; |
|
1765 } |
|
1766 |
|
1767 // Check for float store. |
|
1768 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { |
|
1769 int dst_offset = ra_->reg2offset(dst_lo); |
|
1770 if (src_hi != OptoReg::Bad) { |
|
1771 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, |
|
1772 "expected same type of move for high parts"); |
|
1773 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1774 } else { |
|
1775 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); |
|
1776 } |
|
1777 return size; |
|
1778 } |
|
1779 |
|
1780 // Check for float load. |
|
1781 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { |
|
1782 int src_offset = ra_->reg2offset(src_lo); |
|
1783 if (src_hi != OptoReg::Bad) { |
|
1784 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, |
|
1785 "expected same type of move for high parts"); |
|
1786 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1787 } else { |
|
1788 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); |
|
1789 } |
|
1790 return size; |
|
1791 } |
|
1792 |
|
1793 // -------------------------------------------------------------------- |
|
1794 // Check for hi bits still needing moving. Only happens for misaligned |
|
1795 // arguments to native calls. |
|
1796 if (src_hi == dst_hi) |
|
1797 return size; // Self copy; no move. |
|
1798 |
|
1799 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); |
|
1800 ShouldNotReachHere(); // Unimplemented |
|
1801 return 0; |
|
1802 } |
|
1803 |
|
1804 #ifndef PRODUCT |
|
1805 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1806 if (!ra_) |
|
1807 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); |
|
1808 else |
|
1809 implementation(NULL, ra_, false, st); |
|
1810 } |
|
1811 #endif |
|
1812 |
|
1813 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1814 implementation(&cbuf, ra_, false, NULL); |
|
1815 } |
|
1816 |
|
1817 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
|
1818 return implementation(NULL, ra_, true, NULL); |
|
1819 } |
|
1820 |
|
1821 #if 0 // TODO: PPC port |
|
1822 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { |
|
1823 #ifndef PRODUCT |
|
1824 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; |
|
1825 #endif |
|
1826 assert(ra_->node_regs_max_index() != 0, ""); |
|
1827 |
|
1828 // Get registers to move. |
|
1829 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); |
|
1830 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); |
|
1831 OptoReg::Name dst_hi = ra_->get_reg_second(n); |
|
1832 OptoReg::Name dst_lo = ra_->get_reg_first(n); |
|
1833 |
|
1834 enum RC src_lo_rc = rc_class(src_lo); |
|
1835 enum RC dst_lo_rc = rc_class(dst_lo); |
|
1836 |
|
1837 if (src_lo == dst_lo && src_hi == dst_hi) |
|
1838 return ppc64Opcode_none; // Self copy, no move. |
|
1839 |
|
1840 // -------------------------------------- |
|
1841 // Memory->Memory Spill. Use R0 to hold the value. |
|
1842 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { |
|
1843 return ppc64Opcode_compound; |
|
1844 } |
|
1845 |
|
1846 // -------------------------------------- |
|
1847 // Check for float->int copy; requires a trip through memory. |
|
1848 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { |
|
1849 Unimplemented(); |
|
1850 } |
|
1851 |
|
1852 // -------------------------------------- |
|
1853 // Check for integer reg-reg copy. |
|
1854 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { |
|
1855 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); |
|
1856 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); |
|
1857 if (Rsrc == Rdst) { |
|
1858 return ppc64Opcode_none; |
|
1859 } else { |
|
1860 return ppc64Opcode_or; |
|
1861 } |
|
1862 } |
|
1863 |
|
1864 // Check for integer store. |
|
1865 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { |
|
1866 if (src_hi != OptoReg::Bad) { |
|
1867 return ppc64Opcode_std; |
|
1868 } else { |
|
1869 return ppc64Opcode_stw; |
|
1870 } |
|
1871 } |
|
1872 |
|
1873 // Check for integer load. |
|
1874 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { |
|
1875 if (src_hi != OptoReg::Bad) { |
|
1876 return ppc64Opcode_ld; |
|
1877 } else { |
|
1878 return ppc64Opcode_lwz; |
|
1879 } |
|
1880 } |
|
1881 |
|
1882 // Check for float reg-reg copy. |
|
1883 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { |
|
1884 return ppc64Opcode_fmr; |
|
1885 } |
|
1886 |
|
1887 // Check for float store. |
|
1888 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { |
|
1889 if (src_hi != OptoReg::Bad) { |
|
1890 return ppc64Opcode_stfd; |
|
1891 } else { |
|
1892 return ppc64Opcode_stfs; |
|
1893 } |
|
1894 } |
|
1895 |
|
1896 // Check for float load. |
|
1897 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { |
|
1898 if (src_hi != OptoReg::Bad) { |
|
1899 return ppc64Opcode_lfd; |
|
1900 } else { |
|
1901 return ppc64Opcode_lfs; |
|
1902 } |
|
1903 } |
|
1904 |
|
1905 // -------------------------------------------------------------------- |
|
1906 // Check for hi bits still needing moving. Only happens for misaligned |
|
1907 // arguments to native calls. |
|
1908 if (src_hi == dst_hi) |
|
1909 return ppc64Opcode_none; // Self copy; no move. |
|
1910 |
|
1911 ShouldNotReachHere(); |
|
1912 return ppc64Opcode_undefined; |
|
1913 } |
|
1914 #endif // PPC port |
|
1915 |
|
1916 #ifndef PRODUCT |
|
1917 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1918 st->print("NOP \t// %d nops to pad for loops.", _count); |
|
1919 } |
|
1920 #endif |
|
1921 |
|
1922 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { |
|
1923 MacroAssembler _masm(&cbuf); |
|
1924 // _count contains the number of nops needed for padding. |
|
1925 for (int i = 0; i < _count; i++) { |
|
1926 __ nop(); |
|
1927 } |
|
1928 } |
|
1929 |
|
1930 uint MachNopNode::size(PhaseRegAlloc *ra_) const { |
|
1931 return _count * 4; |
|
1932 } |
|
1933 |
|
1934 #ifndef PRODUCT |
|
1935 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1936 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1937 int reg = ra_->get_reg_first(this); |
|
1938 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset); |
|
1939 } |
|
1940 #endif |
|
1941 |
|
1942 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1943 MacroAssembler _masm(&cbuf); |
|
1944 |
|
1945 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); |
|
1946 int reg = ra_->get_encode(this); |
|
1947 |
|
1948 if (Assembler::is_simm(offset, 16)) { |
|
1949 __ addi(as_Register(reg), R1, offset); |
|
1950 } else { |
|
1951 ShouldNotReachHere(); |
|
1952 } |
|
1953 } |
|
1954 |
|
1955 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { |
|
1956 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). |
|
1957 return 4; |
|
1958 } |
|
1959 |
|
1960 #ifndef PRODUCT |
|
1961 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { |
|
1962 st->print_cr("---- MachUEPNode ----"); |
|
1963 st->print_cr("..."); |
|
1964 } |
|
1965 #endif |
|
1966 |
|
1967 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
|
1968 // This is the unverified entry point. |
|
1969 MacroAssembler _masm(&cbuf); |
|
1970 |
|
1971 // Inline_cache contains a klass. |
|
1972 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); |
|
1973 Register receiver_klass = R0; // tmp |
|
1974 |
|
1975 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); |
|
1976 assert(R11_scratch1 == R11, "need prologue scratch register"); |
|
1977 |
|
1978 // Check for NULL argument if we don't have implicit null checks. |
|
1979 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { |
|
1980 if (TrapBasedNullChecks) { |
|
1981 __ trap_null_check(R3_ARG1); |
|
1982 } else { |
|
1983 Label valid; |
|
1984 __ cmpdi(CCR0, R3_ARG1, 0); |
|
1985 __ bne_predict_taken(CCR0, valid); |
|
1986 // We have a null argument, branch to ic_miss_stub. |
|
1987 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), |
|
1988 relocInfo::runtime_call_type); |
|
1989 __ bind(valid); |
|
1990 } |
|
1991 } |
|
1992 // Assume argument is not NULL, load klass from receiver. |
|
1993 __ load_klass(receiver_klass, R3_ARG1); |
|
1994 |
|
1995 if (TrapBasedICMissChecks) { |
|
1996 __ trap_ic_miss_check(receiver_klass, ic_klass); |
|
1997 } else { |
|
1998 Label valid; |
|
1999 __ cmpd(CCR0, receiver_klass, ic_klass); |
|
2000 __ beq_predict_taken(CCR0, valid); |
|
2001 // We have an unexpected klass, branch to ic_miss_stub. |
|
2002 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), |
|
2003 relocInfo::runtime_call_type); |
|
2004 __ bind(valid); |
|
2005 } |
|
2006 |
|
2007 // Argument is valid and klass is as expected, continue. |
|
2008 } |
|
2009 |
|
2010 #if 0 // TODO: PPC port |
|
2011 // Optimize UEP code on z (save a load_const() call in main path). |
|
2012 int MachUEPNode::ep_offset() { |
|
2013 return 0; |
|
2014 } |
|
2015 #endif |
|
2016 |
|
2017 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { |
|
2018 // Variable size. Determine dynamically. |
|
2019 return MachNode::size(ra_); |
|
2020 } |
|
2021 |
|
2022 //============================================================================= |
|
2023 |
|
2024 uint size_exception_handler() { |
|
2025 // The exception_handler is a b64_patchable. |
|
2026 return MacroAssembler::b64_patchable_size; |
|
2027 } |
|
2028 |
|
2029 uint size_deopt_handler() { |
|
2030 // The deopt_handler is a bl64_patchable. |
|
2031 return MacroAssembler::bl64_patchable_size; |
|
2032 } |
|
2033 |
|
2034 int emit_exception_handler(CodeBuffer &cbuf) { |
|
2035 MacroAssembler _masm(&cbuf); |
|
2036 |
|
2037 address base = __ start_a_stub(size_exception_handler()); |
|
2038 if (base == NULL) return 0; // CodeBuffer::expand failed |
|
2039 |
|
2040 int offset = __ offset(); |
|
2041 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), |
|
2042 relocInfo::runtime_call_type); |
|
2043 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); |
|
2044 __ end_a_stub(); |
|
2045 |
|
2046 return offset; |
|
2047 } |
|
2048 |
|
2049 // The deopt_handler is like the exception handler, but it calls to |
|
2050 // the deoptimization blob instead of jumping to the exception blob. |
|
2051 int emit_deopt_handler(CodeBuffer& cbuf) { |
|
2052 MacroAssembler _masm(&cbuf); |
|
2053 |
|
2054 address base = __ start_a_stub(size_deopt_handler()); |
|
2055 if (base == NULL) return 0; // CodeBuffer::expand failed |
|
2056 |
|
2057 int offset = __ offset(); |
|
2058 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), |
|
2059 relocInfo::runtime_call_type); |
|
2060 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); |
|
2061 __ end_a_stub(); |
|
2062 |
|
2063 return offset; |
|
2064 } |
|
2065 |
|
2066 //============================================================================= |
|
2067 |
|
2068 // Use a frame slots bias for frameless methods if accessing the stack. |
|
2069 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { |
|
2070 if (as_Register(reg_enc) == R1_SP) { |
|
2071 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); |
|
2072 } |
|
2073 return 0; |
|
2074 } |
|
2075 |
|
2076 const bool Matcher::match_rule_supported(int opcode) { |
|
2077 if (!has_match_rule(opcode)) |
|
2078 return false; |
|
2079 |
|
2080 switch (opcode) { |
|
2081 case Op_CountLeadingZerosI: |
|
2082 case Op_CountLeadingZerosL: |
|
2083 case Op_CountTrailingZerosI: |
|
2084 case Op_CountTrailingZerosL: |
|
2085 if (!UseCountLeadingZerosInstructionsPPC64) |
|
2086 return false; |
|
2087 break; |
|
2088 |
|
2089 case Op_PopCountI: |
|
2090 case Op_PopCountL: |
|
2091 return (UsePopCountInstruction && VM_Version::has_popcntw()); |
|
2092 |
|
2093 case Op_StrComp: |
|
2094 return SpecialStringCompareTo; |
|
2095 case Op_StrEquals: |
|
2096 return SpecialStringEquals; |
|
2097 case Op_StrIndexOf: |
|
2098 return SpecialStringIndexOf; |
|
2099 } |
|
2100 |
|
2101 return true; // Per default match rules are supported. |
|
2102 } |
|
2103 |
|
2104 int Matcher::regnum_to_fpu_offset(int regnum) { |
|
2105 // No user for this method? |
|
2106 Unimplemented(); |
|
2107 return 999; |
|
2108 } |
|
2109 |
|
2110 const bool Matcher::convL2FSupported(void) { |
|
2111 // fcfids can do the conversion (>= Power7). |
|
2112 // fcfid + frsp showed rounding problem when result should be 0x3f800001. |
|
2113 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. |
|
2114 } |
|
2115 |
|
2116 // Vector width in bytes. |
|
2117 const int Matcher::vector_width_in_bytes(BasicType bt) { |
|
2118 assert(MaxVectorSize == 8, ""); |
|
2119 return 8; |
|
2120 } |
|
2121 |
|
2122 // Vector ideal reg. |
|
2123 const int Matcher::vector_ideal_reg(int size) { |
|
2124 assert(MaxVectorSize == 8 && size == 8, ""); |
|
2125 return Op_RegL; |
|
2126 } |
|
2127 |
|
2128 const int Matcher::vector_shift_count_ideal_reg(int size) { |
|
2129 fatal("vector shift is not supported"); |
|
2130 return Node::NotAMachineReg; |
|
2131 } |
|
2132 |
|
2133 // Limits on vector size (number of elements) loaded into vector. |
|
2134 const int Matcher::max_vector_size(const BasicType bt) { |
|
2135 assert(is_java_primitive(bt), "only primitive type vectors"); |
|
2136 return vector_width_in_bytes(bt)/type2aelembytes(bt); |
|
2137 } |
|
2138 |
|
2139 const int Matcher::min_vector_size(const BasicType bt) { |
|
2140 return max_vector_size(bt); // Same as max. |
|
2141 } |
|
2142 |
|
2143 // PPC doesn't support misaligned vectors store/load. |
|
2144 const bool Matcher::misaligned_vectors_ok() { |
|
2145 return false; |
|
2146 } |
|
2147 |
|
2148 // RETURNS: whether this branch offset is short enough that a short |
|
2149 // branch can be used. |
|
2150 // |
|
2151 // If the platform does not provide any short branch variants, then |
|
2152 // this method should return `false' for offset 0. |
|
2153 // |
|
2154 // `Compile::Fill_buffer' will decide on basis of this information |
|
2155 // whether to do the pass `Compile::Shorten_branches' at all. |
|
2156 // |
|
2157 // And `Compile::Shorten_branches' will decide on basis of this |
|
2158 // information whether to replace particular branch sites by short |
|
2159 // ones. |
|
2160 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
|
2161 // Is the offset within the range of a ppc64 pc relative branch? |
|
2162 bool b; |
|
2163 |
|
2164 const int safety_zone = 3 * BytesPerInstWord; |
|
2165 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), |
|
2166 29 - 16 + 1 + 2); |
|
2167 return b; |
|
2168 } |
|
2169 |
|
2170 const bool Matcher::isSimpleConstant64(jlong value) { |
|
2171 // Probably always true, even if a temp register is required. |
|
2172 return true; |
|
2173 } |
|
2174 /* TODO: PPC port |
|
2175 // Make a new machine dependent decode node (with its operands). |
|
2176 MachTypeNode *Matcher::make_decode_node(Compile *C) { |
|
2177 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, |
|
2178 "This method is only implemented for unscaled cOops mode so far"); |
|
2179 MachTypeNode *decode = new (C) decodeN_unscaledNode(); |
|
2180 decode->set_opnd_array(0, new (C) iRegPdstOper()); |
|
2181 decode->set_opnd_array(1, new (C) iRegNsrcOper()); |
|
2182 return decode; |
|
2183 } |
|
2184 */ |
|
2185 // Threshold size for cleararray. |
|
2186 const int Matcher::init_array_short_size = 8 * BytesPerLong; |
|
2187 |
|
2188 // false => size gets scaled to BytesPerLong, ok. |
|
2189 const bool Matcher::init_array_count_is_in_bytes = false; |
|
2190 |
|
2191 // Use conditional move (CMOVL) on Power7. |
|
2192 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves |
|
2193 |
|
2194 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. |
|
2195 // fsel doesn't accept a condition register as input, so this would be slightly different. |
|
2196 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } |
|
2197 |
|
2198 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). |
|
2199 const bool Matcher::require_postalloc_expand = true; |
|
2200 |
|
2201 // Should the Matcher clone shifts on addressing modes, expecting them to |
|
2202 // be subsumed into complex addressing expressions or compute them into |
|
2203 // registers? True for Intel but false for most RISCs. |
|
2204 const bool Matcher::clone_shift_expressions = false; |
|
2205 |
|
2206 // Do we need to mask the count passed to shift instructions or does |
|
2207 // the cpu only look at the lower 5/6 bits anyway? |
|
2208 // Off, as masks are generated in expand rules where required. |
|
2209 // Constant shift counts are handled in Ideal phase. |
|
2210 const bool Matcher::need_masked_shift_count = false; |
|
2211 |
|
2212 // This affects two different things: |
|
2213 // - how Decode nodes are matched |
|
2214 // - how ImplicitNullCheck opportunities are recognized |
|
2215 // If true, the matcher will try to remove all Decodes and match them |
|
2216 // (as operands) into nodes. NullChecks are not prepared to deal with |
|
2217 // Decodes by final_graph_reshaping(). |
|
2218 // If false, final_graph_reshaping() forces the decode behind the Cmp |
|
2219 // for a NullCheck. The matcher matches the Decode node into a register. |
|
2220 // Implicit_null_check optimization moves the Decode along with the |
|
2221 // memory operation back up before the NullCheck. |
|
2222 bool Matcher::narrow_oop_use_complex_address() { |
|
2223 // TODO: PPC port if (MatchDecodeNodes) return true; |
|
2224 return false; |
|
2225 } |
|
2226 |
|
2227 bool Matcher::narrow_klass_use_complex_address() { |
|
2228 NOT_LP64(ShouldNotCallThis()); |
|
2229 assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
2230 // TODO: PPC port if (MatchDecodeNodes) return true; |
|
2231 return false; |
|
2232 } |
|
2233 |
|
2234 // Is it better to copy float constants, or load them directly from memory? |
|
2235 // Intel can load a float constant from a direct address, requiring no |
|
2236 // extra registers. Most RISCs will have to materialize an address into a |
|
2237 // register first, so they would do better to copy the constant from stack. |
|
2238 const bool Matcher::rematerialize_float_constants = false; |
|
2239 |
|
2240 // If CPU can load and store mis-aligned doubles directly then no fixup is |
|
2241 // needed. Else we split the double into 2 integer pieces and move it |
|
2242 // piece-by-piece. Only happens when passing doubles into C code as the |
|
2243 // Java calling convention forces doubles to be aligned. |
|
2244 const bool Matcher::misaligned_doubles_ok = true; |
|
2245 |
|
2246 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { |
|
2247 Unimplemented(); |
|
2248 } |
|
2249 |
|
2250 // Advertise here if the CPU requires explicit rounding operations |
|
2251 // to implement the UseStrictFP mode. |
|
2252 const bool Matcher::strict_fp_requires_explicit_rounding = false; |
|
2253 |
|
2254 // Do floats take an entire double register or just half? |
|
2255 // |
|
2256 // A float occupies a ppc64 double register. For the allocator, a |
|
2257 // ppc64 double register appears as a pair of float registers. |
|
2258 bool Matcher::float_in_double() { return true; } |
|
2259 |
|
2260 // Do ints take an entire long register or just half? |
|
2261 // The relevant question is how the int is callee-saved: |
|
2262 // the whole long is written but de-opt'ing will have to extract |
|
2263 // the relevant 32 bits. |
|
2264 const bool Matcher::int_in_long = true; |
|
2265 |
|
2266 // Constants for c2c and c calling conventions. |
|
2267 |
|
2268 const MachRegisterNumbers iarg_reg[8] = { |
|
2269 R3_num, R4_num, R5_num, R6_num, |
|
2270 R7_num, R8_num, R9_num, R10_num |
|
2271 }; |
|
2272 |
|
2273 const MachRegisterNumbers farg_reg[13] = { |
|
2274 F1_num, F2_num, F3_num, F4_num, |
|
2275 F5_num, F6_num, F7_num, F8_num, |
|
2276 F9_num, F10_num, F11_num, F12_num, |
|
2277 F13_num |
|
2278 }; |
|
2279 |
|
2280 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); |
|
2281 |
|
2282 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); |
|
2283 |
|
2284 // Return whether or not this register is ever used as an argument. This |
|
2285 // function is used on startup to build the trampoline stubs in generateOptoStub. |
|
2286 // Registers not mentioned will be killed by the VM call in the trampoline, and |
|
2287 // arguments in those registers not be available to the callee. |
|
2288 bool Matcher::can_be_java_arg(int reg) { |
|
2289 // We return true for all registers contained in iarg_reg[] and |
|
2290 // farg_reg[] and their virtual halves. |
|
2291 // We must include the virtual halves in order to get STDs and LDs |
|
2292 // instead of STWs and LWs in the trampoline stubs. |
|
2293 |
|
2294 if ( reg == R3_num || reg == R3_H_num |
|
2295 || reg == R4_num || reg == R4_H_num |
|
2296 || reg == R5_num || reg == R5_H_num |
|
2297 || reg == R6_num || reg == R6_H_num |
|
2298 || reg == R7_num || reg == R7_H_num |
|
2299 || reg == R8_num || reg == R8_H_num |
|
2300 || reg == R9_num || reg == R9_H_num |
|
2301 || reg == R10_num || reg == R10_H_num) |
|
2302 return true; |
|
2303 |
|
2304 if ( reg == F1_num || reg == F1_H_num |
|
2305 || reg == F2_num || reg == F2_H_num |
|
2306 || reg == F3_num || reg == F3_H_num |
|
2307 || reg == F4_num || reg == F4_H_num |
|
2308 || reg == F5_num || reg == F5_H_num |
|
2309 || reg == F6_num || reg == F6_H_num |
|
2310 || reg == F7_num || reg == F7_H_num |
|
2311 || reg == F8_num || reg == F8_H_num |
|
2312 || reg == F9_num || reg == F9_H_num |
|
2313 || reg == F10_num || reg == F10_H_num |
|
2314 || reg == F11_num || reg == F11_H_num |
|
2315 || reg == F12_num || reg == F12_H_num |
|
2316 || reg == F13_num || reg == F13_H_num) |
|
2317 return true; |
|
2318 |
|
2319 return false; |
|
2320 } |
|
2321 |
|
2322 bool Matcher::is_spillable_arg(int reg) { |
|
2323 return can_be_java_arg(reg); |
|
2324 } |
|
2325 |
|
2326 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { |
|
2327 return false; |
|
2328 } |
|
2329 |
|
2330 // Register for DIVI projection of divmodI. |
|
2331 RegMask Matcher::divI_proj_mask() { |
|
2332 ShouldNotReachHere(); |
|
2333 return RegMask(); |
|
2334 } |
|
2335 |
|
2336 // Register for MODI projection of divmodI. |
|
2337 RegMask Matcher::modI_proj_mask() { |
|
2338 ShouldNotReachHere(); |
|
2339 return RegMask(); |
|
2340 } |
|
2341 |
|
2342 // Register for DIVL projection of divmodL. |
|
2343 RegMask Matcher::divL_proj_mask() { |
|
2344 ShouldNotReachHere(); |
|
2345 return RegMask(); |
|
2346 } |
|
2347 |
|
2348 // Register for MODL projection of divmodL. |
|
2349 RegMask Matcher::modL_proj_mask() { |
|
2350 ShouldNotReachHere(); |
|
2351 return RegMask(); |
|
2352 } |
|
2353 |
|
2354 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
2355 return RegMask(); |
|
2356 } |
|
2357 |
|
2358 const RegMask Matcher::mathExactI_result_proj_mask() { |
|
2359 return RARG4_BITS64_REG_mask(); |
|
2360 } |
|
2361 |
|
2362 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
2363 return RARG4_BITS64_REG_mask(); |
|
2364 } |
|
2365 |
|
2366 const RegMask Matcher::mathExactI_flags_proj_mask() { |
|
2367 return INT_FLAGS_mask(); |
|
2368 } |
|
2369 |
|
2370 %} |
|
2371 |
|
2372 //----------ENCODING BLOCK----------------------------------------------------- |
|
2373 // This block specifies the encoding classes used by the compiler to output |
|
2374 // byte streams. Encoding classes are parameterized macros used by |
|
2375 // Machine Instruction Nodes in order to generate the bit encoding of the |
|
2376 // instruction. Operands specify their base encoding interface with the |
|
2377 // interface keyword. There are currently supported four interfaces, |
|
2378 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an |
|
2379 // operand to generate a function which returns its register number when |
|
2380 // queried. CONST_INTER causes an operand to generate a function which |
|
2381 // returns the value of the constant when queried. MEMORY_INTER causes an |
|
2382 // operand to generate four functions which return the Base Register, the |
|
2383 // Index Register, the Scale Value, and the Offset Value of the operand when |
|
2384 // queried. COND_INTER causes an operand to generate six functions which |
|
2385 // return the encoding code (ie - encoding bits for the instruction) |
|
2386 // associated with each basic boolean condition for a conditional instruction. |
|
2387 // |
|
2388 // Instructions specify two basic values for encoding. Again, a function |
|
2389 // is available to check if the constant displacement is an oop. They use the |
|
2390 // ins_encode keyword to specify their encoding classes (which must be |
|
2391 // a sequence of enc_class names, and their parameters, specified in |
|
2392 // the encoding block), and they use the |
|
2393 // opcode keyword to specify, in order, their primary, secondary, and |
|
2394 // tertiary opcode. Only the opcode sections which a particular instruction |
|
2395 // needs for encoding need to be specified. |
|
2396 encode %{ |
|
2397 enc_class enc_unimplemented %{ |
|
2398 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2399 MacroAssembler _masm(&cbuf); |
|
2400 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); |
|
2401 %} |
|
2402 |
|
2403 enc_class enc_untested %{ |
|
2404 #ifdef ASSERT |
|
2405 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2406 MacroAssembler _masm(&cbuf); |
|
2407 __ untested("Untested mach node encoding in AD file."); |
|
2408 #else |
|
2409 // TODO: PPC port $archOpcode(ppc64Opcode_none); |
|
2410 #endif |
|
2411 %} |
|
2412 |
|
2413 enc_class enc_lbz(iRegIdst dst, memory mem) %{ |
|
2414 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); |
|
2415 MacroAssembler _masm(&cbuf); |
|
2416 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2417 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2418 %} |
|
2419 |
|
2420 // Load acquire. |
|
2421 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ |
|
2422 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2423 MacroAssembler _masm(&cbuf); |
|
2424 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2425 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2426 __ twi_0($dst$$Register); |
|
2427 __ isync(); |
|
2428 %} |
|
2429 |
|
2430 enc_class enc_lhz(iRegIdst dst, memory mem) %{ |
|
2431 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); |
|
2432 |
|
2433 MacroAssembler _masm(&cbuf); |
|
2434 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2435 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2436 %} |
|
2437 |
|
2438 // Load acquire. |
|
2439 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ |
|
2440 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2441 |
|
2442 MacroAssembler _masm(&cbuf); |
|
2443 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2444 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2445 __ twi_0($dst$$Register); |
|
2446 __ isync(); |
|
2447 %} |
|
2448 |
|
2449 enc_class enc_lwz(iRegIdst dst, memory mem) %{ |
|
2450 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); |
|
2451 |
|
2452 MacroAssembler _masm(&cbuf); |
|
2453 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2454 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2455 %} |
|
2456 |
|
2457 // Load acquire. |
|
2458 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ |
|
2459 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2460 |
|
2461 MacroAssembler _masm(&cbuf); |
|
2462 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2463 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); |
|
2464 __ twi_0($dst$$Register); |
|
2465 __ isync(); |
|
2466 %} |
|
2467 |
|
2468 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ |
|
2469 // TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
2470 MacroAssembler _masm(&cbuf); |
|
2471 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2472 // Operand 'ds' requires 4-alignment. |
|
2473 assert((Idisp & 0x3) == 0, "unaligned offset"); |
|
2474 __ ld($dst$$Register, Idisp, $mem$$base$$Register); |
|
2475 %} |
|
2476 |
|
2477 // Load acquire. |
|
2478 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ |
|
2479 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2480 MacroAssembler _masm(&cbuf); |
|
2481 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2482 // Operand 'ds' requires 4-alignment. |
|
2483 assert((Idisp & 0x3) == 0, "unaligned offset"); |
|
2484 __ ld($dst$$Register, Idisp, $mem$$base$$Register); |
|
2485 __ twi_0($dst$$Register); |
|
2486 __ isync(); |
|
2487 %} |
|
2488 |
|
2489 enc_class enc_lfd(RegF dst, memory mem) %{ |
|
2490 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); |
|
2491 MacroAssembler _masm(&cbuf); |
|
2492 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2493 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
2494 %} |
|
2495 |
|
2496 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ |
|
2497 // TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
2498 |
|
2499 MacroAssembler _masm(&cbuf); |
|
2500 int toc_offset = 0; |
|
2501 |
|
2502 if (!ra_->C->in_scratch_emit_size()) { |
|
2503 address const_toc_addr; |
|
2504 // Create a non-oop constant, no relocation needed. |
|
2505 // If it is an IC, it has a virtual_call_Relocation. |
|
2506 const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2507 |
|
2508 // Get the constant's TOC offset. |
|
2509 toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2510 |
|
2511 // Keep the current instruction offset in mind. |
|
2512 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); |
|
2513 } |
|
2514 |
|
2515 __ ld($dst$$Register, toc_offset, $toc$$Register); |
|
2516 %} |
|
2517 |
|
2518 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ |
|
2519 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
2520 |
|
2521 MacroAssembler _masm(&cbuf); |
|
2522 |
|
2523 if (!ra_->C->in_scratch_emit_size()) { |
|
2524 address const_toc_addr; |
|
2525 // Create a non-oop constant, no relocation needed. |
|
2526 // If it is an IC, it has a virtual_call_Relocation. |
|
2527 const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2528 |
|
2529 // Get the constant's TOC offset. |
|
2530 const int toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2531 // Store the toc offset of the constant. |
|
2532 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; |
|
2533 |
|
2534 // Also keep the current instruction offset in mind. |
|
2535 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); |
|
2536 } |
|
2537 |
|
2538 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); |
|
2539 %} |
|
2540 |
|
2541 %} // encode |
|
2542 |
|
2543 source %{ |
|
2544 |
|
2545 typedef struct { |
|
2546 loadConL_hiNode *_large_hi; |
|
2547 loadConL_loNode *_large_lo; |
|
2548 loadConLNode *_small; |
|
2549 MachNode *_last; |
|
2550 } loadConLNodesTuple; |
|
2551 |
|
2552 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, |
|
2553 OptoReg::Name reg_second, OptoReg::Name reg_first) { |
|
2554 loadConLNodesTuple nodes; |
|
2555 |
|
2556 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2557 if (large_constant_pool) { |
|
2558 // Create new nodes. |
|
2559 loadConL_hiNode *m1 = new (C) loadConL_hiNode(); |
|
2560 loadConL_loNode *m2 = new (C) loadConL_loNode(); |
|
2561 |
|
2562 // inputs for new nodes |
|
2563 m1->add_req(NULL, toc); |
|
2564 m2->add_req(NULL, m1); |
|
2565 |
|
2566 // operands for new nodes |
|
2567 m1->_opnds[0] = new (C) iRegLdstOper(); // dst |
|
2568 m1->_opnds[1] = immSrc; // src |
|
2569 m1->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2570 m2->_opnds[0] = new (C) iRegLdstOper(); // dst |
|
2571 m2->_opnds[1] = immSrc; // src |
|
2572 m2->_opnds[2] = new (C) iRegLdstOper(); // base |
|
2573 |
|
2574 // Initialize ins_attrib TOC fields. |
|
2575 m1->_const_toc_offset = -1; |
|
2576 m2->_const_toc_offset_hi_node = m1; |
|
2577 |
|
2578 // Initialize ins_attrib instruction offset. |
|
2579 m1->_cbuf_insts_offset = -1; |
|
2580 |
|
2581 // register allocation for new nodes |
|
2582 ra_->set_pair(m1->_idx, reg_second, reg_first); |
|
2583 ra_->set_pair(m2->_idx, reg_second, reg_first); |
|
2584 |
|
2585 // Create result. |
|
2586 nodes._large_hi = m1; |
|
2587 nodes._large_lo = m2; |
|
2588 nodes._small = NULL; |
|
2589 nodes._last = nodes._large_lo; |
|
2590 assert(m2->bottom_type()->isa_long(), "must be long"); |
|
2591 } else { |
|
2592 loadConLNode *m2 = new (C) loadConLNode(); |
|
2593 |
|
2594 // inputs for new nodes |
|
2595 m2->add_req(NULL, toc); |
|
2596 |
|
2597 // operands for new nodes |
|
2598 m2->_opnds[0] = new (C) iRegLdstOper(); // dst |
|
2599 m2->_opnds[1] = immSrc; // src |
|
2600 m2->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2601 |
|
2602 // Initialize ins_attrib instruction offset. |
|
2603 m2->_cbuf_insts_offset = -1; |
|
2604 |
|
2605 // register allocation for new nodes |
|
2606 ra_->set_pair(m2->_idx, reg_second, reg_first); |
|
2607 |
|
2608 // Create result. |
|
2609 nodes._large_hi = NULL; |
|
2610 nodes._large_lo = NULL; |
|
2611 nodes._small = m2; |
|
2612 nodes._last = nodes._small; |
|
2613 assert(m2->bottom_type()->isa_long(), "must be long"); |
|
2614 } |
|
2615 |
|
2616 return nodes; |
|
2617 } |
|
2618 |
|
2619 %} // source |
|
2620 |
|
2621 encode %{ |
|
2622 // Postalloc expand emitter for loading a long constant from the method's TOC. |
|
2623 // Enc_class needed as consttanttablebase is not supported by postalloc |
|
2624 // expand. |
|
2625 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ |
|
2626 // Create new nodes. |
|
2627 loadConLNodesTuple loadConLNodes = |
|
2628 loadConLNodesTuple_create(C, ra_, n_toc, op_src, |
|
2629 ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2630 |
|
2631 // Push new nodes. |
|
2632 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); |
|
2633 if (loadConLNodes._last) nodes->push(loadConLNodes._last); |
|
2634 |
|
2635 // some asserts |
|
2636 assert(nodes->length() >= 1, "must have created at least 1 node"); |
|
2637 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); |
|
2638 %} |
|
2639 |
|
2640 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ |
|
2641 // TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
2642 |
|
2643 MacroAssembler _masm(&cbuf); |
|
2644 int toc_offset = 0; |
|
2645 |
|
2646 if (!ra_->C->in_scratch_emit_size()) { |
|
2647 intptr_t val = $src$$constant; |
|
2648 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src |
|
2649 address const_toc_addr; |
|
2650 if (constant_reloc == relocInfo::oop_type) { |
|
2651 // Create an oop constant and a corresponding relocation. |
|
2652 AddressLiteral a = __ allocate_oop_address((jobject)val); |
|
2653 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2654 __ relocate(a.rspec()); |
|
2655 } else if (constant_reloc == relocInfo::metadata_type) { |
|
2656 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); |
|
2657 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2658 __ relocate(a.rspec()); |
|
2659 } else { |
|
2660 // Create a non-oop constant, no relocation needed. |
|
2661 const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2662 } |
|
2663 |
|
2664 // Get the constant's TOC offset. |
|
2665 toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2666 } |
|
2667 |
|
2668 __ ld($dst$$Register, toc_offset, $toc$$Register); |
|
2669 %} |
|
2670 |
|
2671 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ |
|
2672 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
2673 |
|
2674 MacroAssembler _masm(&cbuf); |
|
2675 if (!ra_->C->in_scratch_emit_size()) { |
|
2676 intptr_t val = $src$$constant; |
|
2677 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src |
|
2678 address const_toc_addr; |
|
2679 if (constant_reloc == relocInfo::oop_type) { |
|
2680 // Create an oop constant and a corresponding relocation. |
|
2681 AddressLiteral a = __ allocate_oop_address((jobject)val); |
|
2682 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2683 __ relocate(a.rspec()); |
|
2684 } else if (constant_reloc == relocInfo::metadata_type) { |
|
2685 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); |
|
2686 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); |
|
2687 __ relocate(a.rspec()); |
|
2688 } else { // non-oop pointers, e.g. card mark base, heap top |
|
2689 // Create a non-oop constant, no relocation needed. |
|
2690 const_toc_addr = __ long_constant((jlong)$src$$constant); |
|
2691 } |
|
2692 |
|
2693 // Get the constant's TOC offset. |
|
2694 const int toc_offset = __ offset_to_method_toc(const_toc_addr); |
|
2695 // Store the toc offset of the constant. |
|
2696 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; |
|
2697 } |
|
2698 |
|
2699 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); |
|
2700 %} |
|
2701 |
|
2702 // Postalloc expand emitter for loading a ptr constant from the method's TOC. |
|
2703 // Enc_class needed as consttanttablebase is not supported by postalloc |
|
2704 // expand. |
|
2705 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ |
|
2706 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2707 if (large_constant_pool) { |
|
2708 // Create new nodes. |
|
2709 loadConP_hiNode *m1 = new (C) loadConP_hiNode(); |
|
2710 loadConP_loNode *m2 = new (C) loadConP_loNode(); |
|
2711 |
|
2712 // inputs for new nodes |
|
2713 m1->add_req(NULL, n_toc); |
|
2714 m2->add_req(NULL, m1); |
|
2715 |
|
2716 // operands for new nodes |
|
2717 m1->_opnds[0] = new (C) iRegPdstOper(); // dst |
|
2718 m1->_opnds[1] = op_src; // src |
|
2719 m1->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2720 m2->_opnds[0] = new (C) iRegPdstOper(); // dst |
|
2721 m2->_opnds[1] = op_src; // src |
|
2722 m2->_opnds[2] = new (C) iRegLdstOper(); // base |
|
2723 |
|
2724 // Initialize ins_attrib TOC fields. |
|
2725 m1->_const_toc_offset = -1; |
|
2726 m2->_const_toc_offset_hi_node = m1; |
|
2727 |
|
2728 // Register allocation for new nodes. |
|
2729 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2730 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2731 |
|
2732 nodes->push(m1); |
|
2733 nodes->push(m2); |
|
2734 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); |
|
2735 } else { |
|
2736 loadConPNode *m2 = new (C) loadConPNode(); |
|
2737 |
|
2738 // inputs for new nodes |
|
2739 m2->add_req(NULL, n_toc); |
|
2740 |
|
2741 // operands for new nodes |
|
2742 m2->_opnds[0] = new (C) iRegPdstOper(); // dst |
|
2743 m2->_opnds[1] = op_src; // src |
|
2744 m2->_opnds[2] = new (C) iRegPdstOper(); // toc |
|
2745 |
|
2746 // Register allocation for new nodes. |
|
2747 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2748 |
|
2749 nodes->push(m2); |
|
2750 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); |
|
2751 } |
|
2752 %} |
|
2753 |
|
2754 // Enc_class needed as consttanttablebase is not supported by postalloc |
|
2755 // expand. |
|
2756 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ |
|
2757 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2758 |
|
2759 MachNode *m2; |
|
2760 if (large_constant_pool) { |
|
2761 m2 = new (C) loadConFCompNode(); |
|
2762 } else { |
|
2763 m2 = new (C) loadConFNode(); |
|
2764 } |
|
2765 // inputs for new nodes |
|
2766 m2->add_req(NULL, n_toc); |
|
2767 |
|
2768 // operands for new nodes |
|
2769 m2->_opnds[0] = op_dst; |
|
2770 m2->_opnds[1] = op_src; |
|
2771 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase |
|
2772 |
|
2773 // register allocation for new nodes |
|
2774 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2775 nodes->push(m2); |
|
2776 %} |
|
2777 |
|
2778 // Enc_class needed as consttanttablebase is not supported by postalloc |
|
2779 // expand. |
|
2780 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ |
|
2781 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; |
|
2782 |
|
2783 MachNode *m2; |
|
2784 if (large_constant_pool) { |
|
2785 m2 = new (C) loadConDCompNode(); |
|
2786 } else { |
|
2787 m2 = new (C) loadConDNode(); |
|
2788 } |
|
2789 // inputs for new nodes |
|
2790 m2->add_req(NULL, n_toc); |
|
2791 |
|
2792 // operands for new nodes |
|
2793 m2->_opnds[0] = op_dst; |
|
2794 m2->_opnds[1] = op_src; |
|
2795 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase |
|
2796 |
|
2797 // register allocation for new nodes |
|
2798 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2799 nodes->push(m2); |
|
2800 %} |
|
2801 |
|
2802 enc_class enc_stw(iRegIsrc src, memory mem) %{ |
|
2803 // TODO: PPC port $archOpcode(ppc64Opcode_stw); |
|
2804 MacroAssembler _masm(&cbuf); |
|
2805 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2806 __ stw($src$$Register, Idisp, $mem$$base$$Register); |
|
2807 %} |
|
2808 |
|
2809 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ |
|
2810 // TODO: PPC port $archOpcode(ppc64Opcode_std); |
|
2811 MacroAssembler _masm(&cbuf); |
|
2812 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2813 // Operand 'ds' requires 4-alignment. |
|
2814 assert((Idisp & 0x3) == 0, "unaligned offset"); |
|
2815 __ std($src$$Register, Idisp, $mem$$base$$Register); |
|
2816 %} |
|
2817 |
|
2818 enc_class enc_stfs(RegF src, memory mem) %{ |
|
2819 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); |
|
2820 MacroAssembler _masm(&cbuf); |
|
2821 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2822 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); |
|
2823 %} |
|
2824 |
|
2825 enc_class enc_stfd(RegF src, memory mem) %{ |
|
2826 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); |
|
2827 MacroAssembler _masm(&cbuf); |
|
2828 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
2829 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); |
|
2830 %} |
|
2831 |
|
2832 // Use release_store for card-marking to ensure that previous |
|
2833 // oop-stores are visible before the card-mark change. |
|
2834 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{ |
|
2835 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
2836 // FIXME: Implement this as a cmove and use a fixed condition code |
|
2837 // register which is written on every transition to compiled code, |
|
2838 // e.g. in call-stub and when returning from runtime stubs. |
|
2839 // |
|
2840 // Proposed code sequence for the cmove implementation: |
|
2841 // |
|
2842 // Label skip_release; |
|
2843 // __ beq(CCRfixed, skip_release); |
|
2844 // __ release(); |
|
2845 // __ bind(skip_release); |
|
2846 // __ stb(card mark); |
|
2847 |
|
2848 MacroAssembler _masm(&cbuf); |
|
2849 Label skip_storestore; |
|
2850 |
|
2851 #if 0 // TODO: PPC port |
|
2852 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the |
|
2853 // StoreStore barrier conditionally. |
|
2854 __ lwz(R0, 0, $releaseFieldAddr$$Register); |
|
2855 __ cmpwi(CCR0, R0, 0); |
|
2856 __ beq_predict_taken(CCR0, skip_release); |
|
2857 #endif |
|
2858 __ li(R0, 0); |
|
2859 __ membar(Assembler::StoreStore); |
|
2860 #if 0 // TODO: PPC port |
|
2861 __ bind(skip_storestore); |
|
2862 #endif |
|
2863 |
|
2864 // Do the store. |
|
2865 if ($mem$$index == 0) { |
|
2866 __ stb(R0, $mem$$disp, $mem$$base$$Register); |
|
2867 } else { |
|
2868 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); |
|
2869 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); |
|
2870 } |
|
2871 %} |
|
2872 |
|
2873 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ |
|
2874 |
|
2875 if (VM_Version::has_isel()) { |
|
2876 // use isel instruction with Power 7 |
|
2877 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); |
|
2878 encodeP_subNode *n_sub_base = new (C) encodeP_subNode(); |
|
2879 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); |
|
2880 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode(); |
|
2881 |
|
2882 n_compare->add_req(n_region, n_src); |
|
2883 n_compare->_opnds[0] = op_crx; |
|
2884 n_compare->_opnds[1] = op_src; |
|
2885 n_compare->_opnds[2] = new (C) immL16Oper(0); |
|
2886 |
|
2887 n_sub_base->add_req(n_region, n_src); |
|
2888 n_sub_base->_opnds[0] = op_dst; |
|
2889 n_sub_base->_opnds[1] = op_src; |
|
2890 n_sub_base->_bottom_type = _bottom_type; |
|
2891 |
|
2892 n_shift->add_req(n_region, n_sub_base); |
|
2893 n_shift->_opnds[0] = op_dst; |
|
2894 n_shift->_opnds[1] = op_dst; |
|
2895 n_shift->_bottom_type = _bottom_type; |
|
2896 |
|
2897 n_cond_set->add_req(n_region, n_compare, n_shift); |
|
2898 n_cond_set->_opnds[0] = op_dst; |
|
2899 n_cond_set->_opnds[1] = op_crx; |
|
2900 n_cond_set->_opnds[2] = op_dst; |
|
2901 n_cond_set->_bottom_type = _bottom_type; |
|
2902 |
|
2903 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
2904 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2905 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2906 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2907 |
|
2908 nodes->push(n_compare); |
|
2909 nodes->push(n_sub_base); |
|
2910 nodes->push(n_shift); |
|
2911 nodes->push(n_cond_set); |
|
2912 |
|
2913 } else { |
|
2914 // before Power 7 |
|
2915 moveRegNode *n_move = new (C) moveRegNode(); |
|
2916 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); |
|
2917 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); |
|
2918 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode(); |
|
2919 |
|
2920 n_move->add_req(n_region, n_src); |
|
2921 n_move->_opnds[0] = op_dst; |
|
2922 n_move->_opnds[1] = op_src; |
|
2923 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. |
|
2924 |
|
2925 n_compare->add_req(n_region, n_src); |
|
2926 n_compare->add_prec(n_move); |
|
2927 |
|
2928 n_compare->_opnds[0] = op_crx; |
|
2929 n_compare->_opnds[1] = op_src; |
|
2930 n_compare->_opnds[2] = new (C) immL16Oper(0); |
|
2931 |
|
2932 n_sub_base->add_req(n_region, n_compare, n_src); |
|
2933 n_sub_base->_opnds[0] = op_dst; |
|
2934 n_sub_base->_opnds[1] = op_crx; |
|
2935 n_sub_base->_opnds[2] = op_src; |
|
2936 n_sub_base->_bottom_type = _bottom_type; |
|
2937 |
|
2938 n_shift->add_req(n_region, n_sub_base); |
|
2939 n_shift->_opnds[0] = op_dst; |
|
2940 n_shift->_opnds[1] = op_dst; |
|
2941 n_shift->_bottom_type = _bottom_type; |
|
2942 |
|
2943 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2944 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
2945 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2946 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2947 |
|
2948 nodes->push(n_move); |
|
2949 nodes->push(n_compare); |
|
2950 nodes->push(n_sub_base); |
|
2951 nodes->push(n_shift); |
|
2952 } |
|
2953 |
|
2954 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. |
|
2955 %} |
|
2956 |
|
2957 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ |
|
2958 |
|
2959 encodeP_subNode *n1 = new (C) encodeP_subNode(); |
|
2960 n1->add_req(n_region, n_src); |
|
2961 n1->_opnds[0] = op_dst; |
|
2962 n1->_opnds[1] = op_src; |
|
2963 n1->_bottom_type = _bottom_type; |
|
2964 |
|
2965 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode(); |
|
2966 n2->add_req(n_region, n1); |
|
2967 n2->_opnds[0] = op_dst; |
|
2968 n2->_opnds[1] = op_dst; |
|
2969 n2->_bottom_type = _bottom_type; |
|
2970 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2971 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
2972 |
|
2973 nodes->push(n1); |
|
2974 nodes->push(n2); |
|
2975 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. |
|
2976 %} |
|
2977 |
|
2978 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ |
|
2979 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode(); |
|
2980 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node(); |
|
2981 |
|
2982 n_compare->add_req(n_region, n_src); |
|
2983 n_compare->_opnds[0] = op_crx; |
|
2984 n_compare->_opnds[1] = op_src; |
|
2985 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR); |
|
2986 |
|
2987 n_shift->add_req(n_region, n_src); |
|
2988 n_shift->_opnds[0] = op_dst; |
|
2989 n_shift->_opnds[1] = op_src; |
|
2990 n_shift->_bottom_type = _bottom_type; |
|
2991 |
|
2992 if (VM_Version::has_isel()) { |
|
2993 // use isel instruction with Power 7 |
|
2994 |
|
2995 decodeN_addNode *n_add_base = new (C) decodeN_addNode(); |
|
2996 n_add_base->add_req(n_region, n_shift); |
|
2997 n_add_base->_opnds[0] = op_dst; |
|
2998 n_add_base->_opnds[1] = op_dst; |
|
2999 n_add_base->_bottom_type = _bottom_type; |
|
3000 |
|
3001 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode(); |
|
3002 n_cond_set->add_req(n_region, n_compare, n_add_base); |
|
3003 n_cond_set->_opnds[0] = op_dst; |
|
3004 n_cond_set->_opnds[1] = op_crx; |
|
3005 n_cond_set->_opnds[2] = op_dst; |
|
3006 n_cond_set->_bottom_type = _bottom_type; |
|
3007 |
|
3008 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); |
|
3009 ra_->set_oop(n_cond_set, true); |
|
3010 |
|
3011 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3012 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
3013 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3014 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3015 |
|
3016 nodes->push(n_compare); |
|
3017 nodes->push(n_shift); |
|
3018 nodes->push(n_add_base); |
|
3019 nodes->push(n_cond_set); |
|
3020 |
|
3021 } else { |
|
3022 // before Power 7 |
|
3023 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode(); |
|
3024 |
|
3025 n_add_base->add_req(n_region, n_compare, n_shift); |
|
3026 n_add_base->_opnds[0] = op_dst; |
|
3027 n_add_base->_opnds[1] = op_crx; |
|
3028 n_add_base->_opnds[2] = op_dst; |
|
3029 n_add_base->_bottom_type = _bottom_type; |
|
3030 |
|
3031 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); |
|
3032 ra_->set_oop(n_add_base, true); |
|
3033 |
|
3034 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3035 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); |
|
3036 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3037 |
|
3038 nodes->push(n_compare); |
|
3039 nodes->push(n_shift); |
|
3040 nodes->push(n_add_base); |
|
3041 } |
|
3042 %} |
|
3043 |
|
3044 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ |
|
3045 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode(); |
|
3046 n1->add_req(n_region, n_src); |
|
3047 n1->_opnds[0] = op_dst; |
|
3048 n1->_opnds[1] = op_src; |
|
3049 n1->_bottom_type = _bottom_type; |
|
3050 |
|
3051 decodeN_addNode *n2 = new (C) decodeN_addNode(); |
|
3052 n2->add_req(n_region, n1); |
|
3053 n2->_opnds[0] = op_dst; |
|
3054 n2->_opnds[1] = op_dst; |
|
3055 n2->_bottom_type = _bottom_type; |
|
3056 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3057 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3058 |
|
3059 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); |
|
3060 ra_->set_oop(n2, true); |
|
3061 |
|
3062 nodes->push(n1); |
|
3063 nodes->push(n2); |
|
3064 %} |
|
3065 |
|
3066 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{ |
|
3067 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
3068 |
|
3069 MacroAssembler _masm(&cbuf); |
|
3070 int cc = $cmp$$cmpcode; |
|
3071 int flags_reg = $crx$$reg; |
|
3072 Label done; |
|
3073 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
3074 // Branch if not (cmp crx). |
|
3075 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); |
|
3076 __ mr($dst$$Register, $src$$Register); |
|
3077 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
3078 __ bind(done); |
|
3079 %} |
|
3080 |
|
3081 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{ |
|
3082 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
3083 |
|
3084 MacroAssembler _masm(&cbuf); |
|
3085 Label done; |
|
3086 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
3087 // Branch if not (cmp crx). |
|
3088 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); |
|
3089 __ li($dst$$Register, $src$$constant); |
|
3090 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
3091 __ bind(done); |
|
3092 %} |
|
3093 |
|
3094 // New atomics. |
|
3095 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ |
|
3096 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3097 |
|
3098 MacroAssembler _masm(&cbuf); |
|
3099 Register Rtmp = R0; |
|
3100 Register Rres = $res$$Register; |
|
3101 Register Rsrc = $src$$Register; |
|
3102 Register Rptr = $mem_ptr$$Register; |
|
3103 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3104 Register Rold = RegCollision ? Rtmp : Rres; |
|
3105 |
|
3106 Label Lretry; |
|
3107 __ bind(Lretry); |
|
3108 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3109 __ add(Rtmp, Rsrc, Rold); |
|
3110 __ stwcx_(Rtmp, Rptr); |
|
3111 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { |
|
3112 __ bne_predict_not_taken(CCR0, Lretry); |
|
3113 } else { |
|
3114 __ bne( CCR0, Lretry); |
|
3115 } |
|
3116 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); |
|
3117 __ fence(); |
|
3118 %} |
|
3119 |
|
3120 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ |
|
3121 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3122 |
|
3123 MacroAssembler _masm(&cbuf); |
|
3124 Register Rtmp = R0; |
|
3125 Register Rres = $res$$Register; |
|
3126 Register Rsrc = $src$$Register; |
|
3127 Register Rptr = $mem_ptr$$Register; |
|
3128 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3129 Register Rold = RegCollision ? Rtmp : Rres; |
|
3130 |
|
3131 Label Lretry; |
|
3132 __ bind(Lretry); |
|
3133 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3134 __ add(Rtmp, Rsrc, Rold); |
|
3135 __ stdcx_(Rtmp, Rptr); |
|
3136 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { |
|
3137 __ bne_predict_not_taken(CCR0, Lretry); |
|
3138 } else { |
|
3139 __ bne( CCR0, Lretry); |
|
3140 } |
|
3141 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); |
|
3142 __ fence(); |
|
3143 %} |
|
3144 |
|
3145 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ |
|
3146 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3147 |
|
3148 MacroAssembler _masm(&cbuf); |
|
3149 Register Rtmp = R0; |
|
3150 Register Rres = $res$$Register; |
|
3151 Register Rsrc = $src$$Register; |
|
3152 Register Rptr = $mem_ptr$$Register; |
|
3153 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3154 Register Rold = RegCollision ? Rtmp : Rres; |
|
3155 |
|
3156 Label Lretry; |
|
3157 __ bind(Lretry); |
|
3158 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3159 __ stwcx_(Rsrc, Rptr); |
|
3160 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { |
|
3161 __ bne_predict_not_taken(CCR0, Lretry); |
|
3162 } else { |
|
3163 __ bne( CCR0, Lretry); |
|
3164 } |
|
3165 if (RegCollision) __ mr(Rres, Rtmp); |
|
3166 __ fence(); |
|
3167 %} |
|
3168 |
|
3169 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ |
|
3170 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3171 |
|
3172 MacroAssembler _masm(&cbuf); |
|
3173 Register Rtmp = R0; |
|
3174 Register Rres = $res$$Register; |
|
3175 Register Rsrc = $src$$Register; |
|
3176 Register Rptr = $mem_ptr$$Register; |
|
3177 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); |
|
3178 Register Rold = RegCollision ? Rtmp : Rres; |
|
3179 |
|
3180 Label Lretry; |
|
3181 __ bind(Lretry); |
|
3182 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); |
|
3183 __ stdcx_(Rsrc, Rptr); |
|
3184 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { |
|
3185 __ bne_predict_not_taken(CCR0, Lretry); |
|
3186 } else { |
|
3187 __ bne( CCR0, Lretry); |
|
3188 } |
|
3189 if (RegCollision) __ mr(Rres, Rtmp); |
|
3190 __ fence(); |
|
3191 %} |
|
3192 |
|
3193 // This enc_class is needed so that scheduler gets proper |
|
3194 // input mapping for latency computation. |
|
3195 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
3196 // TODO: PPC port $archOpcode(ppc64Opcode_andc); |
|
3197 MacroAssembler _masm(&cbuf); |
|
3198 __ andc($dst$$Register, $src1$$Register, $src2$$Register); |
|
3199 %} |
|
3200 |
|
3201 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ |
|
3202 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3203 |
|
3204 MacroAssembler _masm(&cbuf); |
|
3205 |
|
3206 Label done; |
|
3207 __ cmpwi($crx$$CondRegister, $src$$Register, 0); |
|
3208 __ li($dst$$Register, $zero$$constant); |
|
3209 __ beq($crx$$CondRegister, done); |
|
3210 __ li($dst$$Register, $notzero$$constant); |
|
3211 __ bind(done); |
|
3212 %} |
|
3213 |
|
3214 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ |
|
3215 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3216 |
|
3217 MacroAssembler _masm(&cbuf); |
|
3218 |
|
3219 Label done; |
|
3220 __ cmpdi($crx$$CondRegister, $src$$Register, 0); |
|
3221 __ li($dst$$Register, $zero$$constant); |
|
3222 __ beq($crx$$CondRegister, done); |
|
3223 __ li($dst$$Register, $notzero$$constant); |
|
3224 __ bind(done); |
|
3225 %} |
|
3226 |
|
3227 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{ |
|
3228 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
3229 |
|
3230 MacroAssembler _masm(&cbuf); |
|
3231 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
3232 Label done; |
|
3233 __ bso($crx$$CondRegister, done); |
|
3234 __ ld($dst$$Register, Idisp, $mem$$base$$Register); |
|
3235 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
3236 __ bind(done); |
|
3237 %} |
|
3238 |
|
3239 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{ |
|
3240 // TODO: PPC port $archOpcode(ppc64Opcode_bc); |
|
3241 |
|
3242 MacroAssembler _masm(&cbuf); |
|
3243 Label d; // dummy |
|
3244 __ bind(d); |
|
3245 Label* p = ($lbl$$label); |
|
3246 // `p' is `NULL' when this encoding class is used only to |
|
3247 // determine the size of the encoded instruction. |
|
3248 Label& l = (NULL == p)? d : *(p); |
|
3249 int cc = $cmp$$cmpcode; |
|
3250 int flags_reg = $crx$$reg; |
|
3251 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
3252 int bhint = Assembler::bhintNoHint; |
|
3253 |
|
3254 if (UseStaticBranchPredictionForUncommonPathsPPC64) { |
|
3255 if (_prob <= PROB_NEVER) { |
|
3256 bhint = Assembler::bhintIsNotTaken; |
|
3257 } else if (_prob >= PROB_ALWAYS) { |
|
3258 bhint = Assembler::bhintIsTaken; |
|
3259 } |
|
3260 } |
|
3261 |
|
3262 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3263 cc_to_biint(cc, flags_reg), |
|
3264 l); |
|
3265 %} |
|
3266 |
|
3267 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{ |
|
3268 // The scheduler doesn't know about branch shortening, so we set the opcode |
|
3269 // to ppc64Opcode_bc in order to hide this detail from the scheduler. |
|
3270 // TODO: PPC port $archOpcode(ppc64Opcode_bc); |
|
3271 |
|
3272 MacroAssembler _masm(&cbuf); |
|
3273 Label d; // dummy |
|
3274 __ bind(d); |
|
3275 Label* p = ($lbl$$label); |
|
3276 // `p' is `NULL' when this encoding class is used only to |
|
3277 // determine the size of the encoded instruction. |
|
3278 Label& l = (NULL == p)? d : *(p); |
|
3279 int cc = $cmp$$cmpcode; |
|
3280 int flags_reg = $crx$$reg; |
|
3281 int bhint = Assembler::bhintNoHint; |
|
3282 |
|
3283 if (UseStaticBranchPredictionForUncommonPathsPPC64) { |
|
3284 if (_prob <= PROB_NEVER) { |
|
3285 bhint = Assembler::bhintIsNotTaken; |
|
3286 } else if (_prob >= PROB_ALWAYS) { |
|
3287 bhint = Assembler::bhintIsTaken; |
|
3288 } |
|
3289 } |
|
3290 |
|
3291 // Tell the conditional far branch to optimize itself when being relocated. |
|
3292 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3293 cc_to_biint(cc, flags_reg), |
|
3294 l, |
|
3295 MacroAssembler::bc_far_optimize_on_relocate); |
|
3296 %} |
|
3297 |
|
3298 // Branch used with Power6 scheduling (can be shortened without changing the node). |
|
3299 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{ |
|
3300 // The scheduler doesn't know about branch shortening, so we set the opcode |
|
3301 // to ppc64Opcode_bc in order to hide this detail from the scheduler. |
|
3302 // TODO: PPC port $archOpcode(ppc64Opcode_bc); |
|
3303 |
|
3304 MacroAssembler _masm(&cbuf); |
|
3305 Label d; // dummy |
|
3306 __ bind(d); |
|
3307 Label* p = ($lbl$$label); |
|
3308 // `p' is `NULL' when this encoding class is used only to |
|
3309 // determine the size of the encoded instruction. |
|
3310 Label& l = (NULL == p)? d : *(p); |
|
3311 int cc = $cmp$$cmpcode; |
|
3312 int flags_reg = $crx$$reg; |
|
3313 int bhint = Assembler::bhintNoHint; |
|
3314 |
|
3315 if (UseStaticBranchPredictionForUncommonPathsPPC64) { |
|
3316 if (_prob <= PROB_NEVER) { |
|
3317 bhint = Assembler::bhintIsNotTaken; |
|
3318 } else if (_prob >= PROB_ALWAYS) { |
|
3319 bhint = Assembler::bhintIsTaken; |
|
3320 } |
|
3321 } |
|
3322 |
|
3323 #if 0 // TODO: PPC port |
|
3324 if (_size == 8) { |
|
3325 // Tell the conditional far branch to optimize itself when being relocated. |
|
3326 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3327 cc_to_biint(cc, flags_reg), |
|
3328 l, |
|
3329 MacroAssembler::bc_far_optimize_on_relocate); |
|
3330 } else { |
|
3331 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), |
|
3332 cc_to_biint(cc, flags_reg), |
|
3333 l); |
|
3334 } |
|
3335 #endif |
|
3336 Unimplemented(); |
|
3337 %} |
|
3338 |
|
3339 // Postalloc expand emitter for loading a replicatef float constant from |
|
3340 // the method's TOC. |
|
3341 // Enc_class needed as consttanttablebase is not supported by postalloc |
|
3342 // expand. |
|
3343 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ |
|
3344 // Create new nodes. |
|
3345 |
|
3346 // Make an operand with the bit pattern to load as float. |
|
3347 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF())); |
|
3348 |
|
3349 loadConLNodesTuple loadConLNodes = |
|
3350 loadConLNodesTuple_create(C, ra_, n_toc, op_repl, |
|
3351 ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
3352 |
|
3353 // Push new nodes. |
|
3354 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); |
|
3355 if (loadConLNodes._last) nodes->push(loadConLNodes._last); |
|
3356 |
|
3357 assert(nodes->length() >= 1, "must have created at least 1 node"); |
|
3358 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); |
|
3359 %} |
|
3360 |
|
3361 // This enc_class is needed so that scheduler gets proper |
|
3362 // input mapping for latency computation. |
|
3363 enc_class enc_poll(immI dst, iRegLdst poll) %{ |
|
3364 // TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
3365 // Fake operand dst needed for PPC scheduler. |
|
3366 assert($dst$$constant == 0x0, "dst must be 0x0"); |
|
3367 |
|
3368 MacroAssembler _masm(&cbuf); |
|
3369 // Mark the code position where the load from the safepoint |
|
3370 // polling page was emitted as relocInfo::poll_type. |
|
3371 __ relocate(relocInfo::poll_type); |
|
3372 __ load_from_polling_page($poll$$Register); |
|
3373 %} |
|
3374 |
|
3375 // A Java static call or a runtime call. |
|
3376 // |
|
3377 // Branch-and-link relative to a trampoline. |
|
3378 // The trampoline loads the target address and does a long branch to there. |
|
3379 // In case we call java, the trampoline branches to a interpreter_stub |
|
3380 // which loads the inline cache and the real call target from the constant pool. |
|
3381 // |
|
3382 // This basically looks like this: |
|
3383 // |
|
3384 // >>>> consts -+ -+ |
|
3385 // | |- offset1 |
|
3386 // [call target1] | <-+ |
|
3387 // [IC cache] |- offset2 |
|
3388 // [call target2] <--+ |
|
3389 // |
|
3390 // <<<< consts |
|
3391 // >>>> insts |
|
3392 // |
|
3393 // bl offset16 -+ -+ ??? // How many bits available? |
|
3394 // | | |
|
3395 // <<<< insts | | |
|
3396 // >>>> stubs | | |
|
3397 // | |- trampoline_stub_Reloc |
|
3398 // trampoline stub: | <-+ |
|
3399 // r2 = toc | |
|
3400 // r2 = [r2 + offset1] | // Load call target1 from const section |
|
3401 // mtctr r2 | |
|
3402 // bctr |- static_stub_Reloc |
|
3403 // comp_to_interp_stub: <---+ |
|
3404 // r1 = toc |
|
3405 // ICreg = [r1 + IC_offset] // Load IC from const section |
|
3406 // r1 = [r1 + offset2] // Load call target2 from const section |
|
3407 // mtctr r1 |
|
3408 // bctr |
|
3409 // |
|
3410 // <<<< stubs |
|
3411 // |
|
3412 // The call instruction in the code either |
|
3413 // - Branches directly to a compiled method if the offset is encodable in instruction. |
|
3414 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. |
|
3415 // - Branches to the compiled_to_interp stub if the target is interpreted. |
|
3416 // |
|
3417 // Further there are three relocations from the loads to the constants in |
|
3418 // the constant section. |
|
3419 // |
|
3420 // Usage of r1 and r2 in the stubs allows to distinguish them. |
|
3421 enc_class enc_java_static_call(method meth) %{ |
|
3422 // TODO: PPC port $archOpcode(ppc64Opcode_bl); |
|
3423 |
|
3424 MacroAssembler _masm(&cbuf); |
|
3425 address entry_point = (address)$meth$$method; |
|
3426 |
|
3427 if (!_method) { |
|
3428 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. |
|
3429 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); |
|
3430 } else { |
|
3431 // Remember the offset not the address. |
|
3432 const int start_offset = __ offset(); |
|
3433 // The trampoline stub. |
|
3434 if (!Compile::current()->in_scratch_emit_size()) { |
|
3435 // No entry point given, use the current pc. |
|
3436 // Make sure branch fits into |
|
3437 if (entry_point == 0) entry_point = __ pc(); |
|
3438 |
|
3439 // Put the entry point as a constant into the constant pool. |
|
3440 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); |
|
3441 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); |
|
3442 |
|
3443 // Emit the trampoline stub which will be related to the branch-and-link below. |
|
3444 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); |
|
3445 __ relocate(_optimized_virtual ? |
|
3446 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); |
|
3447 } |
|
3448 |
|
3449 // The real call. |
|
3450 // Note: At this point we do not have the address of the trampoline |
|
3451 // stub, and the entry point might be too far away for bl, so __ pc() |
|
3452 // serves as dummy and the bl will be patched later. |
|
3453 cbuf.set_insts_mark(); |
|
3454 __ bl(__ pc()); // Emits a relocation. |
|
3455 |
|
3456 // The stub for call to interpreter. |
|
3457 CompiledStaticCall::emit_to_interp_stub(cbuf); |
|
3458 } |
|
3459 %} |
|
3460 |
|
3461 // Emit a method handle call. |
|
3462 // |
|
3463 // Method handle calls from compiled to compiled are going thru a |
|
3464 // c2i -> i2c adapter, extending the frame for their arguments. The |
|
3465 // caller however, returns directly to the compiled callee, that has |
|
3466 // to cope with the extended frame. We restore the original frame by |
|
3467 // loading the callers sp and adding the calculated framesize. |
|
3468 enc_class enc_java_handle_call(method meth) %{ |
|
3469 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3470 |
|
3471 MacroAssembler _masm(&cbuf); |
|
3472 address entry_point = (address)$meth$$method; |
|
3473 |
|
3474 // Remember the offset not the address. |
|
3475 const int start_offset = __ offset(); |
|
3476 // The trampoline stub. |
|
3477 if (!ra_->C->in_scratch_emit_size()) { |
|
3478 // No entry point given, use the current pc. |
|
3479 // Make sure branch fits into |
|
3480 if (entry_point == 0) entry_point = __ pc(); |
|
3481 |
|
3482 // Put the entry point as a constant into the constant pool. |
|
3483 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); |
|
3484 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); |
|
3485 |
|
3486 // Emit the trampoline stub which will be related to the branch-and-link below. |
|
3487 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); |
|
3488 assert(_optimized_virtual, "methodHandle call should be a virtual call"); |
|
3489 __ relocate(relocInfo::opt_virtual_call_type); |
|
3490 } |
|
3491 |
|
3492 // The real call. |
|
3493 // Note: At this point we do not have the address of the trampoline |
|
3494 // stub, and the entry point might be too far away for bl, so __ pc() |
|
3495 // serves as dummy and the bl will be patched later. |
|
3496 cbuf.set_insts_mark(); |
|
3497 __ bl(__ pc()); // Emits a relocation. |
|
3498 |
|
3499 assert(_method, "execute next statement conditionally"); |
|
3500 // The stub for call to interpreter. |
|
3501 CompiledStaticCall::emit_to_interp_stub(cbuf); |
|
3502 |
|
3503 // Restore original sp. |
|
3504 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp. |
|
3505 const long framesize = ra_->C->frame_slots() << LogBytesPerInt; |
|
3506 unsigned int bytes = (unsigned int)framesize; |
|
3507 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); |
|
3508 if (Assembler::is_simm(-offset, 16)) { |
|
3509 __ addi(R1_SP, R11_scratch1, -offset); |
|
3510 } else { |
|
3511 __ load_const_optimized(R12_scratch2, -offset); |
|
3512 __ add(R1_SP, R11_scratch1, R12_scratch2); |
|
3513 } |
|
3514 #ifdef ASSERT |
|
3515 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. |
|
3516 __ cmpd(CCR0, R11_scratch1, R12_scratch2); |
|
3517 __ asm_assert_eq("backlink changed", 0x8000); |
|
3518 #endif |
|
3519 // If fails should store backlink before unextending. |
|
3520 |
|
3521 if (ra_->C->env()->failing()) |
|
3522 return; |
|
3523 %} |
|
3524 |
|
3525 // Second node of expanded dynamic call - the call. |
|
3526 enc_class enc_java_dynamic_call_sched(method meth) %{ |
|
3527 // TODO: PPC port $archOpcode(ppc64Opcode_bl); |
|
3528 |
|
3529 MacroAssembler _masm(&cbuf); |
|
3530 |
|
3531 if (!ra_->C->in_scratch_emit_size()) { |
|
3532 // Create a call trampoline stub for the given method. |
|
3533 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; |
|
3534 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); |
|
3535 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); |
|
3536 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); |
|
3537 |
|
3538 if (ra_->C->env()->failing()) |
|
3539 return; |
|
3540 |
|
3541 // Build relocation at call site with ic position as data. |
|
3542 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || |
|
3543 (_load_ic_hi_node == NULL && _load_ic_node != NULL), |
|
3544 "must have one, but can't have both"); |
|
3545 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || |
|
3546 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), |
|
3547 "must contain instruction offset"); |
|
3548 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL |
|
3549 ? _load_ic_hi_node->_cbuf_insts_offset |
|
3550 : _load_ic_node->_cbuf_insts_offset; |
|
3551 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); |
|
3552 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), |
|
3553 "should be load from TOC"); |
|
3554 |
|
3555 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); |
|
3556 } |
|
3557 |
|
3558 // At this point I do not have the address of the trampoline stub, |
|
3559 // and the entry point might be too far away for bl. Pc() serves |
|
3560 // as dummy and bl will be patched later. |
|
3561 __ bl((address) __ pc()); |
|
3562 %} |
|
3563 |
|
3564 // postalloc expand emitter for virtual calls. |
|
3565 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ |
|
3566 // Toc is in return address field, though not accessible via postalloc_expand |
|
3567 // functionaliy. |
|
3568 Node *toc = in(TypeFunc::ReturnAdr); |
|
3569 |
|
3570 // Create the nodes for loading the IC from the TOC. |
|
3571 loadConLNodesTuple loadConLNodes_IC = |
|
3572 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()), |
|
3573 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); |
|
3574 |
|
3575 // Create the call node. |
|
3576 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode(); |
|
3577 call->_method_handle_invoke = _method_handle_invoke; |
|
3578 call->_vtable_index = _vtable_index; |
|
3579 call->_method = _method; |
|
3580 call->_bci = _bci; |
|
3581 call->_optimized_virtual = _optimized_virtual; |
|
3582 call->_tf = _tf; |
|
3583 call->_entry_point = _entry_point; |
|
3584 call->_cnt = _cnt; |
|
3585 call->_argsize = _argsize; |
|
3586 call->_oop_map = _oop_map; |
|
3587 call->_jvms = _jvms; |
|
3588 call->_jvmadj = _jvmadj; |
|
3589 call->_in_rms = _in_rms; |
|
3590 call->_nesting = _nesting; |
|
3591 |
|
3592 // New call needs all inputs of old call. |
|
3593 // Req... |
|
3594 for (uint i = 0; i < req(); ++i) { |
|
3595 if (i != TypeFunc::ReturnAdr) { |
|
3596 call->add_req(in(i)); |
|
3597 } else { |
|
3598 // The expanded node does not need toc any more. |
|
3599 call->add_req(C->top()); |
|
3600 } |
|
3601 } |
|
3602 // ...as well as prec |
|
3603 for (uint i = req(); i < len() ; ++i) { |
|
3604 call->add_prec(in(i)); |
|
3605 } |
|
3606 |
|
3607 // The cache must come before the call, but it's not a req edge. |
|
3608 // GL: actually it should be a req edge to express that the |
|
3609 // register must be live in the Call. But as R19 is declared to be |
|
3610 // the inline_cache_reg that's fine. |
|
3611 call->add_prec(loadConLNodes_IC._last); |
|
3612 // Remember nodes loading the inline cache into r19. |
|
3613 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; |
|
3614 call->_load_ic_node = loadConLNodes_IC._small; |
|
3615 |
|
3616 // Operands for new nodes. |
|
3617 call->_opnds[0] = _opnds[0]; |
|
3618 call->_opnds[1] = _opnds[1]; |
|
3619 |
|
3620 // Only the inline cache is associated with a register. |
|
3621 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); |
|
3622 |
|
3623 // Push new nodes. |
|
3624 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); |
|
3625 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); |
|
3626 nodes->push(call); |
|
3627 %} |
|
3628 |
|
3629 // Compound version of call dynamic |
|
3630 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ |
|
3631 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3632 MacroAssembler _masm(&cbuf); |
|
3633 int start_offset = __ offset(); |
|
3634 |
|
3635 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; |
|
3636 #if 0 |
|
3637 if (_vtable_index < 0) { |
|
3638 // Must be invalid_vtable_index, not nonvirtual_vtable_index. |
|
3639 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); |
|
3640 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); |
|
3641 AddressLiteral oop = __ allocate_metadata_address((Metadata *)Universe::non_oop_word()); |
|
3642 |
|
3643 address virtual_call_oop_addr = __ pc(); |
|
3644 __ load_const_from_method_toc(ic_reg, oop, Rtoc); |
|
3645 // CALL to fixup routine. Fixup routine uses ScopeDesc info |
|
3646 // to determine who we intended to call. |
|
3647 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); |
|
3648 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); |
|
3649 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, |
|
3650 "Fix constant in ret_addr_offset()"); |
|
3651 } else { |
|
3652 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); |
|
3653 // Go thru the vtable. Get receiver klass. Receiver already |
|
3654 // checked for non-null. If we'll go thru a C2I adapter, the |
|
3655 // interpreter expects method in R19_method. |
|
3656 |
|
3657 __ load_klass(R11_scratch1, R3); |
|
3658 |
|
3659 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); |
|
3660 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); |
|
3661 __ li(R19_method, v_off); |
|
3662 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); |
|
3663 // NOTE: for vtable dispatches, the vtable entry will never be |
|
3664 // null. However it may very well end up in handle_wrong_method |
|
3665 // if the method is abstract for the particular class. |
|
3666 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); |
|
3667 // Call target. Either compiled code or C2I adapter. |
|
3668 __ mtctr(R11_scratch1); |
|
3669 __ bctrl(); |
|
3670 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { |
|
3671 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); |
|
3672 } |
|
3673 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, |
|
3674 "Fix constant in ret_addr_offset()"); |
|
3675 } |
|
3676 #endif |
|
3677 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). |
|
3678 %} |
|
3679 |
|
3680 // a runtime call |
|
3681 enc_class enc_java_to_runtime_call (method meth) %{ |
|
3682 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
3683 |
|
3684 MacroAssembler _masm(&cbuf); |
|
3685 const address start_pc = __ pc(); |
|
3686 |
|
3687 // The function we're going to call. |
|
3688 FunctionDescriptor fdtemp; |
|
3689 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; |
|
3690 |
|
3691 Register Rtoc = R12_scratch2; |
|
3692 // Calculate the method's TOC. |
|
3693 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); |
|
3694 // Put entry, env, toc into the constant pool, this needs up to 3 constant |
|
3695 // pool entries; call_c_using_toc will optimize the call. |
|
3696 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); |
|
3697 |
|
3698 // Check the ret_addr_offset. |
|
3699 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, |
|
3700 "Fix constant in ret_addr_offset()"); |
|
3701 %} |
|
3702 |
|
3703 // Move to ctr for leaf call. |
|
3704 // This enc_class is needed so that scheduler gets proper |
|
3705 // input mapping for latency computation. |
|
3706 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ |
|
3707 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); |
|
3708 MacroAssembler _masm(&cbuf); |
|
3709 __ mtctr($src$$Register); |
|
3710 %} |
|
3711 |
|
3712 // postalloc expand emitter for runtime leaf calls. |
|
3713 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ |
|
3714 // Get the struct that describes the function we are about to call. |
|
3715 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); |
|
3716 assert(fd, "need fd here"); |
|
3717 // new nodes |
|
3718 loadConLNodesTuple loadConLNodes_Entry; |
|
3719 loadConLNodesTuple loadConLNodes_Env; |
|
3720 loadConLNodesTuple loadConLNodes_Toc; |
|
3721 MachNode *mtctr = NULL; |
|
3722 MachCallLeafNode *call = NULL; |
|
3723 |
|
3724 // Create nodes and operands for loading the entry point. |
|
3725 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->entry()), |
|
3726 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); |
|
3727 |
|
3728 |
|
3729 // Create nodes and operands for loading the env pointer. |
|
3730 if (fd->env() != NULL) { |
|
3731 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()), |
|
3732 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); |
|
3733 } else { |
|
3734 loadConLNodes_Env._large_hi = NULL; |
|
3735 loadConLNodes_Env._large_lo = NULL; |
|
3736 loadConLNodes_Env._small = NULL; |
|
3737 loadConLNodes_Env._last = new (C) loadConL16Node(); |
|
3738 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper(); |
|
3739 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0); |
|
3740 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); |
|
3741 } |
|
3742 |
|
3743 // Create nodes and operands for loading the Toc point. |
|
3744 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()), |
|
3745 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); |
|
3746 // mtctr node |
|
3747 mtctr = new (C) CallLeafDirect_mtctrNode(); |
|
3748 |
|
3749 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); |
|
3750 mtctr->add_req(0, loadConLNodes_Entry._last); |
|
3751 |
|
3752 mtctr->_opnds[0] = new (C) iRegLdstOper(); |
|
3753 mtctr->_opnds[1] = new (C) iRegLdstOper(); |
|
3754 |
|
3755 // call node |
|
3756 call = new (C) CallLeafDirectNode(); |
|
3757 |
|
3758 call->_opnds[0] = _opnds[0]; |
|
3759 call->_opnds[1] = new (C) methodOper((intptr_t) fd->entry()); // may get set later |
|
3760 |
|
3761 // Make the new call node look like the old one. |
|
3762 call->_name = _name; |
|
3763 call->_tf = _tf; |
|
3764 call->_entry_point = _entry_point; |
|
3765 call->_cnt = _cnt; |
|
3766 call->_argsize = _argsize; |
|
3767 call->_oop_map = _oop_map; |
|
3768 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); |
|
3769 call->_jvms = NULL; |
|
3770 call->_jvmadj = _jvmadj; |
|
3771 call->_in_rms = _in_rms; |
|
3772 call->_nesting = _nesting; |
|
3773 |
|
3774 |
|
3775 // New call needs all inputs of old call. |
|
3776 // Req... |
|
3777 for (uint i = 0; i < req(); ++i) { |
|
3778 if (i != TypeFunc::ReturnAdr) { |
|
3779 call->add_req(in(i)); |
|
3780 } else { |
|
3781 // put the mtctr where ReturnAdr would be |
|
3782 call->add_req(mtctr); |
|
3783 } |
|
3784 } |
|
3785 |
|
3786 // These must be reqired edges, as the registers are live up to |
|
3787 // the call. Else the constants are handled as kills. |
|
3788 call->add_req(loadConLNodes_Env._last); |
|
3789 call->add_req(loadConLNodes_Toc._last); |
|
3790 |
|
3791 // ...as well as prec |
|
3792 for (uint i = req(); i < len(); ++i) { |
|
3793 call->add_prec(in(i)); |
|
3794 } |
|
3795 |
|
3796 // registers |
|
3797 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); |
|
3798 |
|
3799 // Insert the new nodes. |
|
3800 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); |
|
3801 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); |
|
3802 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); |
|
3803 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); |
|
3804 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); |
|
3805 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); |
|
3806 nodes->push(mtctr); |
|
3807 nodes->push(call); |
|
3808 %} |
|
3809 %} |
|
3810 |
|
3811 //----------FRAME-------------------------------------------------------------- |
|
3812 // Definition of frame structure and management information. |
|
3813 |
|
3814 frame %{ |
|
3815 // What direction does stack grow in (assumed to be same for native & Java). |
|
3816 stack_direction(TOWARDS_LOW); |
|
3817 |
|
3818 // These two registers define part of the calling convention between |
|
3819 // compiled code and the interpreter. |
|
3820 |
|
3821 // Inline Cache Register or methodOop for I2C. |
|
3822 inline_cache_reg(R19); // R19_method |
|
3823 |
|
3824 // Method Oop Register when calling interpreter. |
|
3825 interpreter_method_oop_reg(R19); // R19_method |
|
3826 |
|
3827 // Optional: name the operand used by cisc-spilling to access |
|
3828 // [stack_pointer + offset]. |
|
3829 cisc_spilling_operand_name(indOffset); |
|
3830 |
|
3831 // Number of stack slots consumed by a Monitor enter. |
|
3832 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); |
|
3833 |
|
3834 // Compiled code's Frame Pointer. |
|
3835 frame_pointer(R1); // R1_SP |
|
3836 |
|
3837 // Interpreter stores its frame pointer in a register which is |
|
3838 // stored to the stack by I2CAdaptors. I2CAdaptors convert from |
|
3839 // interpreted java to compiled java. |
|
3840 // |
|
3841 // R14_state holds pointer to caller's cInterpreter. |
|
3842 interpreter_frame_pointer(R14); // R14_state |
|
3843 |
|
3844 stack_alignment(frame::alignment_in_bytes); |
|
3845 |
|
3846 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); |
|
3847 |
|
3848 // Number of outgoing stack slots killed above the |
|
3849 // out_preserve_stack_slots for calls to C. Supports the var-args |
|
3850 // backing area for register parms. |
|
3851 // |
|
3852 varargs_C_out_slots_killed(((frame::abi_112_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); |
|
3853 |
|
3854 // The after-PROLOG location of the return address. Location of |
|
3855 // return address specifies a type (REG or STACK) and a number |
|
3856 // representing the register number (i.e. - use a register name) or |
|
3857 // stack slot. |
|
3858 // |
|
3859 // A: Link register is stored in stack slot ... |
|
3860 // M: ... but it's in the caller's frame according to PPC-64 ABI. |
|
3861 // J: Therefore, we make sure that the link register is also in R11_scratch1 |
|
3862 // at the end of the prolog. |
|
3863 // B: We use R20, now. |
|
3864 //return_addr(REG R20); |
|
3865 |
|
3866 // G: After reading the comments made by all the luminaries on their |
|
3867 // failure to tell the compiler where the return address really is, |
|
3868 // I hardly dare to try myself. However, I'm convinced it's in slot |
|
3869 // 4 what apparently works and saves us some spills. |
|
3870 return_addr(STACK 4); |
|
3871 |
|
3872 // This is the body of the function |
|
3873 // |
|
3874 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs |
|
3875 // uint length, // length of array |
|
3876 // bool is_outgoing) |
|
3877 // |
|
3878 // The `sig' array is to be updated. sig[j] represents the location |
|
3879 // of the j-th argument, either a register or a stack slot. |
|
3880 |
|
3881 // Comment taken from i486.ad: |
|
3882 // Body of function which returns an integer array locating |
|
3883 // arguments either in registers or in stack slots. Passed an array |
|
3884 // of ideal registers called "sig" and a "length" count. Stack-slot |
|
3885 // offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
3886 // arguments for a CALLEE. Incoming stack arguments are |
|
3887 // automatically biased by the preserve_stack_slots field above. |
|
3888 calling_convention %{ |
|
3889 // No difference between ingoing/outgoing. Just pass false. |
|
3890 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); |
|
3891 %} |
|
3892 |
|
3893 // Comment taken from i486.ad: |
|
3894 // Body of function which returns an integer array locating |
|
3895 // arguments either in registers or in stack slots. Passed an array |
|
3896 // of ideal registers called "sig" and a "length" count. Stack-slot |
|
3897 // offsets are based on outgoing arguments, i.e. a CALLER setting up |
|
3898 // arguments for a CALLEE. Incoming stack arguments are |
|
3899 // automatically biased by the preserve_stack_slots field above. |
|
3900 c_calling_convention %{ |
|
3901 // This is obviously always outgoing. |
|
3902 // C argument in register AND stack slot. |
|
3903 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
|
3904 %} |
|
3905 |
|
3906 // Location of native (C/C++) and interpreter return values. This |
|
3907 // is specified to be the same as Java. In the 32-bit VM, long |
|
3908 // values are actually returned from native calls in O0:O1 and |
|
3909 // returned to the interpreter in I0:I1. The copying to and from |
|
3910 // the register pairs is done by the appropriate call and epilog |
|
3911 // opcodes. This simplifies the register allocator. |
|
3912 c_return_value %{ |
|
3913 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || |
|
3914 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), |
|
3915 "only return normal values"); |
|
3916 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL |
|
3917 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; |
|
3918 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; |
|
3919 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); |
|
3920 %} |
|
3921 |
|
3922 // Location of compiled Java return values. Same as C |
|
3923 return_value %{ |
|
3924 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || |
|
3925 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), |
|
3926 "only return normal values"); |
|
3927 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL |
|
3928 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; |
|
3929 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; |
|
3930 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); |
|
3931 %} |
|
3932 %} |
|
3933 |
|
3934 |
|
3935 //----------ATTRIBUTES--------------------------------------------------------- |
|
3936 |
|
3937 //----------Operand Attributes------------------------------------------------- |
|
3938 op_attrib op_cost(1); // Required cost attribute. |
|
3939 |
|
3940 //----------Instruction Attributes--------------------------------------------- |
|
3941 |
|
3942 // Cost attribute. required. |
|
3943 ins_attrib ins_cost(DEFAULT_COST); |
|
3944 |
|
3945 // Is this instruction a non-matching short branch variant of some |
|
3946 // long branch? Not required. |
|
3947 ins_attrib ins_short_branch(0); |
|
3948 |
|
3949 // This instruction does implicit checks at the given machine-instruction offset |
|
3950 // (optional attribute). |
|
3951 ins_attrib ins_implicit_check_offset(-1); // TODO: PPC port |
|
3952 |
|
3953 ins_attrib ins_implicit_check_follows_matched_true_path(true); |
|
3954 ins_attrib ins_is_TrapBasedCheckNode(true); |
|
3955 |
|
3956 // Number of constants. |
|
3957 // This instruction uses the given number of constants |
|
3958 // (optional attribute). |
|
3959 // This is needed to determine in time whether the constant pool will |
|
3960 // exceed 4000 entries. Before postalloc_expand the overall number of constants |
|
3961 // is determined. It's also used to compute the constant pool size |
|
3962 // in Output(). |
|
3963 ins_attrib ins_num_consts(0); |
|
3964 |
|
3965 // Required alignment attribute (must be a power of 2) specifies the |
|
3966 // alignment that some part of the instruction (not necessarily the |
|
3967 // start) requires. If > 1, a compute_padding() function must be |
|
3968 // provided for the instruction. |
|
3969 ins_attrib ins_alignment(1); |
|
3970 |
|
3971 // Enforce/prohibit rematerializations. |
|
3972 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' |
|
3973 // then rematerialization of that instruction is prohibited and the |
|
3974 // instruction's value will be spilled if necessary. |
|
3975 // Causes that MachNode::rematerialize() returns false. |
|
3976 // - If an instruction is attributed with 'ins_should_rematerialize(true)' |
|
3977 // then rematerialization should be enforced and a copy of the instruction |
|
3978 // should be inserted if possible; rematerialization is not guaranteed. |
|
3979 // Note: this may result in rematerializations in front of every use. |
|
3980 // Causes that MachNode::rematerialize() can return true. |
|
3981 // (optional attribute) |
|
3982 ins_attrib ins_cannot_rematerialize(false); |
|
3983 ins_attrib ins_should_rematerialize(false); |
|
3984 |
|
3985 // Instruction has variable size depending on alignment. |
|
3986 ins_attrib ins_variable_size_depending_on_alignment(false); |
|
3987 |
|
3988 // Instruction is a nop. |
|
3989 ins_attrib ins_is_nop(false); |
|
3990 |
|
3991 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). |
|
3992 ins_attrib ins_use_mach_if_fast_lock_node(false); |
|
3993 |
|
3994 // Field for the toc offset of a constant. |
|
3995 // |
|
3996 // This is needed if the toc offset is not encodable as an immediate in |
|
3997 // the PPC load instruction. If so, the upper (hi) bits of the offset are |
|
3998 // added to the toc, and from this a load with immediate is performed. |
|
3999 // With postalloc expand, we get two nodes that require the same offset |
|
4000 // but which don't know about each other. The offset is only known |
|
4001 // when the constant is added to the constant pool during emitting. |
|
4002 // It is generated in the 'hi'-node adding the upper bits, and saved |
|
4003 // in this node. The 'lo'-node has a link to the 'hi'-node and reads |
|
4004 // the offset from there when it gets encoded. |
|
4005 ins_attrib ins_field_const_toc_offset(0); |
|
4006 ins_attrib ins_field_const_toc_offset_hi_node(0); |
|
4007 |
|
4008 // A field that can hold the instructions offset in the code buffer. |
|
4009 // Set in the nodes emitter. |
|
4010 ins_attrib ins_field_cbuf_insts_offset(-1); |
|
4011 |
|
4012 // Fields for referencing a call's load-IC-node. |
|
4013 // If the toc offset can not be encoded as an immediate in a load, we |
|
4014 // use two nodes. |
|
4015 ins_attrib ins_field_load_ic_hi_node(0); |
|
4016 ins_attrib ins_field_load_ic_node(0); |
|
4017 |
|
4018 //----------OPERANDS----------------------------------------------------------- |
|
4019 // Operand definitions must precede instruction definitions for correct |
|
4020 // parsing in the ADLC because operands constitute user defined types |
|
4021 // which are used in instruction definitions. |
|
4022 // |
|
4023 // Formats are generated automatically for constants and base registers. |
|
4024 |
|
4025 //----------Simple Operands---------------------------------------------------- |
|
4026 // Immediate Operands |
|
4027 |
|
4028 // Integer Immediate: 32-bit |
|
4029 operand immI() %{ |
|
4030 match(ConI); |
|
4031 op_cost(40); |
|
4032 format %{ %} |
|
4033 interface(CONST_INTER); |
|
4034 %} |
|
4035 |
|
4036 operand immI8() %{ |
|
4037 predicate(Assembler::is_simm(n->get_int(), 8)); |
|
4038 op_cost(0); |
|
4039 match(ConI); |
|
4040 format %{ %} |
|
4041 interface(CONST_INTER); |
|
4042 %} |
|
4043 |
|
4044 // Integer Immediate: 16-bit |
|
4045 operand immI16() %{ |
|
4046 predicate(Assembler::is_simm(n->get_int(), 16)); |
|
4047 op_cost(0); |
|
4048 match(ConI); |
|
4049 format %{ %} |
|
4050 interface(CONST_INTER); |
|
4051 %} |
|
4052 |
|
4053 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. |
|
4054 operand immIhi16() %{ |
|
4055 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); |
|
4056 match(ConI); |
|
4057 op_cost(0); |
|
4058 format %{ %} |
|
4059 interface(CONST_INTER); |
|
4060 %} |
|
4061 |
|
4062 operand immInegpow2() %{ |
|
4063 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); |
|
4064 match(ConI); |
|
4065 op_cost(0); |
|
4066 format %{ %} |
|
4067 interface(CONST_INTER); |
|
4068 %} |
|
4069 |
|
4070 operand immIpow2minus1() %{ |
|
4071 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); |
|
4072 match(ConI); |
|
4073 op_cost(0); |
|
4074 format %{ %} |
|
4075 interface(CONST_INTER); |
|
4076 %} |
|
4077 |
|
4078 operand immIpowerOf2() %{ |
|
4079 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); |
|
4080 match(ConI); |
|
4081 op_cost(0); |
|
4082 format %{ %} |
|
4083 interface(CONST_INTER); |
|
4084 %} |
|
4085 |
|
4086 // Unsigned Integer Immediate: the values 0-31 |
|
4087 operand uimmI5() %{ |
|
4088 predicate(Assembler::is_uimm(n->get_int(), 5)); |
|
4089 match(ConI); |
|
4090 op_cost(0); |
|
4091 format %{ %} |
|
4092 interface(CONST_INTER); |
|
4093 %} |
|
4094 |
|
4095 // Unsigned Integer Immediate: 6-bit |
|
4096 operand uimmI6() %{ |
|
4097 predicate(Assembler::is_uimm(n->get_int(), 6)); |
|
4098 match(ConI); |
|
4099 op_cost(0); |
|
4100 format %{ %} |
|
4101 interface(CONST_INTER); |
|
4102 %} |
|
4103 |
|
4104 // Unsigned Integer Immediate: 6-bit int, greater than 32 |
|
4105 operand uimmI6_ge32() %{ |
|
4106 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); |
|
4107 match(ConI); |
|
4108 op_cost(0); |
|
4109 format %{ %} |
|
4110 interface(CONST_INTER); |
|
4111 %} |
|
4112 |
|
4113 // Unsigned Integer Immediate: 15-bit |
|
4114 operand uimmI15() %{ |
|
4115 predicate(Assembler::is_uimm(n->get_int(), 15)); |
|
4116 match(ConI); |
|
4117 op_cost(0); |
|
4118 format %{ %} |
|
4119 interface(CONST_INTER); |
|
4120 %} |
|
4121 |
|
4122 // Unsigned Integer Immediate: 16-bit |
|
4123 operand uimmI16() %{ |
|
4124 predicate(Assembler::is_uimm(n->get_int(), 16)); |
|
4125 match(ConI); |
|
4126 op_cost(0); |
|
4127 format %{ %} |
|
4128 interface(CONST_INTER); |
|
4129 %} |
|
4130 |
|
4131 // constant 'int 0'. |
|
4132 operand immI_0() %{ |
|
4133 predicate(n->get_int() == 0); |
|
4134 match(ConI); |
|
4135 op_cost(0); |
|
4136 format %{ %} |
|
4137 interface(CONST_INTER); |
|
4138 %} |
|
4139 |
|
4140 // constant 'int 1'. |
|
4141 operand immI_1() %{ |
|
4142 predicate(n->get_int() == 1); |
|
4143 match(ConI); |
|
4144 op_cost(0); |
|
4145 format %{ %} |
|
4146 interface(CONST_INTER); |
|
4147 %} |
|
4148 |
|
4149 // constant 'int -1'. |
|
4150 operand immI_minus1() %{ |
|
4151 predicate(n->get_int() == -1); |
|
4152 match(ConI); |
|
4153 op_cost(0); |
|
4154 format %{ %} |
|
4155 interface(CONST_INTER); |
|
4156 %} |
|
4157 |
|
4158 // int value 16. |
|
4159 operand immI_16() %{ |
|
4160 predicate(n->get_int() == 16); |
|
4161 match(ConI); |
|
4162 op_cost(0); |
|
4163 format %{ %} |
|
4164 interface(CONST_INTER); |
|
4165 %} |
|
4166 |
|
4167 // int value 24. |
|
4168 operand immI_24() %{ |
|
4169 predicate(n->get_int() == 24); |
|
4170 match(ConI); |
|
4171 op_cost(0); |
|
4172 format %{ %} |
|
4173 interface(CONST_INTER); |
|
4174 %} |
|
4175 |
|
4176 // Compressed oops constants |
|
4177 // Pointer Immediate |
|
4178 operand immN() %{ |
|
4179 match(ConN); |
|
4180 |
|
4181 op_cost(10); |
|
4182 format %{ %} |
|
4183 interface(CONST_INTER); |
|
4184 %} |
|
4185 |
|
4186 // NULL Pointer Immediate |
|
4187 operand immN_0() %{ |
|
4188 predicate(n->get_narrowcon() == 0); |
|
4189 match(ConN); |
|
4190 |
|
4191 op_cost(0); |
|
4192 format %{ %} |
|
4193 interface(CONST_INTER); |
|
4194 %} |
|
4195 |
|
4196 // Compressed klass constants |
|
4197 operand immNKlass() %{ |
|
4198 match(ConNKlass); |
|
4199 |
|
4200 op_cost(0); |
|
4201 format %{ %} |
|
4202 interface(CONST_INTER); |
|
4203 %} |
|
4204 |
|
4205 // This operand can be used to avoid matching of an instruct |
|
4206 // with chain rule. |
|
4207 operand immNKlass_NM() %{ |
|
4208 match(ConNKlass); |
|
4209 predicate(false); |
|
4210 op_cost(0); |
|
4211 format %{ %} |
|
4212 interface(CONST_INTER); |
|
4213 %} |
|
4214 |
|
4215 // Pointer Immediate: 64-bit |
|
4216 operand immP() %{ |
|
4217 match(ConP); |
|
4218 op_cost(0); |
|
4219 format %{ %} |
|
4220 interface(CONST_INTER); |
|
4221 %} |
|
4222 |
|
4223 // Operand to avoid match of loadConP. |
|
4224 // This operand can be used to avoid matching of an instruct |
|
4225 // with chain rule. |
|
4226 operand immP_NM() %{ |
|
4227 match(ConP); |
|
4228 predicate(false); |
|
4229 op_cost(0); |
|
4230 format %{ %} |
|
4231 interface(CONST_INTER); |
|
4232 %} |
|
4233 |
|
4234 // costant 'pointer 0'. |
|
4235 operand immP_0() %{ |
|
4236 predicate(n->get_ptr() == 0); |
|
4237 match(ConP); |
|
4238 op_cost(0); |
|
4239 format %{ %} |
|
4240 interface(CONST_INTER); |
|
4241 %} |
|
4242 |
|
4243 // pointer 0x0 or 0x1 |
|
4244 operand immP_0or1() %{ |
|
4245 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); |
|
4246 match(ConP); |
|
4247 op_cost(0); |
|
4248 format %{ %} |
|
4249 interface(CONST_INTER); |
|
4250 %} |
|
4251 |
|
4252 operand immL() %{ |
|
4253 match(ConL); |
|
4254 op_cost(40); |
|
4255 format %{ %} |
|
4256 interface(CONST_INTER); |
|
4257 %} |
|
4258 |
|
4259 // Long Immediate: 16-bit |
|
4260 operand immL16() %{ |
|
4261 predicate(Assembler::is_simm(n->get_long(), 16)); |
|
4262 match(ConL); |
|
4263 op_cost(0); |
|
4264 format %{ %} |
|
4265 interface(CONST_INTER); |
|
4266 %} |
|
4267 |
|
4268 // Long Immediate: 16-bit, 4-aligned |
|
4269 operand immL16Alg4() %{ |
|
4270 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); |
|
4271 match(ConL); |
|
4272 op_cost(0); |
|
4273 format %{ %} |
|
4274 interface(CONST_INTER); |
|
4275 %} |
|
4276 |
|
4277 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. |
|
4278 operand immL32hi16() %{ |
|
4279 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); |
|
4280 match(ConL); |
|
4281 op_cost(0); |
|
4282 format %{ %} |
|
4283 interface(CONST_INTER); |
|
4284 %} |
|
4285 |
|
4286 // Long Immediate: 32-bit |
|
4287 operand immL32() %{ |
|
4288 predicate(Assembler::is_simm(n->get_long(), 32)); |
|
4289 match(ConL); |
|
4290 op_cost(0); |
|
4291 format %{ %} |
|
4292 interface(CONST_INTER); |
|
4293 %} |
|
4294 |
|
4295 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. |
|
4296 operand immLhighest16() %{ |
|
4297 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); |
|
4298 match(ConL); |
|
4299 op_cost(0); |
|
4300 format %{ %} |
|
4301 interface(CONST_INTER); |
|
4302 %} |
|
4303 |
|
4304 operand immLnegpow2() %{ |
|
4305 predicate(is_power_of_2_long((jlong)-(n->get_long()))); |
|
4306 match(ConL); |
|
4307 op_cost(0); |
|
4308 format %{ %} |
|
4309 interface(CONST_INTER); |
|
4310 %} |
|
4311 |
|
4312 operand immLpow2minus1() %{ |
|
4313 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && |
|
4314 (n->get_long() != (jlong)0xffffffffffffffffL)); |
|
4315 match(ConL); |
|
4316 op_cost(0); |
|
4317 format %{ %} |
|
4318 interface(CONST_INTER); |
|
4319 %} |
|
4320 |
|
4321 // constant 'long 0'. |
|
4322 operand immL_0() %{ |
|
4323 predicate(n->get_long() == 0L); |
|
4324 match(ConL); |
|
4325 op_cost(0); |
|
4326 format %{ %} |
|
4327 interface(CONST_INTER); |
|
4328 %} |
|
4329 |
|
4330 // constat ' long -1'. |
|
4331 operand immL_minus1() %{ |
|
4332 predicate(n->get_long() == -1L); |
|
4333 match(ConL); |
|
4334 op_cost(0); |
|
4335 format %{ %} |
|
4336 interface(CONST_INTER); |
|
4337 %} |
|
4338 |
|
4339 // Long Immediate: low 32-bit mask |
|
4340 operand immL_32bits() %{ |
|
4341 predicate(n->get_long() == 0xFFFFFFFFL); |
|
4342 match(ConL); |
|
4343 op_cost(0); |
|
4344 format %{ %} |
|
4345 interface(CONST_INTER); |
|
4346 %} |
|
4347 |
|
4348 // Unsigned Long Immediate: 16-bit |
|
4349 operand uimmL16() %{ |
|
4350 predicate(Assembler::is_uimm(n->get_long(), 16)); |
|
4351 match(ConL); |
|
4352 op_cost(0); |
|
4353 format %{ %} |
|
4354 interface(CONST_INTER); |
|
4355 %} |
|
4356 |
|
4357 // Float Immediate |
|
4358 operand immF() %{ |
|
4359 match(ConF); |
|
4360 op_cost(40); |
|
4361 format %{ %} |
|
4362 interface(CONST_INTER); |
|
4363 %} |
|
4364 |
|
4365 // constant 'float +0.0'. |
|
4366 operand immF_0() %{ |
|
4367 predicate((n->getf() == 0) && |
|
4368 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0)); |
|
4369 match(ConF); |
|
4370 op_cost(0); |
|
4371 format %{ %} |
|
4372 interface(CONST_INTER); |
|
4373 %} |
|
4374 |
|
4375 // Double Immediate |
|
4376 operand immD() %{ |
|
4377 match(ConD); |
|
4378 op_cost(40); |
|
4379 format %{ %} |
|
4380 interface(CONST_INTER); |
|
4381 %} |
|
4382 |
|
4383 // Integer Register Operands |
|
4384 // Integer Destination Register |
|
4385 // See definition of reg_class bits32_reg_rw. |
|
4386 operand iRegIdst() %{ |
|
4387 constraint(ALLOC_IN_RC(bits32_reg_rw)); |
|
4388 match(RegI); |
|
4389 match(rscratch1RegI); |
|
4390 match(rscratch2RegI); |
|
4391 match(rarg1RegI); |
|
4392 match(rarg2RegI); |
|
4393 match(rarg3RegI); |
|
4394 match(rarg4RegI); |
|
4395 format %{ %} |
|
4396 interface(REG_INTER); |
|
4397 %} |
|
4398 |
|
4399 // Integer Source Register |
|
4400 // See definition of reg_class bits32_reg_ro. |
|
4401 operand iRegIsrc() %{ |
|
4402 constraint(ALLOC_IN_RC(bits32_reg_ro)); |
|
4403 match(RegI); |
|
4404 match(rscratch1RegI); |
|
4405 match(rscratch2RegI); |
|
4406 match(rarg1RegI); |
|
4407 match(rarg2RegI); |
|
4408 match(rarg3RegI); |
|
4409 match(rarg4RegI); |
|
4410 format %{ %} |
|
4411 interface(REG_INTER); |
|
4412 %} |
|
4413 |
|
4414 operand rscratch1RegI() %{ |
|
4415 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); |
|
4416 match(iRegIdst); |
|
4417 format %{ %} |
|
4418 interface(REG_INTER); |
|
4419 %} |
|
4420 |
|
4421 operand rscratch2RegI() %{ |
|
4422 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); |
|
4423 match(iRegIdst); |
|
4424 format %{ %} |
|
4425 interface(REG_INTER); |
|
4426 %} |
|
4427 |
|
4428 operand rarg1RegI() %{ |
|
4429 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); |
|
4430 match(iRegIdst); |
|
4431 format %{ %} |
|
4432 interface(REG_INTER); |
|
4433 %} |
|
4434 |
|
4435 operand rarg2RegI() %{ |
|
4436 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); |
|
4437 match(iRegIdst); |
|
4438 format %{ %} |
|
4439 interface(REG_INTER); |
|
4440 %} |
|
4441 |
|
4442 operand rarg3RegI() %{ |
|
4443 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); |
|
4444 match(iRegIdst); |
|
4445 format %{ %} |
|
4446 interface(REG_INTER); |
|
4447 %} |
|
4448 |
|
4449 operand rarg4RegI() %{ |
|
4450 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); |
|
4451 match(iRegIdst); |
|
4452 format %{ %} |
|
4453 interface(REG_INTER); |
|
4454 %} |
|
4455 |
|
4456 operand rarg1RegL() %{ |
|
4457 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); |
|
4458 match(iRegLdst); |
|
4459 format %{ %} |
|
4460 interface(REG_INTER); |
|
4461 %} |
|
4462 |
|
4463 operand rarg2RegL() %{ |
|
4464 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); |
|
4465 match(iRegLdst); |
|
4466 format %{ %} |
|
4467 interface(REG_INTER); |
|
4468 %} |
|
4469 |
|
4470 operand rarg3RegL() %{ |
|
4471 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); |
|
4472 match(iRegLdst); |
|
4473 format %{ %} |
|
4474 interface(REG_INTER); |
|
4475 %} |
|
4476 |
|
4477 operand rarg4RegL() %{ |
|
4478 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); |
|
4479 match(iRegLdst); |
|
4480 format %{ %} |
|
4481 interface(REG_INTER); |
|
4482 %} |
|
4483 |
|
4484 // Pointer Destination Register |
|
4485 // See definition of reg_class bits64_reg_rw. |
|
4486 operand iRegPdst() %{ |
|
4487 constraint(ALLOC_IN_RC(bits64_reg_rw)); |
|
4488 match(RegP); |
|
4489 match(rscratch1RegP); |
|
4490 match(rscratch2RegP); |
|
4491 match(rarg1RegP); |
|
4492 match(rarg2RegP); |
|
4493 match(rarg3RegP); |
|
4494 match(rarg4RegP); |
|
4495 format %{ %} |
|
4496 interface(REG_INTER); |
|
4497 %} |
|
4498 |
|
4499 // Pointer Destination Register |
|
4500 // Operand not using r11 and r12 (killed in epilog). |
|
4501 operand iRegPdstNoScratch() %{ |
|
4502 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); |
|
4503 match(RegP); |
|
4504 match(rarg1RegP); |
|
4505 match(rarg2RegP); |
|
4506 match(rarg3RegP); |
|
4507 match(rarg4RegP); |
|
4508 format %{ %} |
|
4509 interface(REG_INTER); |
|
4510 %} |
|
4511 |
|
4512 // Pointer Source Register |
|
4513 // See definition of reg_class bits64_reg_ro. |
|
4514 operand iRegPsrc() %{ |
|
4515 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4516 match(RegP); |
|
4517 match(iRegPdst); |
|
4518 match(rscratch1RegP); |
|
4519 match(rscratch2RegP); |
|
4520 match(rarg1RegP); |
|
4521 match(rarg2RegP); |
|
4522 match(rarg3RegP); |
|
4523 match(rarg4RegP); |
|
4524 match(threadRegP); |
|
4525 format %{ %} |
|
4526 interface(REG_INTER); |
|
4527 %} |
|
4528 |
|
4529 // Thread operand. |
|
4530 operand threadRegP() %{ |
|
4531 constraint(ALLOC_IN_RC(thread_bits64_reg)); |
|
4532 match(iRegPdst); |
|
4533 format %{ "R16" %} |
|
4534 interface(REG_INTER); |
|
4535 %} |
|
4536 |
|
4537 operand rscratch1RegP() %{ |
|
4538 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); |
|
4539 match(iRegPdst); |
|
4540 format %{ "R11" %} |
|
4541 interface(REG_INTER); |
|
4542 %} |
|
4543 |
|
4544 operand rscratch2RegP() %{ |
|
4545 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); |
|
4546 match(iRegPdst); |
|
4547 format %{ %} |
|
4548 interface(REG_INTER); |
|
4549 %} |
|
4550 |
|
4551 operand rarg1RegP() %{ |
|
4552 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); |
|
4553 match(iRegPdst); |
|
4554 format %{ %} |
|
4555 interface(REG_INTER); |
|
4556 %} |
|
4557 |
|
4558 operand rarg2RegP() %{ |
|
4559 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); |
|
4560 match(iRegPdst); |
|
4561 format %{ %} |
|
4562 interface(REG_INTER); |
|
4563 %} |
|
4564 |
|
4565 operand rarg3RegP() %{ |
|
4566 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); |
|
4567 match(iRegPdst); |
|
4568 format %{ %} |
|
4569 interface(REG_INTER); |
|
4570 %} |
|
4571 |
|
4572 operand rarg4RegP() %{ |
|
4573 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); |
|
4574 match(iRegPdst); |
|
4575 format %{ %} |
|
4576 interface(REG_INTER); |
|
4577 %} |
|
4578 |
|
4579 operand iRegNsrc() %{ |
|
4580 constraint(ALLOC_IN_RC(bits32_reg_ro)); |
|
4581 match(RegN); |
|
4582 match(iRegNdst); |
|
4583 |
|
4584 format %{ %} |
|
4585 interface(REG_INTER); |
|
4586 %} |
|
4587 |
|
4588 operand iRegNdst() %{ |
|
4589 constraint(ALLOC_IN_RC(bits32_reg_rw)); |
|
4590 match(RegN); |
|
4591 |
|
4592 format %{ %} |
|
4593 interface(REG_INTER); |
|
4594 %} |
|
4595 |
|
4596 // Long Destination Register |
|
4597 // See definition of reg_class bits64_reg_rw. |
|
4598 operand iRegLdst() %{ |
|
4599 constraint(ALLOC_IN_RC(bits64_reg_rw)); |
|
4600 match(RegL); |
|
4601 match(rscratch1RegL); |
|
4602 match(rscratch2RegL); |
|
4603 format %{ %} |
|
4604 interface(REG_INTER); |
|
4605 %} |
|
4606 |
|
4607 // Long Source Register |
|
4608 // See definition of reg_class bits64_reg_ro. |
|
4609 operand iRegLsrc() %{ |
|
4610 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4611 match(RegL); |
|
4612 match(iRegLdst); |
|
4613 match(rscratch1RegL); |
|
4614 match(rscratch2RegL); |
|
4615 format %{ %} |
|
4616 interface(REG_INTER); |
|
4617 %} |
|
4618 |
|
4619 // Special operand for ConvL2I. |
|
4620 operand iRegL2Isrc(iRegLsrc reg) %{ |
|
4621 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4622 match(ConvL2I reg); |
|
4623 format %{ "ConvL2I($reg)" %} |
|
4624 interface(REG_INTER) |
|
4625 %} |
|
4626 |
|
4627 operand rscratch1RegL() %{ |
|
4628 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); |
|
4629 match(RegL); |
|
4630 format %{ %} |
|
4631 interface(REG_INTER); |
|
4632 %} |
|
4633 |
|
4634 operand rscratch2RegL() %{ |
|
4635 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); |
|
4636 match(RegL); |
|
4637 format %{ %} |
|
4638 interface(REG_INTER); |
|
4639 %} |
|
4640 |
|
4641 // Condition Code Flag Registers |
|
4642 operand flagsReg() %{ |
|
4643 constraint(ALLOC_IN_RC(int_flags)); |
|
4644 match(RegFlags); |
|
4645 format %{ %} |
|
4646 interface(REG_INTER); |
|
4647 %} |
|
4648 |
|
4649 // Condition Code Flag Register CR0 |
|
4650 operand flagsRegCR0() %{ |
|
4651 constraint(ALLOC_IN_RC(int_flags_CR0)); |
|
4652 match(RegFlags); |
|
4653 format %{ "CR0" %} |
|
4654 interface(REG_INTER); |
|
4655 %} |
|
4656 |
|
4657 operand flagsRegCR1() %{ |
|
4658 constraint(ALLOC_IN_RC(int_flags_CR1)); |
|
4659 match(RegFlags); |
|
4660 format %{ "CR1" %} |
|
4661 interface(REG_INTER); |
|
4662 %} |
|
4663 |
|
4664 operand flagsRegCR6() %{ |
|
4665 constraint(ALLOC_IN_RC(int_flags_CR6)); |
|
4666 match(RegFlags); |
|
4667 format %{ "CR6" %} |
|
4668 interface(REG_INTER); |
|
4669 %} |
|
4670 |
|
4671 operand regCTR() %{ |
|
4672 constraint(ALLOC_IN_RC(ctr_reg)); |
|
4673 // RegFlags should work. Introducing a RegSpecial type would cause a |
|
4674 // lot of changes. |
|
4675 match(RegFlags); |
|
4676 format %{"SR_CTR" %} |
|
4677 interface(REG_INTER); |
|
4678 %} |
|
4679 |
|
4680 operand regD() %{ |
|
4681 constraint(ALLOC_IN_RC(dbl_reg)); |
|
4682 match(RegD); |
|
4683 format %{ %} |
|
4684 interface(REG_INTER); |
|
4685 %} |
|
4686 |
|
4687 operand regF() %{ |
|
4688 constraint(ALLOC_IN_RC(flt_reg)); |
|
4689 match(RegF); |
|
4690 format %{ %} |
|
4691 interface(REG_INTER); |
|
4692 %} |
|
4693 |
|
4694 // Special Registers |
|
4695 |
|
4696 // Method Register |
|
4697 operand inline_cache_regP(iRegPdst reg) %{ |
|
4698 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg |
|
4699 match(reg); |
|
4700 format %{ %} |
|
4701 interface(REG_INTER); |
|
4702 %} |
|
4703 |
|
4704 operand compiler_method_oop_regP(iRegPdst reg) %{ |
|
4705 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg |
|
4706 match(reg); |
|
4707 format %{ %} |
|
4708 interface(REG_INTER); |
|
4709 %} |
|
4710 |
|
4711 operand interpreter_method_oop_regP(iRegPdst reg) %{ |
|
4712 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg |
|
4713 match(reg); |
|
4714 format %{ %} |
|
4715 interface(REG_INTER); |
|
4716 %} |
|
4717 |
|
4718 // Operands to remove register moves in unscaled mode. |
|
4719 // Match read/write registers with an EncodeP node if neither shift nor add are required. |
|
4720 operand iRegP2N(iRegPsrc reg) %{ |
|
4721 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); |
|
4722 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4723 match(EncodeP reg); |
|
4724 format %{ "$reg" %} |
|
4725 interface(REG_INTER) |
|
4726 %} |
|
4727 |
|
4728 operand iRegN2P(iRegNsrc reg) %{ |
|
4729 predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4730 constraint(ALLOC_IN_RC(bits32_reg_ro)); |
|
4731 match(DecodeN reg); |
|
4732 match(DecodeNKlass reg); |
|
4733 format %{ "$reg" %} |
|
4734 interface(REG_INTER) |
|
4735 %} |
|
4736 |
|
4737 //----------Complex Operands--------------------------------------------------- |
|
4738 // Indirect Memory Reference |
|
4739 operand indirect(iRegPsrc reg) %{ |
|
4740 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4741 match(reg); |
|
4742 op_cost(100); |
|
4743 format %{ "[$reg]" %} |
|
4744 interface(MEMORY_INTER) %{ |
|
4745 base($reg); |
|
4746 index(0x0); |
|
4747 scale(0x0); |
|
4748 disp(0x0); |
|
4749 %} |
|
4750 %} |
|
4751 |
|
4752 // Indirect with Offset |
|
4753 operand indOffset16(iRegPsrc reg, immL16 offset) %{ |
|
4754 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4755 match(AddP reg offset); |
|
4756 op_cost(100); |
|
4757 format %{ "[$reg + $offset]" %} |
|
4758 interface(MEMORY_INTER) %{ |
|
4759 base($reg); |
|
4760 index(0x0); |
|
4761 scale(0x0); |
|
4762 disp($offset); |
|
4763 %} |
|
4764 %} |
|
4765 |
|
4766 // Indirect with 4-aligned Offset |
|
4767 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ |
|
4768 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4769 match(AddP reg offset); |
|
4770 op_cost(100); |
|
4771 format %{ "[$reg + $offset]" %} |
|
4772 interface(MEMORY_INTER) %{ |
|
4773 base($reg); |
|
4774 index(0x0); |
|
4775 scale(0x0); |
|
4776 disp($offset); |
|
4777 %} |
|
4778 %} |
|
4779 |
|
4780 //----------Complex Operands for Compressed OOPs------------------------------- |
|
4781 // Compressed OOPs with narrow_oop_shift == 0. |
|
4782 |
|
4783 // Indirect Memory Reference, compressed OOP |
|
4784 operand indirectNarrow(iRegNsrc reg) %{ |
|
4785 predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4786 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4787 match(DecodeN reg); |
|
4788 match(DecodeNKlass reg); |
|
4789 op_cost(100); |
|
4790 format %{ "[$reg]" %} |
|
4791 interface(MEMORY_INTER) %{ |
|
4792 base($reg); |
|
4793 index(0x0); |
|
4794 scale(0x0); |
|
4795 disp(0x0); |
|
4796 %} |
|
4797 %} |
|
4798 |
|
4799 // Indirect with Offset, compressed OOP |
|
4800 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ |
|
4801 predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4802 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4803 match(AddP (DecodeN reg) offset); |
|
4804 match(AddP (DecodeNKlass reg) offset); |
|
4805 op_cost(100); |
|
4806 format %{ "[$reg + $offset]" %} |
|
4807 interface(MEMORY_INTER) %{ |
|
4808 base($reg); |
|
4809 index(0x0); |
|
4810 scale(0x0); |
|
4811 disp($offset); |
|
4812 %} |
|
4813 %} |
|
4814 |
|
4815 // Indirect with 4-aligned Offset, compressed OOP |
|
4816 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ |
|
4817 predicate(false /* TODO: PPC port MatchDecodeNodes*/); |
|
4818 constraint(ALLOC_IN_RC(bits64_reg_ro)); |
|
4819 match(AddP (DecodeN reg) offset); |
|
4820 match(AddP (DecodeNKlass reg) offset); |
|
4821 op_cost(100); |
|
4822 format %{ "[$reg + $offset]" %} |
|
4823 interface(MEMORY_INTER) %{ |
|
4824 base($reg); |
|
4825 index(0x0); |
|
4826 scale(0x0); |
|
4827 disp($offset); |
|
4828 %} |
|
4829 %} |
|
4830 |
|
4831 //----------Special Memory Operands-------------------------------------------- |
|
4832 // Stack Slot Operand |
|
4833 // |
|
4834 // This operand is used for loading and storing temporary values on |
|
4835 // the stack where a match requires a value to flow through memory. |
|
4836 operand stackSlotI(sRegI reg) %{ |
|
4837 constraint(ALLOC_IN_RC(stack_slots)); |
|
4838 op_cost(100); |
|
4839 //match(RegI); |
|
4840 format %{ "[sp+$reg]" %} |
|
4841 interface(MEMORY_INTER) %{ |
|
4842 base(0x1); // R1_SP |
|
4843 index(0x0); |
|
4844 scale(0x0); |
|
4845 disp($reg); // Stack Offset |
|
4846 %} |
|
4847 %} |
|
4848 |
|
4849 operand stackSlotL(sRegL reg) %{ |
|
4850 constraint(ALLOC_IN_RC(stack_slots)); |
|
4851 op_cost(100); |
|
4852 //match(RegL); |
|
4853 format %{ "[sp+$reg]" %} |
|
4854 interface(MEMORY_INTER) %{ |
|
4855 base(0x1); // R1_SP |
|
4856 index(0x0); |
|
4857 scale(0x0); |
|
4858 disp($reg); // Stack Offset |
|
4859 %} |
|
4860 %} |
|
4861 |
|
4862 operand stackSlotP(sRegP reg) %{ |
|
4863 constraint(ALLOC_IN_RC(stack_slots)); |
|
4864 op_cost(100); |
|
4865 //match(RegP); |
|
4866 format %{ "[sp+$reg]" %} |
|
4867 interface(MEMORY_INTER) %{ |
|
4868 base(0x1); // R1_SP |
|
4869 index(0x0); |
|
4870 scale(0x0); |
|
4871 disp($reg); // Stack Offset |
|
4872 %} |
|
4873 %} |
|
4874 |
|
4875 operand stackSlotF(sRegF reg) %{ |
|
4876 constraint(ALLOC_IN_RC(stack_slots)); |
|
4877 op_cost(100); |
|
4878 //match(RegF); |
|
4879 format %{ "[sp+$reg]" %} |
|
4880 interface(MEMORY_INTER) %{ |
|
4881 base(0x1); // R1_SP |
|
4882 index(0x0); |
|
4883 scale(0x0); |
|
4884 disp($reg); // Stack Offset |
|
4885 %} |
|
4886 %} |
|
4887 |
|
4888 operand stackSlotD(sRegD reg) %{ |
|
4889 constraint(ALLOC_IN_RC(stack_slots)); |
|
4890 op_cost(100); |
|
4891 //match(RegD); |
|
4892 format %{ "[sp+$reg]" %} |
|
4893 interface(MEMORY_INTER) %{ |
|
4894 base(0x1); // R1_SP |
|
4895 index(0x0); |
|
4896 scale(0x0); |
|
4897 disp($reg); // Stack Offset |
|
4898 %} |
|
4899 %} |
|
4900 |
|
4901 // Operands for expressing Control Flow |
|
4902 // NOTE: Label is a predefined operand which should not be redefined in |
|
4903 // the AD file. It is generically handled within the ADLC. |
|
4904 |
|
4905 //----------Conditional Branch Operands---------------------------------------- |
|
4906 // Comparison Op |
|
4907 // |
|
4908 // This is the operation of the comparison, and is limited to the |
|
4909 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE |
|
4910 // (!=). |
|
4911 // |
|
4912 // Other attributes of the comparison, such as unsignedness, are specified |
|
4913 // by the comparison instruction that sets a condition code flags register. |
|
4914 // That result is represented by a flags operand whose subtype is appropriate |
|
4915 // to the unsignedness (etc.) of the comparison. |
|
4916 // |
|
4917 // Later, the instruction which matches both the Comparison Op (a Bool) and |
|
4918 // the flags (produced by the Cmp) specifies the coding of the comparison op |
|
4919 // by matching a specific subtype of Bool operand below. |
|
4920 |
|
4921 // When used for floating point comparisons: unordered same as less. |
|
4922 operand cmpOp() %{ |
|
4923 match(Bool); |
|
4924 format %{ "" %} |
|
4925 interface(COND_INTER) %{ |
|
4926 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. |
|
4927 // BO & BI |
|
4928 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal |
|
4929 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal |
|
4930 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less |
|
4931 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less |
|
4932 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater |
|
4933 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater |
|
4934 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow |
|
4935 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow |
|
4936 %} |
|
4937 %} |
|
4938 |
|
4939 //----------OPERAND CLASSES---------------------------------------------------- |
|
4940 // Operand Classes are groups of operands that are used to simplify |
|
4941 // instruction definitions by not requiring the AD writer to specify |
|
4942 // seperate instructions for every form of operand when the |
|
4943 // instruction accepts multiple operand types with the same basic |
|
4944 // encoding and format. The classic case of this is memory operands. |
|
4945 // Indirect is not included since its use is limited to Compare & Swap. |
|
4946 |
|
4947 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow); |
|
4948 // Memory operand where offsets are 4-aligned. Required for ld, std. |
|
4949 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4); |
|
4950 opclass indirectMemory(indirect, indirectNarrow); |
|
4951 |
|
4952 // Special opclass for I and ConvL2I. |
|
4953 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); |
|
4954 |
|
4955 // Operand classes to match encode and decode. iRegN_P2N is only used |
|
4956 // for storeN. I have never seen an encode node elsewhere. |
|
4957 opclass iRegN_P2N(iRegNsrc, iRegP2N); |
|
4958 opclass iRegP_N2P(iRegPsrc, iRegN2P); |
|
4959 |
|
4960 //----------PIPELINE----------------------------------------------------------- |
|
4961 |
|
4962 pipeline %{ |
|
4963 |
|
4964 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM |
|
4965 // J. Res. & Dev., No. 1, Jan. 2002. |
|
4966 |
|
4967 //----------ATTRIBUTES--------------------------------------------------------- |
|
4968 attributes %{ |
|
4969 |
|
4970 // Power4 instructions are of fixed length. |
|
4971 fixed_size_instructions; |
|
4972 |
|
4973 // TODO: if `bundle' means number of instructions fetched |
|
4974 // per cycle, this is 8. If `bundle' means Power4 `group', that is |
|
4975 // max instructions issued per cycle, this is 5. |
|
4976 max_instructions_per_bundle = 8; |
|
4977 |
|
4978 // A Power4 instruction is 4 bytes long. |
|
4979 instruction_unit_size = 4; |
|
4980 |
|
4981 // The Power4 processor fetches 64 bytes... |
|
4982 instruction_fetch_unit_size = 64; |
|
4983 |
|
4984 // ...in one line |
|
4985 instruction_fetch_units = 1 |
|
4986 |
|
4987 // Unused, list one so that array generated by adlc is not empty. |
|
4988 // Aix compiler chokes if _nop_count = 0. |
|
4989 nops(fxNop); |
|
4990 %} |
|
4991 |
|
4992 //----------RESOURCES---------------------------------------------------------- |
|
4993 // Resources are the functional units available to the machine |
|
4994 resources( |
|
4995 PPC_BR, // branch unit |
|
4996 PPC_CR, // condition unit |
|
4997 PPC_FX1, // integer arithmetic unit 1 |
|
4998 PPC_FX2, // integer arithmetic unit 2 |
|
4999 PPC_LDST1, // load/store unit 1 |
|
5000 PPC_LDST2, // load/store unit 2 |
|
5001 PPC_FP1, // float arithmetic unit 1 |
|
5002 PPC_FP2, // float arithmetic unit 2 |
|
5003 PPC_LDST = PPC_LDST1 | PPC_LDST2, |
|
5004 PPC_FX = PPC_FX1 | PPC_FX2, |
|
5005 PPC_FP = PPC_FP1 | PPC_FP2 |
|
5006 ); |
|
5007 |
|
5008 //----------PIPELINE DESCRIPTION----------------------------------------------- |
|
5009 // Pipeline Description specifies the stages in the machine's pipeline |
|
5010 pipe_desc( |
|
5011 // Power4 longest pipeline path |
|
5012 PPC_IF, // instruction fetch |
|
5013 PPC_IC, |
|
5014 //PPC_BP, // branch prediction |
|
5015 PPC_D0, // decode |
|
5016 PPC_D1, // decode |
|
5017 PPC_D2, // decode |
|
5018 PPC_D3, // decode |
|
5019 PPC_Xfer1, |
|
5020 PPC_GD, // group definition |
|
5021 PPC_MP, // map |
|
5022 PPC_ISS, // issue |
|
5023 PPC_RF, // resource fetch |
|
5024 PPC_EX1, // execute (all units) |
|
5025 PPC_EX2, // execute (FP, LDST) |
|
5026 PPC_EX3, // execute (FP, LDST) |
|
5027 PPC_EX4, // execute (FP) |
|
5028 PPC_EX5, // execute (FP) |
|
5029 PPC_EX6, // execute (FP) |
|
5030 PPC_WB, // write back |
|
5031 PPC_Xfer2, |
|
5032 PPC_CP |
|
5033 ); |
|
5034 |
|
5035 //----------PIPELINE CLASSES--------------------------------------------------- |
|
5036 // Pipeline Classes describe the stages in which input and output are |
|
5037 // referenced by the hardware pipeline. |
|
5038 |
|
5039 // Simple pipeline classes. |
|
5040 |
|
5041 // Default pipeline class. |
|
5042 pipe_class pipe_class_default() %{ |
|
5043 single_instruction; |
|
5044 fixed_latency(2); |
|
5045 %} |
|
5046 |
|
5047 // Pipeline class for empty instructions. |
|
5048 pipe_class pipe_class_empty() %{ |
|
5049 single_instruction; |
|
5050 fixed_latency(0); |
|
5051 %} |
|
5052 |
|
5053 // Pipeline class for compares. |
|
5054 pipe_class pipe_class_compare() %{ |
|
5055 single_instruction; |
|
5056 fixed_latency(16); |
|
5057 %} |
|
5058 |
|
5059 // Pipeline class for traps. |
|
5060 pipe_class pipe_class_trap() %{ |
|
5061 single_instruction; |
|
5062 fixed_latency(100); |
|
5063 %} |
|
5064 |
|
5065 // Pipeline class for memory operations. |
|
5066 pipe_class pipe_class_memory() %{ |
|
5067 single_instruction; |
|
5068 fixed_latency(16); |
|
5069 %} |
|
5070 |
|
5071 // Pipeline class for call. |
|
5072 pipe_class pipe_class_call() %{ |
|
5073 single_instruction; |
|
5074 fixed_latency(100); |
|
5075 %} |
|
5076 |
|
5077 // Define the class for the Nop node. |
|
5078 define %{ |
|
5079 MachNop = pipe_class_default; |
|
5080 %} |
|
5081 |
|
5082 %} |
|
5083 |
|
5084 //----------INSTRUCTIONS------------------------------------------------------- |
|
5085 |
|
5086 // Naming of instructions: |
|
5087 // opA_operB / opA_operB_operC: |
|
5088 // Operation 'op' with one or two source operands 'oper'. Result |
|
5089 // type is A, source operand types are B and C. |
|
5090 // Iff A == B == C, B and C are left out. |
|
5091 // |
|
5092 // The instructions are ordered according to the following scheme: |
|
5093 // - loads |
|
5094 // - load constants |
|
5095 // - prefetch |
|
5096 // - store |
|
5097 // - encode/decode |
|
5098 // - membar |
|
5099 // - conditional moves |
|
5100 // - compare & swap |
|
5101 // - arithmetic and logic operations |
|
5102 // * int: Add, Sub, Mul, Div, Mod |
|
5103 // * int: lShift, arShift, urShift, rot |
|
5104 // * float: Add, Sub, Mul, Div |
|
5105 // * and, or, xor ... |
|
5106 // - register moves: float <-> int, reg <-> stack, repl |
|
5107 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. |
|
5108 // - conv (low level type cast requiring bit changes (sign extend etc) |
|
5109 // - compares, range & zero checks. |
|
5110 // - branches |
|
5111 // - complex operations, intrinsics, min, max, replicate |
|
5112 // - lock |
|
5113 // - Calls |
|
5114 // |
|
5115 // If there are similar instructions with different types they are sorted: |
|
5116 // int before float |
|
5117 // small before big |
|
5118 // signed before unsigned |
|
5119 // e.g., loadS before loadUS before loadI before loadF. |
|
5120 |
|
5121 |
|
5122 //----------Load/Store Instructions-------------------------------------------- |
|
5123 |
|
5124 //----------Load Instructions-------------------------------------------------- |
|
5125 |
|
5126 // Converts byte to int. |
|
5127 // As convB2I_reg, but without match rule. The match rule of convB2I_reg |
|
5128 // reuses the 'amount' operand, but adlc expects that operand specification |
|
5129 // and operands in match rule are equivalent. |
|
5130 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ |
|
5131 effect(DEF dst, USE src); |
|
5132 format %{ "EXTSB $dst, $src \t// byte->int" %} |
|
5133 size(4); |
|
5134 ins_encode %{ |
|
5135 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); |
|
5136 __ extsb($dst$$Register, $src$$Register); |
|
5137 %} |
|
5138 ins_pipe(pipe_class_default); |
|
5139 %} |
|
5140 |
|
5141 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ |
|
5142 // match-rule, false predicate |
|
5143 match(Set dst (LoadB mem)); |
|
5144 predicate(false); |
|
5145 |
|
5146 format %{ "LBZ $dst, $mem" %} |
|
5147 size(4); |
|
5148 ins_encode( enc_lbz(dst, mem) ); |
|
5149 ins_pipe(pipe_class_memory); |
|
5150 %} |
|
5151 |
|
5152 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ |
|
5153 // match-rule, false predicate |
|
5154 match(Set dst (LoadB mem)); |
|
5155 predicate(false); |
|
5156 |
|
5157 format %{ "LBZ $dst, $mem\n\t" |
|
5158 "TWI $dst\n\t" |
|
5159 "ISYNC" %} |
|
5160 size(12); |
|
5161 ins_encode( enc_lbz_ac(dst, mem) ); |
|
5162 ins_pipe(pipe_class_memory); |
|
5163 %} |
|
5164 |
|
5165 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. |
|
5166 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ |
|
5167 match(Set dst (LoadB mem)); |
|
5168 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5169 ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5170 expand %{ |
|
5171 iRegIdst tmp; |
|
5172 loadUB_indirect(tmp, mem); |
|
5173 convB2I_reg_2(dst, tmp); |
|
5174 %} |
|
5175 %} |
|
5176 |
|
5177 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ |
|
5178 match(Set dst (LoadB mem)); |
|
5179 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); |
|
5180 expand %{ |
|
5181 iRegIdst tmp; |
|
5182 loadUB_indirect_ac(tmp, mem); |
|
5183 convB2I_reg_2(dst, tmp); |
|
5184 %} |
|
5185 %} |
|
5186 |
|
5187 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ |
|
5188 // match-rule, false predicate |
|
5189 match(Set dst (LoadB mem)); |
|
5190 predicate(false); |
|
5191 |
|
5192 format %{ "LBZ $dst, $mem" %} |
|
5193 size(4); |
|
5194 ins_encode( enc_lbz(dst, mem) ); |
|
5195 ins_pipe(pipe_class_memory); |
|
5196 %} |
|
5197 |
|
5198 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ |
|
5199 // match-rule, false predicate |
|
5200 match(Set dst (LoadB mem)); |
|
5201 predicate(false); |
|
5202 |
|
5203 format %{ "LBZ $dst, $mem\n\t" |
|
5204 "TWI $dst\n\t" |
|
5205 "ISYNC" %} |
|
5206 size(12); |
|
5207 ins_encode( enc_lbz_ac(dst, mem) ); |
|
5208 ins_pipe(pipe_class_memory); |
|
5209 %} |
|
5210 |
|
5211 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. |
|
5212 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ |
|
5213 match(Set dst (LoadB mem)); |
|
5214 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5215 ins_cost(MEMORY_REF_COST + DEFAULT_COST); |
|
5216 |
|
5217 expand %{ |
|
5218 iRegIdst tmp; |
|
5219 loadUB_indOffset16(tmp, mem); |
|
5220 convB2I_reg_2(dst, tmp); |
|
5221 %} |
|
5222 %} |
|
5223 |
|
5224 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ |
|
5225 match(Set dst (LoadB mem)); |
|
5226 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); |
|
5227 |
|
5228 expand %{ |
|
5229 iRegIdst tmp; |
|
5230 loadUB_indOffset16_ac(tmp, mem); |
|
5231 convB2I_reg_2(dst, tmp); |
|
5232 %} |
|
5233 %} |
|
5234 |
|
5235 // Load Unsigned Byte (8bit UNsigned) into an int reg. |
|
5236 instruct loadUB(iRegIdst dst, memory mem) %{ |
|
5237 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5238 match(Set dst (LoadUB mem)); |
|
5239 ins_cost(MEMORY_REF_COST); |
|
5240 |
|
5241 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} |
|
5242 size(4); |
|
5243 ins_encode( enc_lbz(dst, mem) ); |
|
5244 ins_pipe(pipe_class_memory); |
|
5245 %} |
|
5246 |
|
5247 // Load Unsigned Byte (8bit UNsigned) acquire. |
|
5248 instruct loadUB_ac(iRegIdst dst, memory mem) %{ |
|
5249 match(Set dst (LoadUB mem)); |
|
5250 ins_cost(3*MEMORY_REF_COST); |
|
5251 |
|
5252 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" |
|
5253 "TWI $dst\n\t" |
|
5254 "ISYNC" %} |
|
5255 size(12); |
|
5256 ins_encode( enc_lbz_ac(dst, mem) ); |
|
5257 ins_pipe(pipe_class_memory); |
|
5258 %} |
|
5259 |
|
5260 // Load Unsigned Byte (8bit UNsigned) into a Long Register. |
|
5261 instruct loadUB2L(iRegLdst dst, memory mem) %{ |
|
5262 match(Set dst (ConvI2L (LoadUB mem))); |
|
5263 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); |
|
5264 ins_cost(MEMORY_REF_COST); |
|
5265 |
|
5266 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} |
|
5267 size(4); |
|
5268 ins_encode( enc_lbz(dst, mem) ); |
|
5269 ins_pipe(pipe_class_memory); |
|
5270 %} |
|
5271 |
|
5272 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ |
|
5273 match(Set dst (ConvI2L (LoadUB mem))); |
|
5274 ins_cost(3*MEMORY_REF_COST); |
|
5275 |
|
5276 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" |
|
5277 "TWI $dst\n\t" |
|
5278 "ISYNC" %} |
|
5279 size(12); |
|
5280 ins_encode( enc_lbz_ac(dst, mem) ); |
|
5281 ins_pipe(pipe_class_memory); |
|
5282 %} |
|
5283 |
|
5284 // Load Short (16bit signed) |
|
5285 instruct loadS(iRegIdst dst, memory mem) %{ |
|
5286 match(Set dst (LoadS mem)); |
|
5287 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5288 ins_cost(MEMORY_REF_COST); |
|
5289 |
|
5290 format %{ "LHA $dst, $mem" %} |
|
5291 size(4); |
|
5292 ins_encode %{ |
|
5293 // TODO: PPC port $archOpcode(ppc64Opcode_lha); |
|
5294 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5295 __ lha($dst$$Register, Idisp, $mem$$base$$Register); |
|
5296 %} |
|
5297 ins_pipe(pipe_class_memory); |
|
5298 %} |
|
5299 |
|
5300 // Load Short (16bit signed) acquire. |
|
5301 instruct loadS_ac(iRegIdst dst, memory mem) %{ |
|
5302 match(Set dst (LoadS mem)); |
|
5303 ins_cost(3*MEMORY_REF_COST); |
|
5304 |
|
5305 format %{ "LHA $dst, $mem\t acquire\n\t" |
|
5306 "TWI $dst\n\t" |
|
5307 "ISYNC" %} |
|
5308 size(12); |
|
5309 ins_encode %{ |
|
5310 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
5311 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5312 __ lha($dst$$Register, Idisp, $mem$$base$$Register); |
|
5313 __ twi_0($dst$$Register); |
|
5314 __ isync(); |
|
5315 %} |
|
5316 ins_pipe(pipe_class_memory); |
|
5317 %} |
|
5318 |
|
5319 // Load Char (16bit unsigned) |
|
5320 instruct loadUS(iRegIdst dst, memory mem) %{ |
|
5321 match(Set dst (LoadUS mem)); |
|
5322 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5323 ins_cost(MEMORY_REF_COST); |
|
5324 |
|
5325 format %{ "LHZ $dst, $mem" %} |
|
5326 size(4); |
|
5327 ins_encode( enc_lhz(dst, mem) ); |
|
5328 ins_pipe(pipe_class_memory); |
|
5329 %} |
|
5330 |
|
5331 // Load Char (16bit unsigned) acquire. |
|
5332 instruct loadUS_ac(iRegIdst dst, memory mem) %{ |
|
5333 match(Set dst (LoadUS mem)); |
|
5334 ins_cost(3*MEMORY_REF_COST); |
|
5335 |
|
5336 format %{ "LHZ $dst, $mem \t// acquire\n\t" |
|
5337 "TWI $dst\n\t" |
|
5338 "ISYNC" %} |
|
5339 size(12); |
|
5340 ins_encode( enc_lhz_ac(dst, mem) ); |
|
5341 ins_pipe(pipe_class_memory); |
|
5342 %} |
|
5343 |
|
5344 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. |
|
5345 instruct loadUS2L(iRegLdst dst, memory mem) %{ |
|
5346 match(Set dst (ConvI2L (LoadUS mem))); |
|
5347 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); |
|
5348 ins_cost(MEMORY_REF_COST); |
|
5349 |
|
5350 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} |
|
5351 size(4); |
|
5352 ins_encode( enc_lhz(dst, mem) ); |
|
5353 ins_pipe(pipe_class_memory); |
|
5354 %} |
|
5355 |
|
5356 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. |
|
5357 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ |
|
5358 match(Set dst (ConvI2L (LoadUS mem))); |
|
5359 ins_cost(3*MEMORY_REF_COST); |
|
5360 |
|
5361 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" |
|
5362 "TWI $dst\n\t" |
|
5363 "ISYNC" %} |
|
5364 size(12); |
|
5365 ins_encode( enc_lhz_ac(dst, mem) ); |
|
5366 ins_pipe(pipe_class_memory); |
|
5367 %} |
|
5368 |
|
5369 // Load Integer. |
|
5370 instruct loadI(iRegIdst dst, memory mem) %{ |
|
5371 match(Set dst (LoadI mem)); |
|
5372 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5373 ins_cost(MEMORY_REF_COST); |
|
5374 |
|
5375 format %{ "LWZ $dst, $mem" %} |
|
5376 size(4); |
|
5377 ins_encode( enc_lwz(dst, mem) ); |
|
5378 ins_pipe(pipe_class_memory); |
|
5379 %} |
|
5380 |
|
5381 // Load Integer acquire. |
|
5382 instruct loadI_ac(iRegIdst dst, memory mem) %{ |
|
5383 match(Set dst (LoadI mem)); |
|
5384 ins_cost(3*MEMORY_REF_COST); |
|
5385 |
|
5386 format %{ "LWZ $dst, $mem \t// load acquire\n\t" |
|
5387 "TWI $dst\n\t" |
|
5388 "ISYNC" %} |
|
5389 size(12); |
|
5390 ins_encode( enc_lwz_ac(dst, mem) ); |
|
5391 ins_pipe(pipe_class_memory); |
|
5392 %} |
|
5393 |
|
5394 // Match loading integer and casting it to unsigned int in |
|
5395 // long register. |
|
5396 // LoadI + ConvI2L + AndL 0xffffffff. |
|
5397 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ |
|
5398 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); |
|
5399 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); |
|
5400 ins_cost(MEMORY_REF_COST); |
|
5401 |
|
5402 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} |
|
5403 size(4); |
|
5404 ins_encode( enc_lwz(dst, mem) ); |
|
5405 ins_pipe(pipe_class_memory); |
|
5406 %} |
|
5407 |
|
5408 // Match loading integer and casting it to long. |
|
5409 instruct loadI2L(iRegLdst dst, memory mem) %{ |
|
5410 match(Set dst (ConvI2L (LoadI mem))); |
|
5411 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); |
|
5412 ins_cost(MEMORY_REF_COST); |
|
5413 |
|
5414 format %{ "LWA $dst, $mem \t// loadI2L" %} |
|
5415 size(4); |
|
5416 ins_encode %{ |
|
5417 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); |
|
5418 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5419 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); |
|
5420 %} |
|
5421 ins_pipe(pipe_class_memory); |
|
5422 %} |
|
5423 |
|
5424 // Match loading integer and casting it to long - acquire. |
|
5425 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ |
|
5426 match(Set dst (ConvI2L (LoadI mem))); |
|
5427 ins_cost(3*MEMORY_REF_COST); |
|
5428 |
|
5429 format %{ "LWA $dst, $mem \t// loadI2L acquire" |
|
5430 "TWI $dst\n\t" |
|
5431 "ISYNC" %} |
|
5432 size(12); |
|
5433 ins_encode %{ |
|
5434 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); |
|
5435 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5436 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); |
|
5437 __ twi_0($dst$$Register); |
|
5438 __ isync(); |
|
5439 %} |
|
5440 ins_pipe(pipe_class_memory); |
|
5441 %} |
|
5442 |
|
5443 // Load Long - aligned |
|
5444 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ |
|
5445 match(Set dst (LoadL mem)); |
|
5446 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5447 ins_cost(MEMORY_REF_COST); |
|
5448 |
|
5449 format %{ "LD $dst, $mem \t// long" %} |
|
5450 size(4); |
|
5451 ins_encode( enc_ld(dst, mem) ); |
|
5452 ins_pipe(pipe_class_memory); |
|
5453 %} |
|
5454 |
|
5455 // Load Long - aligned acquire. |
|
5456 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ |
|
5457 match(Set dst (LoadL mem)); |
|
5458 ins_cost(3*MEMORY_REF_COST); |
|
5459 |
|
5460 format %{ "LD $dst, $mem \t// long acquire\n\t" |
|
5461 "TWI $dst\n\t" |
|
5462 "ISYNC" %} |
|
5463 size(12); |
|
5464 ins_encode( enc_ld_ac(dst, mem) ); |
|
5465 ins_pipe(pipe_class_memory); |
|
5466 %} |
|
5467 |
|
5468 // Load Long - UNaligned |
|
5469 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ |
|
5470 match(Set dst (LoadL_unaligned mem)); |
|
5471 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). |
|
5472 ins_cost(MEMORY_REF_COST); |
|
5473 |
|
5474 format %{ "LD $dst, $mem \t// unaligned long" %} |
|
5475 size(4); |
|
5476 ins_encode( enc_ld(dst, mem) ); |
|
5477 ins_pipe(pipe_class_memory); |
|
5478 %} |
|
5479 |
|
5480 // Load nodes for superwords |
|
5481 |
|
5482 // Load Aligned Packed Byte |
|
5483 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ |
|
5484 predicate(n->as_LoadVector()->memory_size() == 8); |
|
5485 match(Set dst (LoadVector mem)); |
|
5486 ins_cost(MEMORY_REF_COST); |
|
5487 |
|
5488 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} |
|
5489 size(4); |
|
5490 ins_encode( enc_ld(dst, mem) ); |
|
5491 ins_pipe(pipe_class_memory); |
|
5492 %} |
|
5493 |
|
5494 // Load Range, range = array length (=jint) |
|
5495 instruct loadRange(iRegIdst dst, memory mem) %{ |
|
5496 match(Set dst (LoadRange mem)); |
|
5497 ins_cost(MEMORY_REF_COST); |
|
5498 |
|
5499 format %{ "LWZ $dst, $mem \t// range" %} |
|
5500 size(4); |
|
5501 ins_encode( enc_lwz(dst, mem) ); |
|
5502 ins_pipe(pipe_class_memory); |
|
5503 %} |
|
5504 |
|
5505 // Load Compressed Pointer |
|
5506 instruct loadN(iRegNdst dst, memory mem) %{ |
|
5507 match(Set dst (LoadN mem)); |
|
5508 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5509 ins_cost(MEMORY_REF_COST); |
|
5510 |
|
5511 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} |
|
5512 size(4); |
|
5513 ins_encode( enc_lwz(dst, mem) ); |
|
5514 ins_pipe(pipe_class_memory); |
|
5515 %} |
|
5516 |
|
5517 // Load Compressed Pointer acquire. |
|
5518 instruct loadN_ac(iRegNdst dst, memory mem) %{ |
|
5519 match(Set dst (LoadN mem)); |
|
5520 ins_cost(3*MEMORY_REF_COST); |
|
5521 |
|
5522 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" |
|
5523 "TWI $dst\n\t" |
|
5524 "ISYNC" %} |
|
5525 size(12); |
|
5526 ins_encode( enc_lwz_ac(dst, mem) ); |
|
5527 ins_pipe(pipe_class_memory); |
|
5528 %} |
|
5529 |
|
5530 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. |
|
5531 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ |
|
5532 match(Set dst (DecodeN (LoadN mem))); |
|
5533 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); |
|
5534 ins_cost(MEMORY_REF_COST); |
|
5535 |
|
5536 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} |
|
5537 size(4); |
|
5538 ins_encode( enc_lwz(dst, mem) ); |
|
5539 ins_pipe(pipe_class_memory); |
|
5540 %} |
|
5541 |
|
5542 // Load Pointer |
|
5543 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ |
|
5544 match(Set dst (LoadP mem)); |
|
5545 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5546 ins_cost(MEMORY_REF_COST); |
|
5547 |
|
5548 format %{ "LD $dst, $mem \t// ptr" %} |
|
5549 size(4); |
|
5550 ins_encode( enc_ld(dst, mem) ); |
|
5551 ins_pipe(pipe_class_memory); |
|
5552 %} |
|
5553 |
|
5554 // Load Pointer acquire. |
|
5555 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ |
|
5556 match(Set dst (LoadP mem)); |
|
5557 ins_cost(3*MEMORY_REF_COST); |
|
5558 |
|
5559 format %{ "LD $dst, $mem \t// ptr acquire\n\t" |
|
5560 "TWI $dst\n\t" |
|
5561 "ISYNC" %} |
|
5562 size(12); |
|
5563 ins_encode( enc_ld_ac(dst, mem) ); |
|
5564 ins_pipe(pipe_class_memory); |
|
5565 %} |
|
5566 |
|
5567 // LoadP + CastP2L |
|
5568 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ |
|
5569 match(Set dst (CastP2X (LoadP mem))); |
|
5570 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); |
|
5571 ins_cost(MEMORY_REF_COST); |
|
5572 |
|
5573 format %{ "LD $dst, $mem \t// ptr + p2x" %} |
|
5574 size(4); |
|
5575 ins_encode( enc_ld(dst, mem) ); |
|
5576 ins_pipe(pipe_class_memory); |
|
5577 %} |
|
5578 |
|
5579 // Load compressed klass pointer. |
|
5580 instruct loadNKlass(iRegNdst dst, memory mem) %{ |
|
5581 match(Set dst (LoadNKlass mem)); |
|
5582 ins_cost(MEMORY_REF_COST); |
|
5583 |
|
5584 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} |
|
5585 size(4); |
|
5586 ins_encode( enc_lwz(dst, mem) ); |
|
5587 ins_pipe(pipe_class_memory); |
|
5588 %} |
|
5589 |
|
5590 //// Load compressed klass and decode it if narrow_klass_shift == 0. |
|
5591 //// TODO: will narrow_klass_shift ever be 0? |
|
5592 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{ |
|
5593 // match(Set dst (DecodeNKlass (LoadNKlass mem))); |
|
5594 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*); |
|
5595 // ins_cost(MEMORY_REF_COST); |
|
5596 // |
|
5597 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %} |
|
5598 // size(4); |
|
5599 // ins_encode( enc_lwz(dst, mem) ); |
|
5600 // ins_pipe(pipe_class_memory); |
|
5601 //%} |
|
5602 |
|
5603 // Load Klass Pointer |
|
5604 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ |
|
5605 match(Set dst (LoadKlass mem)); |
|
5606 ins_cost(MEMORY_REF_COST); |
|
5607 |
|
5608 format %{ "LD $dst, $mem \t// klass ptr" %} |
|
5609 size(4); |
|
5610 ins_encode( enc_ld(dst, mem) ); |
|
5611 ins_pipe(pipe_class_memory); |
|
5612 %} |
|
5613 |
|
5614 // Load Float |
|
5615 instruct loadF(regF dst, memory mem) %{ |
|
5616 match(Set dst (LoadF mem)); |
|
5617 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5618 ins_cost(MEMORY_REF_COST); |
|
5619 |
|
5620 format %{ "LFS $dst, $mem" %} |
|
5621 size(4); |
|
5622 ins_encode %{ |
|
5623 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); |
|
5624 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5625 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
5626 %} |
|
5627 ins_pipe(pipe_class_memory); |
|
5628 %} |
|
5629 |
|
5630 // Load Float acquire. |
|
5631 instruct loadF_ac(regF dst, memory mem) %{ |
|
5632 match(Set dst (LoadF mem)); |
|
5633 ins_cost(3*MEMORY_REF_COST); |
|
5634 |
|
5635 format %{ "LFS $dst, $mem \t// acquire\n\t" |
|
5636 "FCMPU cr0, $dst, $dst\n\t" |
|
5637 "BNE cr0, next\n" |
|
5638 "next:\n\t" |
|
5639 "ISYNC" %} |
|
5640 size(16); |
|
5641 ins_encode %{ |
|
5642 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
5643 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5644 Label next; |
|
5645 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
5646 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); |
|
5647 __ bne(CCR0, next); |
|
5648 __ bind(next); |
|
5649 __ isync(); |
|
5650 %} |
|
5651 ins_pipe(pipe_class_memory); |
|
5652 %} |
|
5653 |
|
5654 // Load Double - aligned |
|
5655 instruct loadD(regD dst, memory mem) %{ |
|
5656 match(Set dst (LoadD mem)); |
|
5657 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); |
|
5658 ins_cost(MEMORY_REF_COST); |
|
5659 |
|
5660 format %{ "LFD $dst, $mem" %} |
|
5661 size(4); |
|
5662 ins_encode( enc_lfd(dst, mem) ); |
|
5663 ins_pipe(pipe_class_memory); |
|
5664 %} |
|
5665 |
|
5666 // Load Double - aligned acquire. |
|
5667 instruct loadD_ac(regD dst, memory mem) %{ |
|
5668 match(Set dst (LoadD mem)); |
|
5669 ins_cost(3*MEMORY_REF_COST); |
|
5670 |
|
5671 format %{ "LFD $dst, $mem \t// acquire\n\t" |
|
5672 "FCMPU cr0, $dst, $dst\n\t" |
|
5673 "BNE cr0, next\n" |
|
5674 "next:\n\t" |
|
5675 "ISYNC" %} |
|
5676 size(16); |
|
5677 ins_encode %{ |
|
5678 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
5679 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
5680 Label next; |
|
5681 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); |
|
5682 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); |
|
5683 __ bne(CCR0, next); |
|
5684 __ bind(next); |
|
5685 __ isync(); |
|
5686 %} |
|
5687 ins_pipe(pipe_class_memory); |
|
5688 %} |
|
5689 |
|
5690 // Load Double - UNaligned |
|
5691 instruct loadD_unaligned(regD dst, memory mem) %{ |
|
5692 match(Set dst (LoadD_unaligned mem)); |
|
5693 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). |
|
5694 ins_cost(MEMORY_REF_COST); |
|
5695 |
|
5696 format %{ "LFD $dst, $mem" %} |
|
5697 size(4); |
|
5698 ins_encode( enc_lfd(dst, mem) ); |
|
5699 ins_pipe(pipe_class_memory); |
|
5700 %} |
|
5701 |
|
5702 //----------Constants-------------------------------------------------------- |
|
5703 |
|
5704 // Load MachConstantTableBase: add hi offset to global toc. |
|
5705 // TODO: Handle hidden register r29 in bundler! |
|
5706 instruct loadToc_hi(iRegLdst dst) %{ |
|
5707 effect(DEF dst); |
|
5708 ins_cost(DEFAULT_COST); |
|
5709 |
|
5710 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} |
|
5711 size(4); |
|
5712 ins_encode %{ |
|
5713 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5714 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); |
|
5715 %} |
|
5716 ins_pipe(pipe_class_default); |
|
5717 %} |
|
5718 |
|
5719 // Load MachConstantTableBase: add lo offset to global toc. |
|
5720 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ |
|
5721 effect(DEF dst, USE src); |
|
5722 ins_cost(DEFAULT_COST); |
|
5723 |
|
5724 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} |
|
5725 size(4); |
|
5726 ins_encode %{ |
|
5727 // TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
5728 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); |
|
5729 %} |
|
5730 ins_pipe(pipe_class_default); |
|
5731 %} |
|
5732 |
|
5733 // Load 16-bit integer constant 0xssss???? |
|
5734 instruct loadConI16(iRegIdst dst, immI16 src) %{ |
|
5735 match(Set dst src); |
|
5736 |
|
5737 format %{ "LI $dst, $src" %} |
|
5738 size(4); |
|
5739 ins_encode %{ |
|
5740 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5741 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
5742 %} |
|
5743 ins_pipe(pipe_class_default); |
|
5744 %} |
|
5745 |
|
5746 // Load integer constant 0x????0000 |
|
5747 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ |
|
5748 match(Set dst src); |
|
5749 ins_cost(DEFAULT_COST); |
|
5750 |
|
5751 format %{ "LIS $dst, $src.hi" %} |
|
5752 size(4); |
|
5753 ins_encode %{ |
|
5754 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5755 // Lis sign extends 16-bit src then shifts it 16 bit to the left. |
|
5756 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); |
|
5757 %} |
|
5758 ins_pipe(pipe_class_default); |
|
5759 %} |
|
5760 |
|
5761 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted |
|
5762 // and sign extended), this adds the low 16 bits. |
|
5763 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ |
|
5764 // no match-rule, false predicate |
|
5765 effect(DEF dst, USE src1, USE src2); |
|
5766 predicate(false); |
|
5767 |
|
5768 format %{ "ORI $dst, $src1.hi, $src2.lo" %} |
|
5769 size(4); |
|
5770 ins_encode %{ |
|
5771 // TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
5772 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); |
|
5773 %} |
|
5774 ins_pipe(pipe_class_default); |
|
5775 %} |
|
5776 |
|
5777 instruct loadConI_Ex(iRegIdst dst, immI src) %{ |
|
5778 match(Set dst src); |
|
5779 ins_cost(DEFAULT_COST*2); |
|
5780 |
|
5781 expand %{ |
|
5782 // Would like to use $src$$constant. |
|
5783 immI16 srcLo %{ _opnds[1]->constant() %} |
|
5784 // srcHi can be 0000 if srcLo sign-extends to a negative number. |
|
5785 immIhi16 srcHi %{ _opnds[1]->constant() %} |
|
5786 iRegIdst tmpI; |
|
5787 loadConIhi16(tmpI, srcHi); |
|
5788 loadConI32_lo16(dst, tmpI, srcLo); |
|
5789 %} |
|
5790 %} |
|
5791 |
|
5792 // No constant pool entries required. |
|
5793 instruct loadConL16(iRegLdst dst, immL16 src) %{ |
|
5794 match(Set dst src); |
|
5795 |
|
5796 format %{ "LI $dst, $src \t// long" %} |
|
5797 size(4); |
|
5798 ins_encode %{ |
|
5799 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5800 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); |
|
5801 %} |
|
5802 ins_pipe(pipe_class_default); |
|
5803 %} |
|
5804 |
|
5805 // Load long constant 0xssssssss????0000 |
|
5806 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ |
|
5807 match(Set dst src); |
|
5808 ins_cost(DEFAULT_COST); |
|
5809 |
|
5810 format %{ "LIS $dst, $src.hi \t// long" %} |
|
5811 size(4); |
|
5812 ins_encode %{ |
|
5813 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5814 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); |
|
5815 %} |
|
5816 ins_pipe(pipe_class_default); |
|
5817 %} |
|
5818 |
|
5819 // To load a 32 bit constant: merge lower 16 bits into already loaded |
|
5820 // high 16 bits. |
|
5821 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ |
|
5822 // no match-rule, false predicate |
|
5823 effect(DEF dst, USE src1, USE src2); |
|
5824 predicate(false); |
|
5825 |
|
5826 format %{ "ORI $dst, $src1, $src2.lo" %} |
|
5827 size(4); |
|
5828 ins_encode %{ |
|
5829 // TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
5830 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); |
|
5831 %} |
|
5832 ins_pipe(pipe_class_default); |
|
5833 %} |
|
5834 |
|
5835 // Load 32-bit long constant |
|
5836 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ |
|
5837 match(Set dst src); |
|
5838 ins_cost(DEFAULT_COST*2); |
|
5839 |
|
5840 expand %{ |
|
5841 // Would like to use $src$$constant. |
|
5842 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} |
|
5843 // srcHi can be 0000 if srcLo sign-extends to a negative number. |
|
5844 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} |
|
5845 iRegLdst tmpL; |
|
5846 loadConL32hi16(tmpL, srcHi); |
|
5847 loadConL32_lo16(dst, tmpL, srcLo); |
|
5848 %} |
|
5849 %} |
|
5850 |
|
5851 // Load long constant 0x????000000000000. |
|
5852 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ |
|
5853 match(Set dst src); |
|
5854 ins_cost(DEFAULT_COST); |
|
5855 |
|
5856 expand %{ |
|
5857 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} |
|
5858 immI shift32 %{ 32 %} |
|
5859 iRegLdst tmpL; |
|
5860 loadConL32hi16(tmpL, srcHi); |
|
5861 lshiftL_regL_immI(dst, tmpL, shift32); |
|
5862 %} |
|
5863 %} |
|
5864 |
|
5865 // Expand node for constant pool load: small offset. |
|
5866 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ |
|
5867 effect(DEF dst, USE src, USE toc); |
|
5868 ins_cost(MEMORY_REF_COST); |
|
5869 |
|
5870 ins_num_consts(1); |
|
5871 // Needed so that CallDynamicJavaDirect can compute the address of this |
|
5872 // instruction for relocation. |
|
5873 ins_field_cbuf_insts_offset(int); |
|
5874 |
|
5875 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} |
|
5876 size(4); |
|
5877 ins_encode( enc_load_long_constL(dst, src, toc) ); |
|
5878 ins_pipe(pipe_class_memory); |
|
5879 %} |
|
5880 |
|
5881 // Expand node for constant pool load: large offset. |
|
5882 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ |
|
5883 effect(DEF dst, USE src, USE toc); |
|
5884 predicate(false); |
|
5885 |
|
5886 ins_num_consts(1); |
|
5887 ins_field_const_toc_offset(int); |
|
5888 // Needed so that CallDynamicJavaDirect can compute the address of this |
|
5889 // instruction for relocation. |
|
5890 ins_field_cbuf_insts_offset(int); |
|
5891 |
|
5892 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} |
|
5893 size(4); |
|
5894 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); |
|
5895 ins_pipe(pipe_class_default); |
|
5896 %} |
|
5897 |
|
5898 // Expand node for constant pool load: large offset. |
|
5899 // No constant pool entries required. |
|
5900 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ |
|
5901 effect(DEF dst, USE src, USE base); |
|
5902 predicate(false); |
|
5903 |
|
5904 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); |
|
5905 |
|
5906 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} |
|
5907 size(4); |
|
5908 ins_encode %{ |
|
5909 // TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
5910 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; |
|
5911 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); |
|
5912 %} |
|
5913 ins_pipe(pipe_class_memory); |
|
5914 %} |
|
5915 |
|
5916 // Load long constant from constant table. Expand in case of |
|
5917 // offset > 16 bit is needed. |
|
5918 // Adlc adds toc node MachConstantTableBase. |
|
5919 instruct loadConL_Ex(iRegLdst dst, immL src) %{ |
|
5920 match(Set dst src); |
|
5921 ins_cost(MEMORY_REF_COST); |
|
5922 |
|
5923 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} |
|
5924 // We can not inline the enc_class for the expand as that does not support constanttablebase. |
|
5925 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); |
|
5926 %} |
|
5927 |
|
5928 // Load NULL as compressed oop. |
|
5929 instruct loadConN0(iRegNdst dst, immN_0 src) %{ |
|
5930 match(Set dst src); |
|
5931 ins_cost(DEFAULT_COST); |
|
5932 |
|
5933 format %{ "LI $dst, $src \t// compressed ptr" %} |
|
5934 size(4); |
|
5935 ins_encode %{ |
|
5936 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5937 __ li($dst$$Register, 0); |
|
5938 %} |
|
5939 ins_pipe(pipe_class_default); |
|
5940 %} |
|
5941 |
|
5942 // Load hi part of compressed oop constant. |
|
5943 instruct loadConN_hi(iRegNdst dst, immN src) %{ |
|
5944 effect(DEF dst, USE src); |
|
5945 ins_cost(DEFAULT_COST); |
|
5946 |
|
5947 format %{ "LIS $dst, $src \t// narrow oop hi" %} |
|
5948 size(4); |
|
5949 ins_encode %{ |
|
5950 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
5951 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); |
|
5952 %} |
|
5953 ins_pipe(pipe_class_default); |
|
5954 %} |
|
5955 |
|
5956 // Add lo part of compressed oop constant to already loaded hi part. |
|
5957 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ |
|
5958 effect(DEF dst, USE src1, USE src2); |
|
5959 ins_cost(DEFAULT_COST); |
|
5960 |
|
5961 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} |
|
5962 size(4); |
|
5963 ins_encode %{ |
|
5964 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
5965 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
5966 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); |
|
5967 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
5968 __ relocate(rspec, 1); |
|
5969 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); |
|
5970 %} |
|
5971 ins_pipe(pipe_class_default); |
|
5972 %} |
|
5973 |
|
5974 // Needed to postalloc expand loadConN: ConN is loaded as ConI |
|
5975 // leaving the upper 32 bits with sign-extension bits. |
|
5976 // This clears these bits: dst = src & 0xFFFFFFFF. |
|
5977 // TODO: Eventually call this maskN_regN_FFFFFFFF. |
|
5978 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ |
|
5979 effect(DEF dst, USE src); |
|
5980 predicate(false); |
|
5981 |
|
5982 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask |
|
5983 size(4); |
|
5984 ins_encode %{ |
|
5985 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
5986 __ clrldi($dst$$Register, $src$$Register, 0x20); |
|
5987 %} |
|
5988 ins_pipe(pipe_class_default); |
|
5989 %} |
|
5990 |
|
5991 // Loading ConN must be postalloc expanded so that edges between |
|
5992 // the nodes are safe. They may not interfere with a safepoint. |
|
5993 // GL TODO: This needs three instructions: better put this into the constant pool. |
|
5994 instruct loadConN_Ex(iRegNdst dst, immN src) %{ |
|
5995 match(Set dst src); |
|
5996 ins_cost(DEFAULT_COST*2); |
|
5997 |
|
5998 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask |
|
5999 postalloc_expand %{ |
|
6000 MachNode *m1 = new (C) loadConN_hiNode(); |
|
6001 MachNode *m2 = new (C) loadConN_loNode(); |
|
6002 MachNode *m3 = new (C) clearMs32bNode(); |
|
6003 m1->add_req(NULL); |
|
6004 m2->add_req(NULL, m1); |
|
6005 m3->add_req(NULL, m2); |
|
6006 m1->_opnds[0] = op_dst; |
|
6007 m1->_opnds[1] = op_src; |
|
6008 m2->_opnds[0] = op_dst; |
|
6009 m2->_opnds[1] = op_dst; |
|
6010 m2->_opnds[2] = op_src; |
|
6011 m3->_opnds[0] = op_dst; |
|
6012 m3->_opnds[1] = op_dst; |
|
6013 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6014 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6015 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6016 nodes->push(m1); |
|
6017 nodes->push(m2); |
|
6018 nodes->push(m3); |
|
6019 %} |
|
6020 %} |
|
6021 |
|
6022 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{ |
|
6023 effect(DEF dst, USE src); |
|
6024 ins_cost(DEFAULT_COST); |
|
6025 |
|
6026 format %{ "LIS $dst, $src \t// narrow oop hi" %} |
|
6027 size(4); |
|
6028 ins_encode %{ |
|
6029 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
6030 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); |
|
6031 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); |
|
6032 %} |
|
6033 ins_pipe(pipe_class_default); |
|
6034 %} |
|
6035 |
|
6036 // This needs a match rule so that build_oop_map knows this is |
|
6037 // not a narrow oop. |
|
6038 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ |
|
6039 match(Set dst src1); |
|
6040 effect(TEMP src2); |
|
6041 ins_cost(DEFAULT_COST); |
|
6042 |
|
6043 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %} |
|
6044 size(4); |
|
6045 ins_encode %{ |
|
6046 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
6047 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); |
|
6048 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
6049 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); |
|
6050 RelocationHolder rspec = metadata_Relocation::spec(klass_index); |
|
6051 |
|
6052 __ relocate(rspec, 1); |
|
6053 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); |
|
6054 %} |
|
6055 ins_pipe(pipe_class_default); |
|
6056 %} |
|
6057 |
|
6058 // Loading ConNKlass must be postalloc expanded so that edges between |
|
6059 // the nodes are safe. They may not interfere with a safepoint. |
|
6060 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ |
|
6061 match(Set dst src); |
|
6062 ins_cost(DEFAULT_COST*2); |
|
6063 |
|
6064 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask |
|
6065 postalloc_expand %{ |
|
6066 // Load high bits into register. Sign extended. |
|
6067 MachNode *m1 = new (C) loadConNKlass_hiNode(); |
|
6068 m1->add_req(NULL); |
|
6069 m1->_opnds[0] = op_dst; |
|
6070 m1->_opnds[1] = op_src; |
|
6071 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6072 nodes->push(m1); |
|
6073 |
|
6074 MachNode *m2 = m1; |
|
6075 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { |
|
6076 // Value might be 1-extended. Mask out these bits. |
|
6077 m2 = new (C) clearMs32bNode(); |
|
6078 m2->add_req(NULL, m1); |
|
6079 m2->_opnds[0] = op_dst; |
|
6080 m2->_opnds[1] = op_dst; |
|
6081 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6082 nodes->push(m2); |
|
6083 } |
|
6084 |
|
6085 MachNode *m3 = new (C) loadConNKlass_loNode(); |
|
6086 m3->add_req(NULL, m2); |
|
6087 m3->_opnds[0] = op_dst; |
|
6088 m3->_opnds[1] = op_src; |
|
6089 m3->_opnds[2] = op_dst; |
|
6090 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6091 nodes->push(m3); |
|
6092 %} |
|
6093 %} |
|
6094 |
|
6095 // 0x1 is used in object initialization (initial object header). |
|
6096 // No constant pool entries required. |
|
6097 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ |
|
6098 match(Set dst src); |
|
6099 |
|
6100 format %{ "LI $dst, $src \t// ptr" %} |
|
6101 size(4); |
|
6102 ins_encode %{ |
|
6103 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
6104 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
6105 %} |
|
6106 ins_pipe(pipe_class_default); |
|
6107 %} |
|
6108 |
|
6109 // Expand node for constant pool load: small offset. |
|
6110 // The match rule is needed to generate the correct bottom_type(), |
|
6111 // however this node should never match. The use of predicate is not |
|
6112 // possible since ADLC forbids predicates for chain rules. The higher |
|
6113 // costs do not prevent matching in this case. For that reason the |
|
6114 // operand immP_NM with predicate(false) is used. |
|
6115 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ |
|
6116 match(Set dst src); |
|
6117 effect(TEMP toc); |
|
6118 |
|
6119 ins_num_consts(1); |
|
6120 |
|
6121 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} |
|
6122 size(4); |
|
6123 ins_encode( enc_load_long_constP(dst, src, toc) ); |
|
6124 ins_pipe(pipe_class_memory); |
|
6125 %} |
|
6126 |
|
6127 // Expand node for constant pool load: large offset. |
|
6128 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ |
|
6129 effect(DEF dst, USE src, USE toc); |
|
6130 predicate(false); |
|
6131 |
|
6132 ins_num_consts(1); |
|
6133 ins_field_const_toc_offset(int); |
|
6134 |
|
6135 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} |
|
6136 size(4); |
|
6137 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); |
|
6138 ins_pipe(pipe_class_default); |
|
6139 %} |
|
6140 |
|
6141 // Expand node for constant pool load: large offset. |
|
6142 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ |
|
6143 match(Set dst src); |
|
6144 effect(TEMP base); |
|
6145 |
|
6146 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); |
|
6147 |
|
6148 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} |
|
6149 size(4); |
|
6150 ins_encode %{ |
|
6151 // TODO: PPC port $archOpcode(ppc64Opcode_ld); |
|
6152 int offset = ra_->C->in_scratch_emit_size() ? 0 : MacroAssembler::largeoffset_si16_si16_lo(_const_toc_offset_hi_node->_const_toc_offset); |
|
6153 __ ld($dst$$Register, offset, $base$$Register); |
|
6154 %} |
|
6155 ins_pipe(pipe_class_memory); |
|
6156 %} |
|
6157 |
|
6158 // Load pointer constant from constant table. Expand in case an |
|
6159 // offset > 16 bit is needed. |
|
6160 // Adlc adds toc node MachConstantTableBase. |
|
6161 instruct loadConP_Ex(iRegPdst dst, immP src) %{ |
|
6162 match(Set dst src); |
|
6163 ins_cost(MEMORY_REF_COST); |
|
6164 |
|
6165 // This rule does not use "expand" because then |
|
6166 // the result type is not known to be an Oop. An ADLC |
|
6167 // enhancement will be needed to make that work - not worth it! |
|
6168 |
|
6169 // If this instruction rematerializes, it prolongs the live range |
|
6170 // of the toc node, causing illegal graphs. |
|
6171 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). |
|
6172 ins_cannot_rematerialize(true); |
|
6173 |
|
6174 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} |
|
6175 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); |
|
6176 %} |
|
6177 |
|
6178 // Expand node for constant pool load: small offset. |
|
6179 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ |
|
6180 effect(DEF dst, USE src, USE toc); |
|
6181 ins_cost(MEMORY_REF_COST); |
|
6182 |
|
6183 ins_num_consts(1); |
|
6184 |
|
6185 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} |
|
6186 size(4); |
|
6187 ins_encode %{ |
|
6188 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); |
|
6189 address float_address = __ float_constant($src$$constant); |
|
6190 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); |
|
6191 %} |
|
6192 ins_pipe(pipe_class_memory); |
|
6193 %} |
|
6194 |
|
6195 // Expand node for constant pool load: large offset. |
|
6196 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ |
|
6197 effect(DEF dst, USE src, USE toc); |
|
6198 ins_cost(MEMORY_REF_COST); |
|
6199 |
|
6200 ins_num_consts(1); |
|
6201 |
|
6202 format %{ "ADDIS $toc, $toc, offset_hi\n\t" |
|
6203 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" |
|
6204 "ADDIS $toc, $toc, -offset_hi"%} |
|
6205 size(12); |
|
6206 ins_encode %{ |
|
6207 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6208 FloatRegister Rdst = $dst$$FloatRegister; |
|
6209 Register Rtoc = $toc$$Register; |
|
6210 address float_address = __ float_constant($src$$constant); |
|
6211 int offset = __ offset_to_method_toc(float_address); |
|
6212 int hi = (offset + (1<<15))>>16; |
|
6213 int lo = offset - hi * (1<<16); |
|
6214 |
|
6215 __ addis(Rtoc, Rtoc, hi); |
|
6216 __ lfs(Rdst, lo, Rtoc); |
|
6217 __ addis(Rtoc, Rtoc, -hi); |
|
6218 %} |
|
6219 ins_pipe(pipe_class_memory); |
|
6220 %} |
|
6221 |
|
6222 // Adlc adds toc node MachConstantTableBase. |
|
6223 instruct loadConF_Ex(regF dst, immF src) %{ |
|
6224 match(Set dst src); |
|
6225 ins_cost(MEMORY_REF_COST); |
|
6226 |
|
6227 // See loadConP. |
|
6228 ins_cannot_rematerialize(true); |
|
6229 |
|
6230 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} |
|
6231 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); |
|
6232 %} |
|
6233 |
|
6234 // Expand node for constant pool load: small offset. |
|
6235 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ |
|
6236 effect(DEF dst, USE src, USE toc); |
|
6237 ins_cost(MEMORY_REF_COST); |
|
6238 |
|
6239 ins_num_consts(1); |
|
6240 |
|
6241 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} |
|
6242 size(4); |
|
6243 ins_encode %{ |
|
6244 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); |
|
6245 int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); |
|
6246 __ lfd($dst$$FloatRegister, offset, $toc$$Register); |
|
6247 %} |
|
6248 ins_pipe(pipe_class_memory); |
|
6249 %} |
|
6250 |
|
6251 // Expand node for constant pool load: large offset. |
|
6252 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ |
|
6253 effect(DEF dst, USE src, USE toc); |
|
6254 ins_cost(MEMORY_REF_COST); |
|
6255 |
|
6256 ins_num_consts(1); |
|
6257 |
|
6258 format %{ "ADDIS $toc, $toc, offset_hi\n\t" |
|
6259 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" |
|
6260 "ADDIS $toc, $toc, -offset_hi" %} |
|
6261 size(12); |
|
6262 ins_encode %{ |
|
6263 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6264 FloatRegister Rdst = $dst$$FloatRegister; |
|
6265 Register Rtoc = $toc$$Register; |
|
6266 address float_address = __ double_constant($src$$constant); |
|
6267 int offset = __ offset_to_method_toc(float_address); |
|
6268 int hi = (offset + (1<<15))>>16; |
|
6269 int lo = offset - hi * (1<<16); |
|
6270 |
|
6271 __ addis(Rtoc, Rtoc, hi); |
|
6272 __ lfd(Rdst, lo, Rtoc); |
|
6273 __ addis(Rtoc, Rtoc, -hi); |
|
6274 %} |
|
6275 ins_pipe(pipe_class_memory); |
|
6276 %} |
|
6277 |
|
6278 // Adlc adds toc node MachConstantTableBase. |
|
6279 instruct loadConD_Ex(regD dst, immD src) %{ |
|
6280 match(Set dst src); |
|
6281 ins_cost(MEMORY_REF_COST); |
|
6282 |
|
6283 // See loadConP. |
|
6284 ins_cannot_rematerialize(true); |
|
6285 |
|
6286 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} |
|
6287 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); |
|
6288 %} |
|
6289 |
|
6290 // Prefetch instructions. |
|
6291 // Must be safe to execute with invalid address (cannot fault). |
|
6292 |
|
6293 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{ |
|
6294 match(PrefetchRead (AddP mem src)); |
|
6295 ins_cost(MEMORY_REF_COST); |
|
6296 |
|
6297 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %} |
|
6298 size(4); |
|
6299 ins_encode %{ |
|
6300 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); |
|
6301 __ dcbt($src$$Register, $mem$$base$$Register); |
|
6302 %} |
|
6303 ins_pipe(pipe_class_memory); |
|
6304 %} |
|
6305 |
|
6306 instruct prefetchr_no_offset(indirectMemory mem) %{ |
|
6307 match(PrefetchRead mem); |
|
6308 ins_cost(MEMORY_REF_COST); |
|
6309 |
|
6310 format %{ "PREFETCH $mem" %} |
|
6311 size(4); |
|
6312 ins_encode %{ |
|
6313 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); |
|
6314 __ dcbt($mem$$base$$Register); |
|
6315 %} |
|
6316 ins_pipe(pipe_class_memory); |
|
6317 %} |
|
6318 |
|
6319 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{ |
|
6320 match(PrefetchWrite (AddP mem src)); |
|
6321 ins_cost(MEMORY_REF_COST); |
|
6322 |
|
6323 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %} |
|
6324 size(4); |
|
6325 ins_encode %{ |
|
6326 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6327 __ dcbtst($src$$Register, $mem$$base$$Register); |
|
6328 %} |
|
6329 ins_pipe(pipe_class_memory); |
|
6330 %} |
|
6331 |
|
6332 instruct prefetchw_no_offset(indirectMemory mem) %{ |
|
6333 match(PrefetchWrite mem); |
|
6334 ins_cost(MEMORY_REF_COST); |
|
6335 |
|
6336 format %{ "PREFETCH $mem" %} |
|
6337 size(4); |
|
6338 ins_encode %{ |
|
6339 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6340 __ dcbtst($mem$$base$$Register); |
|
6341 %} |
|
6342 ins_pipe(pipe_class_memory); |
|
6343 %} |
|
6344 |
|
6345 // Special prefetch versions which use the dcbz instruction. |
|
6346 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ |
|
6347 match(PrefetchAllocation (AddP mem src)); |
|
6348 predicate(AllocatePrefetchStyle == 3); |
|
6349 ins_cost(MEMORY_REF_COST); |
|
6350 |
|
6351 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} |
|
6352 size(4); |
|
6353 ins_encode %{ |
|
6354 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6355 __ dcbz($src$$Register, $mem$$base$$Register); |
|
6356 %} |
|
6357 ins_pipe(pipe_class_memory); |
|
6358 %} |
|
6359 |
|
6360 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ |
|
6361 match(PrefetchAllocation mem); |
|
6362 predicate(AllocatePrefetchStyle == 3); |
|
6363 ins_cost(MEMORY_REF_COST); |
|
6364 |
|
6365 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} |
|
6366 size(4); |
|
6367 ins_encode %{ |
|
6368 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6369 __ dcbz($mem$$base$$Register); |
|
6370 %} |
|
6371 ins_pipe(pipe_class_memory); |
|
6372 %} |
|
6373 |
|
6374 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ |
|
6375 match(PrefetchAllocation (AddP mem src)); |
|
6376 predicate(AllocatePrefetchStyle != 3); |
|
6377 ins_cost(MEMORY_REF_COST); |
|
6378 |
|
6379 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} |
|
6380 size(4); |
|
6381 ins_encode %{ |
|
6382 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6383 __ dcbtst($src$$Register, $mem$$base$$Register); |
|
6384 %} |
|
6385 ins_pipe(pipe_class_memory); |
|
6386 %} |
|
6387 |
|
6388 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ |
|
6389 match(PrefetchAllocation mem); |
|
6390 predicate(AllocatePrefetchStyle != 3); |
|
6391 ins_cost(MEMORY_REF_COST); |
|
6392 |
|
6393 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} |
|
6394 size(4); |
|
6395 ins_encode %{ |
|
6396 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); |
|
6397 __ dcbtst($mem$$base$$Register); |
|
6398 %} |
|
6399 ins_pipe(pipe_class_memory); |
|
6400 %} |
|
6401 |
|
6402 //----------Store Instructions------------------------------------------------- |
|
6403 |
|
6404 // Store Byte |
|
6405 instruct storeB(memory mem, iRegIsrc src) %{ |
|
6406 match(Set mem (StoreB mem src)); |
|
6407 ins_cost(MEMORY_REF_COST); |
|
6408 |
|
6409 format %{ "STB $src, $mem \t// byte" %} |
|
6410 size(4); |
|
6411 ins_encode %{ |
|
6412 // TODO: PPC port $archOpcode(ppc64Opcode_stb); |
|
6413 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
6414 __ stb($src$$Register, Idisp, $mem$$base$$Register); |
|
6415 %} |
|
6416 ins_pipe(pipe_class_memory); |
|
6417 %} |
|
6418 |
|
6419 // Store Char/Short |
|
6420 instruct storeC(memory mem, iRegIsrc src) %{ |
|
6421 match(Set mem (StoreC mem src)); |
|
6422 ins_cost(MEMORY_REF_COST); |
|
6423 |
|
6424 format %{ "STH $src, $mem \t// short" %} |
|
6425 size(4); |
|
6426 ins_encode %{ |
|
6427 // TODO: PPC port $archOpcode(ppc64Opcode_sth); |
|
6428 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); |
|
6429 __ sth($src$$Register, Idisp, $mem$$base$$Register); |
|
6430 %} |
|
6431 ins_pipe(pipe_class_memory); |
|
6432 %} |
|
6433 |
|
6434 // Store Integer |
|
6435 instruct storeI(memory mem, iRegIsrc src) %{ |
|
6436 match(Set mem (StoreI mem src)); |
|
6437 ins_cost(MEMORY_REF_COST); |
|
6438 |
|
6439 format %{ "STW $src, $mem" %} |
|
6440 size(4); |
|
6441 ins_encode( enc_stw(src, mem) ); |
|
6442 ins_pipe(pipe_class_memory); |
|
6443 %} |
|
6444 |
|
6445 // ConvL2I + StoreI. |
|
6446 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ |
|
6447 match(Set mem (StoreI mem (ConvL2I src))); |
|
6448 ins_cost(MEMORY_REF_COST); |
|
6449 |
|
6450 format %{ "STW l2i($src), $mem" %} |
|
6451 size(4); |
|
6452 ins_encode( enc_stw(src, mem) ); |
|
6453 ins_pipe(pipe_class_memory); |
|
6454 %} |
|
6455 |
|
6456 // Store Long |
|
6457 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ |
|
6458 match(Set mem (StoreL mem src)); |
|
6459 ins_cost(MEMORY_REF_COST); |
|
6460 |
|
6461 format %{ "STD $src, $mem \t// long" %} |
|
6462 size(4); |
|
6463 ins_encode( enc_std(src, mem) ); |
|
6464 ins_pipe(pipe_class_memory); |
|
6465 %} |
|
6466 |
|
6467 // Store super word nodes. |
|
6468 |
|
6469 // Store Aligned Packed Byte long register to memory |
|
6470 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ |
|
6471 predicate(n->as_StoreVector()->memory_size() == 8); |
|
6472 match(Set mem (StoreVector mem src)); |
|
6473 ins_cost(MEMORY_REF_COST); |
|
6474 |
|
6475 format %{ "STD $mem, $src \t// packed8B" %} |
|
6476 size(4); |
|
6477 ins_encode( enc_std(src, mem) ); |
|
6478 ins_pipe(pipe_class_memory); |
|
6479 %} |
|
6480 |
|
6481 // Store Compressed Oop |
|
6482 instruct storeN(memory dst, iRegN_P2N src) %{ |
|
6483 match(Set dst (StoreN dst src)); |
|
6484 ins_cost(MEMORY_REF_COST); |
|
6485 |
|
6486 format %{ "STW $src, $dst \t// compressed oop" %} |
|
6487 size(4); |
|
6488 ins_encode( enc_stw(src, dst) ); |
|
6489 ins_pipe(pipe_class_memory); |
|
6490 %} |
|
6491 |
|
6492 // Store Compressed KLass |
|
6493 instruct storeNKlass(memory dst, iRegN_P2N src) %{ |
|
6494 match(Set dst (StoreNKlass dst src)); |
|
6495 ins_cost(MEMORY_REF_COST); |
|
6496 |
|
6497 format %{ "STW $src, $dst \t// compressed klass" %} |
|
6498 size(4); |
|
6499 ins_encode( enc_stw(src, dst) ); |
|
6500 ins_pipe(pipe_class_memory); |
|
6501 %} |
|
6502 |
|
6503 // Store Pointer |
|
6504 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ |
|
6505 match(Set dst (StoreP dst src)); |
|
6506 ins_cost(MEMORY_REF_COST); |
|
6507 |
|
6508 format %{ "STD $src, $dst \t// ptr" %} |
|
6509 size(4); |
|
6510 ins_encode( enc_std(src, dst) ); |
|
6511 ins_pipe(pipe_class_memory); |
|
6512 %} |
|
6513 |
|
6514 // Store Float |
|
6515 instruct storeF(memory mem, regF src) %{ |
|
6516 match(Set mem (StoreF mem src)); |
|
6517 ins_cost(MEMORY_REF_COST); |
|
6518 |
|
6519 format %{ "STFS $src, $mem" %} |
|
6520 size(4); |
|
6521 ins_encode( enc_stfs(src, mem) ); |
|
6522 ins_pipe(pipe_class_memory); |
|
6523 %} |
|
6524 |
|
6525 // Store Double |
|
6526 instruct storeD(memory mem, regD src) %{ |
|
6527 match(Set mem (StoreD mem src)); |
|
6528 ins_cost(MEMORY_REF_COST); |
|
6529 |
|
6530 format %{ "STFD $src, $mem" %} |
|
6531 size(4); |
|
6532 ins_encode( enc_stfd(src, mem) ); |
|
6533 ins_pipe(pipe_class_memory); |
|
6534 %} |
|
6535 |
|
6536 //----------Store Instructions With Zeros-------------------------------------- |
|
6537 |
|
6538 // Card-mark for CMS garbage collection. |
|
6539 // This cardmark does an optimization so that it must not always |
|
6540 // do a releasing store. For this, it gets the address of |
|
6541 // CMSCollectorCardTableModRefBSExt::_requires_release as input. |
|
6542 // (Using releaseFieldAddr in the match rule is a hack.) |
|
6543 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{ |
|
6544 match(Set mem (StoreCM mem releaseFieldAddr)); |
|
6545 predicate(false); |
|
6546 ins_cost(MEMORY_REF_COST); |
|
6547 |
|
6548 // See loadConP. |
|
6549 ins_cannot_rematerialize(true); |
|
6550 |
|
6551 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} |
|
6552 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) ); |
|
6553 ins_pipe(pipe_class_memory); |
|
6554 %} |
|
6555 |
|
6556 // Card-mark for CMS garbage collection. |
|
6557 // This cardmark does an optimization so that it must not always |
|
6558 // do a releasing store. For this, it needs the constant address of |
|
6559 // CMSCollectorCardTableModRefBSExt::_requires_release. |
|
6560 // This constant address is split off here by expand so we can use |
|
6561 // adlc / matcher functionality to load it from the constant section. |
|
6562 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ |
|
6563 match(Set mem (StoreCM mem zero)); |
|
6564 predicate(UseConcMarkSweepGC); |
|
6565 |
|
6566 expand %{ |
|
6567 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} |
|
6568 iRegLdst releaseFieldAddress; |
|
6569 loadConL_Ex(releaseFieldAddress, baseImm); |
|
6570 storeCM_CMS(mem, releaseFieldAddress); |
|
6571 %} |
|
6572 %} |
|
6573 |
|
6574 instruct storeCM_G1(memory mem, immI_0 zero) %{ |
|
6575 match(Set mem (StoreCM mem zero)); |
|
6576 predicate(UseG1GC); |
|
6577 ins_cost(MEMORY_REF_COST); |
|
6578 |
|
6579 ins_cannot_rematerialize(true); |
|
6580 |
|
6581 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} |
|
6582 size(8); |
|
6583 ins_encode %{ |
|
6584 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6585 __ li(R0, 0); |
|
6586 //__ release(); // G1: oops are allowed to get visible after dirty marking |
|
6587 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); |
|
6588 __ stb(R0, $mem$$disp, $mem$$base$$Register); |
|
6589 %} |
|
6590 ins_pipe(pipe_class_memory); |
|
6591 %} |
|
6592 |
|
6593 // Convert oop pointer into compressed form. |
|
6594 |
|
6595 // Nodes for postalloc expand. |
|
6596 |
|
6597 // Shift node for expand. |
|
6598 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ |
|
6599 // The match rule is needed to make it a 'MachTypeNode'! |
|
6600 match(Set dst (EncodeP src)); |
|
6601 predicate(false); |
|
6602 |
|
6603 format %{ "SRDI $dst, $src, 3 \t// encode" %} |
|
6604 size(4); |
|
6605 ins_encode %{ |
|
6606 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6607 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); |
|
6608 %} |
|
6609 ins_pipe(pipe_class_default); |
|
6610 %} |
|
6611 |
|
6612 // Add node for expand. |
|
6613 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ |
|
6614 // The match rule is needed to make it a 'MachTypeNode'! |
|
6615 match(Set dst (EncodeP src)); |
|
6616 predicate(false); |
|
6617 |
|
6618 format %{ "SUB $dst, $src, oop_base \t// encode" %} |
|
6619 size(4); |
|
6620 ins_encode %{ |
|
6621 // TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
6622 __ subf($dst$$Register, R30, $src$$Register); |
|
6623 %} |
|
6624 ins_pipe(pipe_class_default); |
|
6625 %} |
|
6626 |
|
6627 // Conditional sub base. |
|
6628 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ |
|
6629 // The match rule is needed to make it a 'MachTypeNode'! |
|
6630 match(Set dst (EncodeP (Binary crx src1))); |
|
6631 predicate(false); |
|
6632 |
|
6633 ins_variable_size_depending_on_alignment(true); |
|
6634 |
|
6635 format %{ "BEQ $crx, done\n\t" |
|
6636 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n" |
|
6637 "done:" %} |
|
6638 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
6639 ins_encode %{ |
|
6640 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
6641 Label done; |
|
6642 __ beq($crx$$CondRegister, done); |
|
6643 __ subf($dst$$Register, R30, $src1$$Register); |
|
6644 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
6645 __ bind(done); |
|
6646 %} |
|
6647 ins_pipe(pipe_class_default); |
|
6648 %} |
|
6649 |
|
6650 // Power 7 can use isel instruction |
|
6651 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ |
|
6652 // The match rule is needed to make it a 'MachTypeNode'! |
|
6653 match(Set dst (EncodeP (Binary crx src1))); |
|
6654 predicate(false); |
|
6655 |
|
6656 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} |
|
6657 size(4); |
|
6658 ins_encode %{ |
|
6659 // This is a Power7 instruction for which no machine description exists. |
|
6660 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6661 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); |
|
6662 %} |
|
6663 ins_pipe(pipe_class_default); |
|
6664 %} |
|
6665 |
|
6666 // base != 0 |
|
6667 // 32G aligned narrow oop base. |
|
6668 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{ |
|
6669 match(Set dst (EncodeP src)); |
|
6670 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/); |
|
6671 |
|
6672 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} |
|
6673 size(4); |
|
6674 ins_encode %{ |
|
6675 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6676 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); |
|
6677 %} |
|
6678 ins_pipe(pipe_class_default); |
|
6679 %} |
|
6680 |
|
6681 // shift != 0, base != 0 |
|
6682 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ |
|
6683 match(Set dst (EncodeP src)); |
|
6684 effect(TEMP crx); |
|
6685 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && |
|
6686 Universe::narrow_oop_shift() != 0 && |
|
6687 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); |
|
6688 |
|
6689 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} |
|
6690 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); |
|
6691 %} |
|
6692 |
|
6693 // shift != 0, base != 0 |
|
6694 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ |
|
6695 match(Set dst (EncodeP src)); |
|
6696 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && |
|
6697 Universe::narrow_oop_shift() != 0 && |
|
6698 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); |
|
6699 |
|
6700 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} |
|
6701 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); |
|
6702 %} |
|
6703 |
|
6704 // shift != 0, base == 0 |
|
6705 // TODO: This is the same as encodeP_shift. Merge! |
|
6706 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ |
|
6707 match(Set dst (EncodeP src)); |
|
6708 predicate(Universe::narrow_oop_shift() != 0 && |
|
6709 Universe::narrow_oop_base() ==0); |
|
6710 |
|
6711 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} |
|
6712 size(4); |
|
6713 ins_encode %{ |
|
6714 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6715 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); |
|
6716 %} |
|
6717 ins_pipe(pipe_class_default); |
|
6718 %} |
|
6719 |
|
6720 // Compressed OOPs with narrow_oop_shift == 0. |
|
6721 // shift == 0, base == 0 |
|
6722 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ |
|
6723 match(Set dst (EncodeP src)); |
|
6724 predicate(Universe::narrow_oop_shift() == 0); |
|
6725 |
|
6726 format %{ "MR $dst, $src \t// Ptr->Narrow" %} |
|
6727 // variable size, 0 or 4. |
|
6728 ins_encode %{ |
|
6729 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
6730 __ mr_if_needed($dst$$Register, $src$$Register); |
|
6731 %} |
|
6732 ins_pipe(pipe_class_default); |
|
6733 %} |
|
6734 |
|
6735 // Decode nodes. |
|
6736 |
|
6737 // Shift node for expand. |
|
6738 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ |
|
6739 // The match rule is needed to make it a 'MachTypeNode'! |
|
6740 match(Set dst (DecodeN src)); |
|
6741 predicate(false); |
|
6742 |
|
6743 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} |
|
6744 size(4); |
|
6745 ins_encode %{ |
|
6746 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
6747 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); |
|
6748 %} |
|
6749 ins_pipe(pipe_class_default); |
|
6750 %} |
|
6751 |
|
6752 // Add node for expand. |
|
6753 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ |
|
6754 // The match rule is needed to make it a 'MachTypeNode'! |
|
6755 match(Set dst (DecodeN src)); |
|
6756 predicate(false); |
|
6757 |
|
6758 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %} |
|
6759 size(4); |
|
6760 ins_encode %{ |
|
6761 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
6762 __ add($dst$$Register, $src$$Register, R30); |
|
6763 %} |
|
6764 ins_pipe(pipe_class_default); |
|
6765 %} |
|
6766 |
|
6767 // conditianal add base for expand |
|
6768 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ |
|
6769 // The match rule is needed to make it a 'MachTypeNode'! |
|
6770 // NOTICE that the rule is nonsense - we just have to make sure that: |
|
6771 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) |
|
6772 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. |
|
6773 match(Set dst (DecodeN (Binary crx src1))); |
|
6774 predicate(false); |
|
6775 |
|
6776 ins_variable_size_depending_on_alignment(true); |
|
6777 |
|
6778 format %{ "BEQ $crx, done\n\t" |
|
6779 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n" |
|
6780 "done:" %} |
|
6781 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8); |
|
6782 ins_encode %{ |
|
6783 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
6784 Label done; |
|
6785 __ beq($crx$$CondRegister, done); |
|
6786 __ add($dst$$Register, $src1$$Register, R30); |
|
6787 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
6788 __ bind(done); |
|
6789 %} |
|
6790 ins_pipe(pipe_class_default); |
|
6791 %} |
|
6792 |
|
6793 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ |
|
6794 // The match rule is needed to make it a 'MachTypeNode'! |
|
6795 // NOTICE that the rule is nonsense - we just have to make sure that: |
|
6796 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) |
|
6797 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. |
|
6798 match(Set dst (DecodeN (Binary crx src1))); |
|
6799 predicate(false); |
|
6800 |
|
6801 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} |
|
6802 size(4); |
|
6803 ins_encode %{ |
|
6804 // This is a Power7 instruction for which no machine description exists. |
|
6805 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
6806 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); |
|
6807 %} |
|
6808 ins_pipe(pipe_class_default); |
|
6809 %} |
|
6810 |
|
6811 // shift != 0, base != 0 |
|
6812 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ |
|
6813 match(Set dst (DecodeN src)); |
|
6814 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
6815 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && |
|
6816 Universe::narrow_oop_shift() != 0 && |
|
6817 Universe::narrow_oop_base() != 0); |
|
6818 effect(TEMP crx); |
|
6819 |
|
6820 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} |
|
6821 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); |
|
6822 %} |
|
6823 |
|
6824 // shift != 0, base == 0 |
|
6825 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ |
|
6826 match(Set dst (DecodeN src)); |
|
6827 predicate(Universe::narrow_oop_shift() != 0 && |
|
6828 Universe::narrow_oop_base() == 0); |
|
6829 |
|
6830 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} |
|
6831 size(4); |
|
6832 ins_encode %{ |
|
6833 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
6834 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); |
|
6835 %} |
|
6836 ins_pipe(pipe_class_default); |
|
6837 %} |
|
6838 |
|
6839 // src != 0, shift != 0, base != 0 |
|
6840 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ |
|
6841 match(Set dst (DecodeN src)); |
|
6842 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
6843 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && |
|
6844 Universe::narrow_oop_shift() != 0 && |
|
6845 Universe::narrow_oop_base() != 0); |
|
6846 |
|
6847 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} |
|
6848 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); |
|
6849 %} |
|
6850 |
|
6851 // Compressed OOPs with narrow_oop_shift == 0. |
|
6852 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ |
|
6853 match(Set dst (DecodeN src)); |
|
6854 predicate(Universe::narrow_oop_shift() == 0); |
|
6855 ins_cost(DEFAULT_COST); |
|
6856 |
|
6857 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} |
|
6858 // variable size, 0 or 4. |
|
6859 ins_encode %{ |
|
6860 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
6861 __ mr_if_needed($dst$$Register, $src$$Register); |
|
6862 %} |
|
6863 ins_pipe(pipe_class_default); |
|
6864 %} |
|
6865 |
|
6866 // Convert compressed oop into int for vectors alignment masking. |
|
6867 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ |
|
6868 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
6869 predicate(Universe::narrow_oop_shift() == 0); |
|
6870 ins_cost(DEFAULT_COST); |
|
6871 |
|
6872 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} |
|
6873 // variable size, 0 or 4. |
|
6874 ins_encode %{ |
|
6875 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
6876 __ mr_if_needed($dst$$Register, $src$$Register); |
|
6877 %} |
|
6878 ins_pipe(pipe_class_default); |
|
6879 %} |
|
6880 |
|
6881 // Convert klass pointer into compressed form. |
|
6882 |
|
6883 // Nodes for postalloc expand. |
|
6884 |
|
6885 // Shift node for expand. |
|
6886 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ |
|
6887 // The match rule is needed to make it a 'MachTypeNode'! |
|
6888 match(Set dst (EncodePKlass src)); |
|
6889 predicate(false); |
|
6890 |
|
6891 format %{ "SRDI $dst, $src, 3 \t// encode" %} |
|
6892 size(4); |
|
6893 ins_encode %{ |
|
6894 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6895 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); |
|
6896 %} |
|
6897 ins_pipe(pipe_class_default); |
|
6898 %} |
|
6899 |
|
6900 // Add node for expand. |
|
6901 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ |
|
6902 // The match rule is needed to make it a 'MachTypeNode'! |
|
6903 match(Set dst (EncodePKlass (Binary base src))); |
|
6904 predicate(false); |
|
6905 |
|
6906 format %{ "SUB $dst, $base, $src \t// encode" %} |
|
6907 size(4); |
|
6908 ins_encode %{ |
|
6909 // TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
6910 __ subf($dst$$Register, $base$$Register, $src$$Register); |
|
6911 %} |
|
6912 ins_pipe(pipe_class_default); |
|
6913 %} |
|
6914 |
|
6915 // base != 0 |
|
6916 // 32G aligned narrow oop base. |
|
6917 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{ |
|
6918 match(Set dst (EncodePKlass src)); |
|
6919 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); |
|
6920 |
|
6921 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} |
|
6922 size(4); |
|
6923 ins_encode %{ |
|
6924 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
6925 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); |
|
6926 %} |
|
6927 ins_pipe(pipe_class_default); |
|
6928 %} |
|
6929 |
|
6930 // shift != 0, base != 0 |
|
6931 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ |
|
6932 match(Set dst (EncodePKlass (Binary base src))); |
|
6933 predicate(false); |
|
6934 |
|
6935 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} |
|
6936 postalloc_expand %{ |
|
6937 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode(); |
|
6938 n1->add_req(n_region, n_base, n_src); |
|
6939 n1->_opnds[0] = op_dst; |
|
6940 n1->_opnds[1] = op_base; |
|
6941 n1->_opnds[2] = op_src; |
|
6942 n1->_bottom_type = _bottom_type; |
|
6943 |
|
6944 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode(); |
|
6945 n2->add_req(n_region, n1); |
|
6946 n2->_opnds[0] = op_dst; |
|
6947 n2->_opnds[1] = op_dst; |
|
6948 n2->_bottom_type = _bottom_type; |
|
6949 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6950 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
6951 |
|
6952 nodes->push(n1); |
|
6953 nodes->push(n2); |
|
6954 %} |
|
6955 %} |
|
6956 |
|
6957 // shift != 0, base != 0 |
|
6958 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ |
|
6959 match(Set dst (EncodePKlass src)); |
|
6960 //predicate(Universe::narrow_klass_shift() != 0 && |
|
6961 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); |
|
6962 |
|
6963 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} |
|
6964 ins_cost(DEFAULT_COST*2); // Don't count constant. |
|
6965 expand %{ |
|
6966 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} |
|
6967 iRegLdst base; |
|
6968 loadConL_Ex(base, baseImm); |
|
6969 encodePKlass_not_null_Ex(dst, base, src); |
|
6970 %} |
|
6971 %} |
|
6972 |
|
6973 // Decode nodes. |
|
6974 |
|
6975 // Shift node for expand. |
|
6976 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ |
|
6977 // The match rule is needed to make it a 'MachTypeNode'! |
|
6978 match(Set dst (DecodeNKlass src)); |
|
6979 predicate(false); |
|
6980 |
|
6981 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} |
|
6982 size(4); |
|
6983 ins_encode %{ |
|
6984 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
6985 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); |
|
6986 %} |
|
6987 ins_pipe(pipe_class_default); |
|
6988 %} |
|
6989 |
|
6990 // Add node for expand. |
|
6991 |
|
6992 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ |
|
6993 // The match rule is needed to make it a 'MachTypeNode'! |
|
6994 match(Set dst (DecodeNKlass (Binary base src))); |
|
6995 predicate(false); |
|
6996 |
|
6997 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} |
|
6998 size(4); |
|
6999 ins_encode %{ |
|
7000 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7001 __ add($dst$$Register, $base$$Register, $src$$Register); |
|
7002 %} |
|
7003 ins_pipe(pipe_class_default); |
|
7004 %} |
|
7005 |
|
7006 // src != 0, shift != 0, base != 0 |
|
7007 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ |
|
7008 match(Set dst (DecodeNKlass (Binary base src))); |
|
7009 //effect(kill src); // We need a register for the immediate result after shifting. |
|
7010 predicate(false); |
|
7011 |
|
7012 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} |
|
7013 postalloc_expand %{ |
|
7014 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode(); |
|
7015 n1->add_req(n_region, n_base, n_src); |
|
7016 n1->_opnds[0] = op_dst; |
|
7017 n1->_opnds[1] = op_base; |
|
7018 n1->_opnds[2] = op_src; |
|
7019 n1->_bottom_type = _bottom_type; |
|
7020 |
|
7021 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode(); |
|
7022 n2->add_req(n_region, n2); |
|
7023 n2->_opnds[0] = op_dst; |
|
7024 n2->_opnds[1] = op_dst; |
|
7025 n2->_bottom_type = _bottom_type; |
|
7026 |
|
7027 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
7028 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); |
|
7029 |
|
7030 nodes->push(n1); |
|
7031 nodes->push(n2); |
|
7032 %} |
|
7033 %} |
|
7034 |
|
7035 // src != 0, shift != 0, base != 0 |
|
7036 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ |
|
7037 match(Set dst (DecodeNKlass src)); |
|
7038 // predicate(Universe::narrow_klass_shift() != 0 && |
|
7039 // Universe::narrow_klass_base() != 0); |
|
7040 |
|
7041 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} |
|
7042 |
|
7043 ins_cost(DEFAULT_COST*2); // Don't count constant. |
|
7044 expand %{ |
|
7045 // We add first, then we shift. Like this, we can get along with one register less. |
|
7046 // But we have to load the base pre-shifted. |
|
7047 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} |
|
7048 iRegLdst base; |
|
7049 loadConL_Ex(base, baseImm); |
|
7050 decodeNKlass_notNull_addBase_Ex(dst, base, src); |
|
7051 %} |
|
7052 %} |
|
7053 |
|
7054 //----------MemBar Instructions----------------------------------------------- |
|
7055 // Memory barrier flavors |
|
7056 |
|
7057 instruct membar_acquire() %{ |
|
7058 match(LoadFence); |
|
7059 ins_cost(4*MEMORY_REF_COST); |
|
7060 |
|
7061 format %{ "MEMBAR-acquire" %} |
|
7062 size(4); |
|
7063 ins_encode %{ |
|
7064 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); |
|
7065 __ acquire(); |
|
7066 %} |
|
7067 ins_pipe(pipe_class_default); |
|
7068 %} |
|
7069 |
|
7070 instruct unnecessary_membar_acquire() %{ |
|
7071 match(MemBarAcquire); |
|
7072 ins_cost(0); |
|
7073 |
|
7074 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} |
|
7075 size(0); |
|
7076 ins_encode( /*empty*/ ); |
|
7077 ins_pipe(pipe_class_default); |
|
7078 %} |
|
7079 |
|
7080 instruct membar_acquire_lock() %{ |
|
7081 match(MemBarAcquireLock); |
|
7082 ins_cost(0); |
|
7083 |
|
7084 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} |
|
7085 size(0); |
|
7086 ins_encode( /*empty*/ ); |
|
7087 ins_pipe(pipe_class_default); |
|
7088 %} |
|
7089 |
|
7090 instruct membar_release() %{ |
|
7091 match(MemBarRelease); |
|
7092 match(StoreFence); |
|
7093 ins_cost(4*MEMORY_REF_COST); |
|
7094 |
|
7095 format %{ "MEMBAR-release" %} |
|
7096 size(4); |
|
7097 ins_encode %{ |
|
7098 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); |
|
7099 __ release(); |
|
7100 %} |
|
7101 ins_pipe(pipe_class_default); |
|
7102 %} |
|
7103 |
|
7104 instruct membar_storestore() %{ |
|
7105 match(MemBarStoreStore); |
|
7106 ins_cost(4*MEMORY_REF_COST); |
|
7107 |
|
7108 format %{ "MEMBAR-store-store" %} |
|
7109 size(4); |
|
7110 ins_encode %{ |
|
7111 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); |
|
7112 __ membar(Assembler::StoreStore); |
|
7113 %} |
|
7114 ins_pipe(pipe_class_default); |
|
7115 %} |
|
7116 |
|
7117 instruct membar_release_lock() %{ |
|
7118 match(MemBarReleaseLock); |
|
7119 ins_cost(0); |
|
7120 |
|
7121 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} |
|
7122 size(0); |
|
7123 ins_encode( /*empty*/ ); |
|
7124 ins_pipe(pipe_class_default); |
|
7125 %} |
|
7126 |
|
7127 instruct membar_volatile() %{ |
|
7128 match(MemBarVolatile); |
|
7129 ins_cost(4*MEMORY_REF_COST); |
|
7130 |
|
7131 format %{ "MEMBAR-volatile" %} |
|
7132 size(4); |
|
7133 ins_encode %{ |
|
7134 // TODO: PPC port $archOpcode(ppc64Opcode_sync); |
|
7135 __ fence(); |
|
7136 %} |
|
7137 ins_pipe(pipe_class_default); |
|
7138 %} |
|
7139 |
|
7140 // This optimization is wrong on PPC. The following pattern is not supported: |
|
7141 // MemBarVolatile |
|
7142 // ^ ^ |
|
7143 // | | |
|
7144 // CtrlProj MemProj |
|
7145 // ^ ^ |
|
7146 // | | |
|
7147 // | Load |
|
7148 // | |
|
7149 // MemBarVolatile |
|
7150 // |
|
7151 // The first MemBarVolatile could get optimized out! According to |
|
7152 // Vladimir, this pattern can not occur on Oracle platforms. |
|
7153 // However, it does occur on PPC64 (because of membars in |
|
7154 // inline_unsafe_load_store). |
|
7155 // |
|
7156 // Add this node again if we found a good solution for inline_unsafe_load_store(). |
|
7157 // Don't forget to look at the implementation of post_store_load_barrier again, |
|
7158 // we did other fixes in that method. |
|
7159 //instruct unnecessary_membar_volatile() %{ |
|
7160 // match(MemBarVolatile); |
|
7161 // predicate(Matcher::post_store_load_barrier(n)); |
|
7162 // ins_cost(0); |
|
7163 // |
|
7164 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} |
|
7165 // size(0); |
|
7166 // ins_encode( /*empty*/ ); |
|
7167 // ins_pipe(pipe_class_default); |
|
7168 //%} |
|
7169 |
|
7170 instruct membar_CPUOrder() %{ |
|
7171 match(MemBarCPUOrder); |
|
7172 ins_cost(0); |
|
7173 |
|
7174 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} |
|
7175 size(0); |
|
7176 ins_encode( /*empty*/ ); |
|
7177 ins_pipe(pipe_class_default); |
|
7178 %} |
|
7179 |
|
7180 //----------Conditional Move--------------------------------------------------- |
|
7181 |
|
7182 // Cmove using isel. |
|
7183 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ |
|
7184 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); |
|
7185 predicate(VM_Version::has_isel()); |
|
7186 ins_cost(DEFAULT_COST); |
|
7187 |
|
7188 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7189 size(4); |
|
7190 ins_encode %{ |
|
7191 // This is a Power7 instruction for which no machine description |
|
7192 // exists. Anyways, the scheduler should be off on Power7. |
|
7193 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7194 int cc = $cmp$$cmpcode; |
|
7195 __ isel($dst$$Register, $crx$$CondRegister, |
|
7196 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7197 %} |
|
7198 ins_pipe(pipe_class_default); |
|
7199 %} |
|
7200 |
|
7201 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ |
|
7202 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); |
|
7203 predicate(!VM_Version::has_isel()); |
|
7204 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7205 |
|
7206 ins_variable_size_depending_on_alignment(true); |
|
7207 |
|
7208 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7209 // Worst case is branch + move + stop, no stop without scheduler |
|
7210 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7211 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7212 ins_pipe(pipe_class_default); |
|
7213 %} |
|
7214 |
|
7215 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{ |
|
7216 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); |
|
7217 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7218 |
|
7219 ins_variable_size_depending_on_alignment(true); |
|
7220 |
|
7221 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7222 // Worst case is branch + move + stop, no stop without scheduler |
|
7223 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7224 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7225 ins_pipe(pipe_class_default); |
|
7226 %} |
|
7227 |
|
7228 // Cmove using isel. |
|
7229 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ |
|
7230 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); |
|
7231 predicate(VM_Version::has_isel()); |
|
7232 ins_cost(DEFAULT_COST); |
|
7233 |
|
7234 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7235 size(4); |
|
7236 ins_encode %{ |
|
7237 // This is a Power7 instruction for which no machine description |
|
7238 // exists. Anyways, the scheduler should be off on Power7. |
|
7239 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7240 int cc = $cmp$$cmpcode; |
|
7241 __ isel($dst$$Register, $crx$$CondRegister, |
|
7242 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7243 %} |
|
7244 ins_pipe(pipe_class_default); |
|
7245 %} |
|
7246 |
|
7247 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ |
|
7248 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); |
|
7249 predicate(!VM_Version::has_isel()); |
|
7250 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7251 |
|
7252 ins_variable_size_depending_on_alignment(true); |
|
7253 |
|
7254 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7255 // Worst case is branch + move + stop, no stop without scheduler. |
|
7256 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7257 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7258 ins_pipe(pipe_class_default); |
|
7259 %} |
|
7260 |
|
7261 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{ |
|
7262 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); |
|
7263 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7264 |
|
7265 ins_variable_size_depending_on_alignment(true); |
|
7266 |
|
7267 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7268 // Worst case is branch + move + stop, no stop without scheduler. |
|
7269 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7270 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7271 ins_pipe(pipe_class_default); |
|
7272 %} |
|
7273 |
|
7274 // Cmove using isel. |
|
7275 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ |
|
7276 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); |
|
7277 predicate(VM_Version::has_isel()); |
|
7278 ins_cost(DEFAULT_COST); |
|
7279 |
|
7280 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7281 size(4); |
|
7282 ins_encode %{ |
|
7283 // This is a Power7 instruction for which no machine description |
|
7284 // exists. Anyways, the scheduler should be off on Power7. |
|
7285 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7286 int cc = $cmp$$cmpcode; |
|
7287 __ isel($dst$$Register, $crx$$CondRegister, |
|
7288 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7289 %} |
|
7290 ins_pipe(pipe_class_default); |
|
7291 %} |
|
7292 |
|
7293 // Conditional move for RegN. Only cmov(reg, reg). |
|
7294 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ |
|
7295 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); |
|
7296 predicate(!VM_Version::has_isel()); |
|
7297 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7298 |
|
7299 ins_variable_size_depending_on_alignment(true); |
|
7300 |
|
7301 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7302 // Worst case is branch + move + stop, no stop without scheduler. |
|
7303 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7304 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7305 ins_pipe(pipe_class_default); |
|
7306 %} |
|
7307 |
|
7308 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{ |
|
7309 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); |
|
7310 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7311 |
|
7312 ins_variable_size_depending_on_alignment(true); |
|
7313 |
|
7314 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7315 // Worst case is branch + move + stop, no stop without scheduler. |
|
7316 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7317 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7318 ins_pipe(pipe_class_default); |
|
7319 %} |
|
7320 |
|
7321 // Cmove using isel. |
|
7322 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{ |
|
7323 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); |
|
7324 predicate(VM_Version::has_isel()); |
|
7325 ins_cost(DEFAULT_COST); |
|
7326 |
|
7327 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7328 size(4); |
|
7329 ins_encode %{ |
|
7330 // This is a Power7 instruction for which no machine description |
|
7331 // exists. Anyways, the scheduler should be off on Power7. |
|
7332 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7333 int cc = $cmp$$cmpcode; |
|
7334 __ isel($dst$$Register, $crx$$CondRegister, |
|
7335 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); |
|
7336 %} |
|
7337 ins_pipe(pipe_class_default); |
|
7338 %} |
|
7339 |
|
7340 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{ |
|
7341 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); |
|
7342 predicate(!VM_Version::has_isel()); |
|
7343 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7344 |
|
7345 ins_variable_size_depending_on_alignment(true); |
|
7346 |
|
7347 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7348 // Worst case is branch + move + stop, no stop without scheduler. |
|
7349 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7350 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); |
|
7351 ins_pipe(pipe_class_default); |
|
7352 %} |
|
7353 |
|
7354 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{ |
|
7355 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); |
|
7356 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7357 |
|
7358 ins_variable_size_depending_on_alignment(true); |
|
7359 |
|
7360 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} |
|
7361 // Worst case is branch + move + stop, no stop without scheduler. |
|
7362 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
7363 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); |
|
7364 ins_pipe(pipe_class_default); |
|
7365 %} |
|
7366 |
|
7367 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{ |
|
7368 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); |
|
7369 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7370 |
|
7371 ins_variable_size_depending_on_alignment(true); |
|
7372 |
|
7373 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} |
|
7374 // Worst case is branch + move + stop, no stop without scheduler. |
|
7375 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
7376 ins_encode %{ |
|
7377 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); |
|
7378 Label done; |
|
7379 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
7380 // Branch if not (cmp crx). |
|
7381 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); |
|
7382 __ fmr($dst$$FloatRegister, $src$$FloatRegister); |
|
7383 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
7384 __ bind(done); |
|
7385 %} |
|
7386 ins_pipe(pipe_class_default); |
|
7387 %} |
|
7388 |
|
7389 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{ |
|
7390 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); |
|
7391 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
7392 |
|
7393 ins_variable_size_depending_on_alignment(true); |
|
7394 |
|
7395 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} |
|
7396 // Worst case is branch + move + stop, no stop without scheduler. |
|
7397 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
7398 ins_encode %{ |
|
7399 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); |
|
7400 Label done; |
|
7401 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); |
|
7402 // Branch if not (cmp crx). |
|
7403 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); |
|
7404 __ fmr($dst$$FloatRegister, $src$$FloatRegister); |
|
7405 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
7406 __ bind(done); |
|
7407 %} |
|
7408 ins_pipe(pipe_class_default); |
|
7409 %} |
|
7410 |
|
7411 //----------Conditional_store-------------------------------------------------- |
|
7412 // Conditional-store of the updated heap-top. |
|
7413 // Used during allocation of the shared heap. |
|
7414 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. |
|
7415 |
|
7416 // As compareAndSwapL, but return flag register instead of boolean value in |
|
7417 // int register. |
|
7418 // Used by sun/misc/AtomicLongCSImpl.java. |
|
7419 // Mem_ptr must be a memory operand, else this node does not get |
|
7420 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node |
|
7421 // can be rematerialized which leads to errors. |
|
7422 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{ |
|
7423 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); |
|
7424 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} |
|
7425 ins_encode %{ |
|
7426 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7427 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, |
|
7428 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7429 noreg, NULL, true); |
|
7430 %} |
|
7431 ins_pipe(pipe_class_default); |
|
7432 %} |
|
7433 |
|
7434 // As compareAndSwapP, but return flag register instead of boolean value in |
|
7435 // int register. |
|
7436 // This instruction is matched if UseTLAB is off. |
|
7437 // Mem_ptr must be a memory operand, else this node does not get |
|
7438 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node |
|
7439 // can be rematerialized which leads to errors. |
|
7440 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ |
|
7441 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal))); |
|
7442 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} |
|
7443 ins_encode %{ |
|
7444 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7445 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, |
|
7446 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7447 noreg, NULL, true); |
|
7448 %} |
|
7449 ins_pipe(pipe_class_default); |
|
7450 %} |
|
7451 |
|
7452 // Implement LoadPLocked. Must be ordered against changes of the memory location |
|
7453 // by storePConditional. |
|
7454 // Don't know whether this is ever used. |
|
7455 instruct loadPLocked(iRegPdst dst, memory mem) %{ |
|
7456 match(Set dst (LoadPLocked mem)); |
|
7457 ins_cost(MEMORY_REF_COST); |
|
7458 |
|
7459 format %{ "LD $dst, $mem \t// loadPLocked\n\t" |
|
7460 "TWI $dst\n\t" |
|
7461 "ISYNC" %} |
|
7462 size(12); |
|
7463 ins_encode( enc_ld_ac(dst, mem) ); |
|
7464 ins_pipe(pipe_class_memory); |
|
7465 %} |
|
7466 |
|
7467 //----------Compare-And-Swap--------------------------------------------------- |
|
7468 |
|
7469 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI |
|
7470 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be |
|
7471 // matched. |
|
7472 |
|
7473 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{ |
|
7474 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); |
|
7475 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} |
|
7476 // Variable size: instruction count smaller if regs are disjoint. |
|
7477 ins_encode %{ |
|
7478 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7479 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7480 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7481 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7482 $res$$Register, true); |
|
7483 %} |
|
7484 ins_pipe(pipe_class_default); |
|
7485 %} |
|
7486 |
|
7487 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{ |
|
7488 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); |
|
7489 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} |
|
7490 // Variable size: instruction count smaller if regs are disjoint. |
|
7491 ins_encode %{ |
|
7492 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7493 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7494 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7495 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7496 $res$$Register, true); |
|
7497 %} |
|
7498 ins_pipe(pipe_class_default); |
|
7499 %} |
|
7500 |
|
7501 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{ |
|
7502 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); |
|
7503 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} |
|
7504 // Variable size: instruction count smaller if regs are disjoint. |
|
7505 ins_encode %{ |
|
7506 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7507 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7508 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7509 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7510 $res$$Register, NULL, true); |
|
7511 %} |
|
7512 ins_pipe(pipe_class_default); |
|
7513 %} |
|
7514 |
|
7515 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{ |
|
7516 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); |
|
7517 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} |
|
7518 // Variable size: instruction count smaller if regs are disjoint. |
|
7519 ins_encode %{ |
|
7520 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
7521 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. |
|
7522 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, |
|
7523 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), |
|
7524 $res$$Register, NULL, true); |
|
7525 %} |
|
7526 ins_pipe(pipe_class_default); |
|
7527 %} |
|
7528 |
|
7529 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ |
|
7530 match(Set res (GetAndAddI mem_ptr src)); |
|
7531 format %{ "GetAndAddI $res, $mem_ptr, $src" %} |
|
7532 // Variable size: instruction count smaller if regs are disjoint. |
|
7533 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); |
|
7534 ins_pipe(pipe_class_default); |
|
7535 %} |
|
7536 |
|
7537 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ |
|
7538 match(Set res (GetAndAddL mem_ptr src)); |
|
7539 format %{ "GetAndAddL $res, $mem_ptr, $src" %} |
|
7540 // Variable size: instruction count smaller if regs are disjoint. |
|
7541 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); |
|
7542 ins_pipe(pipe_class_default); |
|
7543 %} |
|
7544 |
|
7545 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ |
|
7546 match(Set res (GetAndSetI mem_ptr src)); |
|
7547 format %{ "GetAndSetI $res, $mem_ptr, $src" %} |
|
7548 // Variable size: instruction count smaller if regs are disjoint. |
|
7549 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); |
|
7550 ins_pipe(pipe_class_default); |
|
7551 %} |
|
7552 |
|
7553 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ |
|
7554 match(Set res (GetAndSetL mem_ptr src)); |
|
7555 format %{ "GetAndSetL $res, $mem_ptr, $src" %} |
|
7556 // Variable size: instruction count smaller if regs are disjoint. |
|
7557 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); |
|
7558 ins_pipe(pipe_class_default); |
|
7559 %} |
|
7560 |
|
7561 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{ |
|
7562 match(Set res (GetAndSetP mem_ptr src)); |
|
7563 format %{ "GetAndSetP $res, $mem_ptr, $src" %} |
|
7564 // Variable size: instruction count smaller if regs are disjoint. |
|
7565 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); |
|
7566 ins_pipe(pipe_class_default); |
|
7567 %} |
|
7568 |
|
7569 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{ |
|
7570 match(Set res (GetAndSetN mem_ptr src)); |
|
7571 format %{ "GetAndSetN $res, $mem_ptr, $src" %} |
|
7572 // Variable size: instruction count smaller if regs are disjoint. |
|
7573 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); |
|
7574 ins_pipe(pipe_class_default); |
|
7575 %} |
|
7576 |
|
7577 //----------Arithmetic Instructions-------------------------------------------- |
|
7578 // Addition Instructions |
|
7579 |
|
7580 // PPC has no instruction setting overflow of 32-bit integer. |
|
7581 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{ |
|
7582 // match(AddExactI dst src); |
|
7583 // effect(DEF cr); |
|
7584 // |
|
7585 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %} |
|
7586 // ins_encode( enc_add(dst, dst, src) ); |
|
7587 // ins_pipe(pipe_class_default); |
|
7588 //%} |
|
7589 |
|
7590 // Register Addition |
|
7591 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ |
|
7592 match(Set dst (AddI src1 src2)); |
|
7593 format %{ "ADD $dst, $src1, $src2" %} |
|
7594 size(4); |
|
7595 ins_encode %{ |
|
7596 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7597 __ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7598 %} |
|
7599 ins_pipe(pipe_class_default); |
|
7600 %} |
|
7601 |
|
7602 // Expand does not work with above instruct. (??) |
|
7603 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
7604 // no match-rule |
|
7605 effect(DEF dst, USE src1, USE src2); |
|
7606 format %{ "ADD $dst, $src1, $src2" %} |
|
7607 size(4); |
|
7608 ins_encode %{ |
|
7609 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7610 __ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7611 %} |
|
7612 ins_pipe(pipe_class_default); |
|
7613 %} |
|
7614 |
|
7615 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ |
|
7616 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); |
|
7617 ins_cost(DEFAULT_COST*3); |
|
7618 |
|
7619 expand %{ |
|
7620 // FIXME: we should do this in the ideal world. |
|
7621 iRegIdst tmp1; |
|
7622 iRegIdst tmp2; |
|
7623 addI_reg_reg(tmp1, src1, src2); |
|
7624 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. |
|
7625 addI_reg_reg(dst, tmp1, tmp2); |
|
7626 %} |
|
7627 %} |
|
7628 |
|
7629 // Immediate Addition |
|
7630 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ |
|
7631 match(Set dst (AddI src1 src2)); |
|
7632 format %{ "ADDI $dst, $src1, $src2" %} |
|
7633 size(4); |
|
7634 ins_encode %{ |
|
7635 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7636 __ addi($dst$$Register, $src1$$Register, $src2$$constant); |
|
7637 %} |
|
7638 ins_pipe(pipe_class_default); |
|
7639 %} |
|
7640 |
|
7641 // Immediate Addition with 16-bit shifted operand |
|
7642 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ |
|
7643 match(Set dst (AddI src1 src2)); |
|
7644 format %{ "ADDIS $dst, $src1, $src2" %} |
|
7645 size(4); |
|
7646 ins_encode %{ |
|
7647 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
7648 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); |
|
7649 %} |
|
7650 ins_pipe(pipe_class_default); |
|
7651 %} |
|
7652 |
|
7653 // Long Addition |
|
7654 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7655 match(Set dst (AddL src1 src2)); |
|
7656 format %{ "ADD $dst, $src1, $src2 \t// long" %} |
|
7657 size(4); |
|
7658 ins_encode %{ |
|
7659 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7660 __ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7661 %} |
|
7662 ins_pipe(pipe_class_default); |
|
7663 %} |
|
7664 |
|
7665 // Expand does not work with above instruct. (??) |
|
7666 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7667 // no match-rule |
|
7668 effect(DEF dst, USE src1, USE src2); |
|
7669 format %{ "ADD $dst, $src1, $src2 \t// long" %} |
|
7670 size(4); |
|
7671 ins_encode %{ |
|
7672 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7673 __ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7674 %} |
|
7675 ins_pipe(pipe_class_default); |
|
7676 %} |
|
7677 |
|
7678 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ |
|
7679 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); |
|
7680 ins_cost(DEFAULT_COST*3); |
|
7681 |
|
7682 expand %{ |
|
7683 // FIXME: we should do this in the ideal world. |
|
7684 iRegLdst tmp1; |
|
7685 iRegLdst tmp2; |
|
7686 addL_reg_reg(tmp1, src1, src2); |
|
7687 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. |
|
7688 addL_reg_reg(dst, tmp1, tmp2); |
|
7689 %} |
|
7690 %} |
|
7691 |
|
7692 // AddL + ConvL2I. |
|
7693 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7694 match(Set dst (ConvL2I (AddL src1 src2))); |
|
7695 |
|
7696 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} |
|
7697 size(4); |
|
7698 ins_encode %{ |
|
7699 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7700 __ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7701 %} |
|
7702 ins_pipe(pipe_class_default); |
|
7703 %} |
|
7704 |
|
7705 // No constant pool entries required. |
|
7706 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ |
|
7707 match(Set dst (AddL src1 src2)); |
|
7708 |
|
7709 format %{ "ADDI $dst, $src1, $src2" %} |
|
7710 size(4); |
|
7711 ins_encode %{ |
|
7712 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7713 __ addi($dst$$Register, $src1$$Register, $src2$$constant); |
|
7714 %} |
|
7715 ins_pipe(pipe_class_default); |
|
7716 %} |
|
7717 |
|
7718 // Long Immediate Addition with 16-bit shifted operand. |
|
7719 // No constant pool entries required. |
|
7720 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ |
|
7721 match(Set dst (AddL src1 src2)); |
|
7722 |
|
7723 format %{ "ADDIS $dst, $src1, $src2" %} |
|
7724 size(4); |
|
7725 ins_encode %{ |
|
7726 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
7727 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); |
|
7728 %} |
|
7729 ins_pipe(pipe_class_default); |
|
7730 %} |
|
7731 |
|
7732 // Pointer Register Addition |
|
7733 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ |
|
7734 match(Set dst (AddP src1 src2)); |
|
7735 format %{ "ADD $dst, $src1, $src2" %} |
|
7736 size(4); |
|
7737 ins_encode %{ |
|
7738 // TODO: PPC port $archOpcode(ppc64Opcode_add); |
|
7739 __ add($dst$$Register, $src1$$Register, $src2$$Register); |
|
7740 %} |
|
7741 ins_pipe(pipe_class_default); |
|
7742 %} |
|
7743 |
|
7744 // Pointer Immediate Addition |
|
7745 // No constant pool entries required. |
|
7746 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ |
|
7747 match(Set dst (AddP src1 src2)); |
|
7748 |
|
7749 format %{ "ADDI $dst, $src1, $src2" %} |
|
7750 size(4); |
|
7751 ins_encode %{ |
|
7752 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7753 __ addi($dst$$Register, $src1$$Register, $src2$$constant); |
|
7754 %} |
|
7755 ins_pipe(pipe_class_default); |
|
7756 %} |
|
7757 |
|
7758 // Pointer Immediate Addition with 16-bit shifted operand. |
|
7759 // No constant pool entries required. |
|
7760 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ |
|
7761 match(Set dst (AddP src1 src2)); |
|
7762 |
|
7763 format %{ "ADDIS $dst, $src1, $src2" %} |
|
7764 size(4); |
|
7765 ins_encode %{ |
|
7766 // TODO: PPC port $archOpcode(ppc64Opcode_addis); |
|
7767 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); |
|
7768 %} |
|
7769 ins_pipe(pipe_class_default); |
|
7770 %} |
|
7771 |
|
7772 //--------------------- |
|
7773 // Subtraction Instructions |
|
7774 |
|
7775 // Register Subtraction |
|
7776 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
7777 match(Set dst (SubI src1 src2)); |
|
7778 format %{ "SUBF $dst, $src2, $src1" %} |
|
7779 size(4); |
|
7780 ins_encode %{ |
|
7781 // TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
7782 __ subf($dst$$Register, $src2$$Register, $src1$$Register); |
|
7783 %} |
|
7784 ins_pipe(pipe_class_default); |
|
7785 %} |
|
7786 |
|
7787 // Immediate Subtraction |
|
7788 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal), |
|
7789 // so this rule seems to be unused. |
|
7790 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ |
|
7791 match(Set dst (SubI src1 src2)); |
|
7792 format %{ "SUBI $dst, $src1, $src2" %} |
|
7793 size(4); |
|
7794 ins_encode %{ |
|
7795 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7796 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); |
|
7797 %} |
|
7798 ins_pipe(pipe_class_default); |
|
7799 %} |
|
7800 |
|
7801 // SubI from constant (using subfic). |
|
7802 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ |
|
7803 match(Set dst (SubI src1 src2)); |
|
7804 format %{ "SUBI $dst, $src1, $src2" %} |
|
7805 |
|
7806 size(4); |
|
7807 ins_encode %{ |
|
7808 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); |
|
7809 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); |
|
7810 %} |
|
7811 ins_pipe(pipe_class_default); |
|
7812 %} |
|
7813 |
|
7814 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for |
|
7815 // positive integers and 0xF...F for negative ones. |
|
7816 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ |
|
7817 // no match-rule, false predicate |
|
7818 effect(DEF dst, USE src); |
|
7819 predicate(false); |
|
7820 |
|
7821 format %{ "SRAWI $dst, $src, #31" %} |
|
7822 size(4); |
|
7823 ins_encode %{ |
|
7824 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); |
|
7825 __ srawi($dst$$Register, $src$$Register, 0x1f); |
|
7826 %} |
|
7827 ins_pipe(pipe_class_default); |
|
7828 %} |
|
7829 |
|
7830 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ |
|
7831 match(Set dst (AbsI src)); |
|
7832 ins_cost(DEFAULT_COST*3); |
|
7833 |
|
7834 expand %{ |
|
7835 iRegIdst tmp1; |
|
7836 iRegIdst tmp2; |
|
7837 signmask32I_regI(tmp1, src); |
|
7838 xorI_reg_reg(tmp2, tmp1, src); |
|
7839 subI_reg_reg(dst, tmp2, tmp1); |
|
7840 %} |
|
7841 %} |
|
7842 |
|
7843 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ |
|
7844 match(Set dst (SubI zero src2)); |
|
7845 format %{ "NEG $dst, $src2" %} |
|
7846 size(4); |
|
7847 ins_encode %{ |
|
7848 // TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7849 __ neg($dst$$Register, $src2$$Register); |
|
7850 %} |
|
7851 ins_pipe(pipe_class_default); |
|
7852 %} |
|
7853 |
|
7854 // Long subtraction |
|
7855 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7856 match(Set dst (SubL src1 src2)); |
|
7857 format %{ "SUBF $dst, $src2, $src1 \t// long" %} |
|
7858 size(4); |
|
7859 ins_encode %{ |
|
7860 // TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
7861 __ subf($dst$$Register, $src2$$Register, $src1$$Register); |
|
7862 %} |
|
7863 ins_pipe(pipe_class_default); |
|
7864 %} |
|
7865 |
|
7866 // SubL + convL2I. |
|
7867 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7868 match(Set dst (ConvL2I (SubL src1 src2))); |
|
7869 |
|
7870 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} |
|
7871 size(4); |
|
7872 ins_encode %{ |
|
7873 // TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
7874 __ subf($dst$$Register, $src2$$Register, $src1$$Register); |
|
7875 %} |
|
7876 ins_pipe(pipe_class_default); |
|
7877 %} |
|
7878 |
|
7879 // Immediate Subtraction |
|
7880 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), |
|
7881 // so this rule seems to be unused. |
|
7882 // No constant pool entries required. |
|
7883 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ |
|
7884 match(Set dst (SubL src1 src2)); |
|
7885 |
|
7886 format %{ "SUBI $dst, $src1, $src2 \t// long" %} |
|
7887 size(4); |
|
7888 ins_encode %{ |
|
7889 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
7890 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); |
|
7891 %} |
|
7892 ins_pipe(pipe_class_default); |
|
7893 %} |
|
7894 |
|
7895 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for |
|
7896 // positive longs and 0xF...F for negative ones. |
|
7897 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{ |
|
7898 // no match-rule, false predicate |
|
7899 effect(DEF dst, USE src); |
|
7900 predicate(false); |
|
7901 |
|
7902 format %{ "SRADI $dst, $src, #63" %} |
|
7903 size(4); |
|
7904 ins_encode %{ |
|
7905 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); |
|
7906 __ sradi($dst$$Register, $src$$Register, 0x3f); |
|
7907 %} |
|
7908 ins_pipe(pipe_class_default); |
|
7909 %} |
|
7910 |
|
7911 // Long negation |
|
7912 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ |
|
7913 match(Set dst (SubL zero src2)); |
|
7914 format %{ "NEG $dst, $src2 \t// long" %} |
|
7915 size(4); |
|
7916 ins_encode %{ |
|
7917 // TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7918 __ neg($dst$$Register, $src2$$Register); |
|
7919 %} |
|
7920 ins_pipe(pipe_class_default); |
|
7921 %} |
|
7922 |
|
7923 // NegL + ConvL2I. |
|
7924 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ |
|
7925 match(Set dst (ConvL2I (SubL zero src2))); |
|
7926 |
|
7927 format %{ "NEG $dst, $src2 \t// long + l2i" %} |
|
7928 size(4); |
|
7929 ins_encode %{ |
|
7930 // TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
7931 __ neg($dst$$Register, $src2$$Register); |
|
7932 %} |
|
7933 ins_pipe(pipe_class_default); |
|
7934 %} |
|
7935 |
|
7936 // Multiplication Instructions |
|
7937 // Integer Multiplication |
|
7938 |
|
7939 // Register Multiplication |
|
7940 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
7941 match(Set dst (MulI src1 src2)); |
|
7942 ins_cost(DEFAULT_COST); |
|
7943 |
|
7944 format %{ "MULLW $dst, $src1, $src2" %} |
|
7945 size(4); |
|
7946 ins_encode %{ |
|
7947 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); |
|
7948 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); |
|
7949 %} |
|
7950 ins_pipe(pipe_class_default); |
|
7951 %} |
|
7952 |
|
7953 // Immediate Multiplication |
|
7954 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ |
|
7955 match(Set dst (MulI src1 src2)); |
|
7956 ins_cost(DEFAULT_COST); |
|
7957 |
|
7958 format %{ "MULLI $dst, $src1, $src2" %} |
|
7959 size(4); |
|
7960 ins_encode %{ |
|
7961 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); |
|
7962 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); |
|
7963 %} |
|
7964 ins_pipe(pipe_class_default); |
|
7965 %} |
|
7966 |
|
7967 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7968 match(Set dst (MulL src1 src2)); |
|
7969 ins_cost(DEFAULT_COST); |
|
7970 |
|
7971 format %{ "MULLD $dst $src1, $src2 \t// long" %} |
|
7972 size(4); |
|
7973 ins_encode %{ |
|
7974 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); |
|
7975 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); |
|
7976 %} |
|
7977 ins_pipe(pipe_class_default); |
|
7978 %} |
|
7979 |
|
7980 // Multiply high for optimized long division by constant. |
|
7981 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
7982 match(Set dst (MulHiL src1 src2)); |
|
7983 ins_cost(DEFAULT_COST); |
|
7984 |
|
7985 format %{ "MULHD $dst $src1, $src2 \t// long" %} |
|
7986 size(4); |
|
7987 ins_encode %{ |
|
7988 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); |
|
7989 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); |
|
7990 %} |
|
7991 ins_pipe(pipe_class_default); |
|
7992 %} |
|
7993 |
|
7994 // Immediate Multiplication |
|
7995 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ |
|
7996 match(Set dst (MulL src1 src2)); |
|
7997 ins_cost(DEFAULT_COST); |
|
7998 |
|
7999 format %{ "MULLI $dst, $src1, $src2" %} |
|
8000 size(4); |
|
8001 ins_encode %{ |
|
8002 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); |
|
8003 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); |
|
8004 %} |
|
8005 ins_pipe(pipe_class_default); |
|
8006 %} |
|
8007 |
|
8008 // Integer Division with Immediate -1: Negate. |
|
8009 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ |
|
8010 match(Set dst (DivI src1 src2)); |
|
8011 ins_cost(DEFAULT_COST); |
|
8012 |
|
8013 format %{ "NEG $dst, $src1 \t// /-1" %} |
|
8014 size(4); |
|
8015 ins_encode %{ |
|
8016 // TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
8017 __ neg($dst$$Register, $src1$$Register); |
|
8018 %} |
|
8019 ins_pipe(pipe_class_default); |
|
8020 %} |
|
8021 |
|
8022 // Integer Division with constant, but not -1. |
|
8023 // We should be able to improve this by checking the type of src2. |
|
8024 // It might well be that src2 is known to be positive. |
|
8025 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8026 match(Set dst (DivI src1 src2)); |
|
8027 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 |
|
8028 ins_cost(2*DEFAULT_COST); |
|
8029 |
|
8030 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} |
|
8031 size(4); |
|
8032 ins_encode %{ |
|
8033 // TODO: PPC port $archOpcode(ppc64Opcode_divw); |
|
8034 __ divw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8035 %} |
|
8036 ins_pipe(pipe_class_default); |
|
8037 %} |
|
8038 |
|
8039 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{ |
|
8040 effect(USE_DEF dst, USE src1, USE crx); |
|
8041 predicate(false); |
|
8042 |
|
8043 ins_variable_size_depending_on_alignment(true); |
|
8044 |
|
8045 format %{ "CMOVE $dst, neg($src1), $crx" %} |
|
8046 // Worst case is branch + move + stop, no stop without scheduler. |
|
8047 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
8048 ins_encode %{ |
|
8049 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
8050 Label done; |
|
8051 __ bne($crx$$CondRegister, done); |
|
8052 __ neg($dst$$Register, $src1$$Register); |
|
8053 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
8054 __ bind(done); |
|
8055 %} |
|
8056 ins_pipe(pipe_class_default); |
|
8057 %} |
|
8058 |
|
8059 // Integer Division with Registers not containing constants. |
|
8060 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8061 match(Set dst (DivI src1 src2)); |
|
8062 ins_cost(10*DEFAULT_COST); |
|
8063 |
|
8064 expand %{ |
|
8065 immI16 imm %{ (int)-1 %} |
|
8066 flagsReg tmp1; |
|
8067 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8068 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 |
|
8069 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 |
|
8070 %} |
|
8071 %} |
|
8072 |
|
8073 // Long Division with Immediate -1: Negate. |
|
8074 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ |
|
8075 match(Set dst (DivL src1 src2)); |
|
8076 ins_cost(DEFAULT_COST); |
|
8077 |
|
8078 format %{ "NEG $dst, $src1 \t// /-1, long" %} |
|
8079 size(4); |
|
8080 ins_encode %{ |
|
8081 // TODO: PPC port $archOpcode(ppc64Opcode_neg); |
|
8082 __ neg($dst$$Register, $src1$$Register); |
|
8083 %} |
|
8084 ins_pipe(pipe_class_default); |
|
8085 %} |
|
8086 |
|
8087 // Long Division with constant, but not -1. |
|
8088 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
8089 match(Set dst (DivL src1 src2)); |
|
8090 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. |
|
8091 ins_cost(2*DEFAULT_COST); |
|
8092 |
|
8093 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} |
|
8094 size(4); |
|
8095 ins_encode %{ |
|
8096 // TODO: PPC port $archOpcode(ppc64Opcode_divd); |
|
8097 __ divd($dst$$Register, $src1$$Register, $src2$$Register); |
|
8098 %} |
|
8099 ins_pipe(pipe_class_default); |
|
8100 %} |
|
8101 |
|
8102 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{ |
|
8103 effect(USE_DEF dst, USE src1, USE crx); |
|
8104 predicate(false); |
|
8105 |
|
8106 ins_variable_size_depending_on_alignment(true); |
|
8107 |
|
8108 format %{ "CMOVE $dst, neg($src1), $crx" %} |
|
8109 // Worst case is branch + move + stop, no stop without scheduler. |
|
8110 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
8111 ins_encode %{ |
|
8112 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
8113 Label done; |
|
8114 __ bne($crx$$CondRegister, done); |
|
8115 __ neg($dst$$Register, $src1$$Register); |
|
8116 // TODO PPC port __ endgroup_if_needed(_size == 12); |
|
8117 __ bind(done); |
|
8118 %} |
|
8119 ins_pipe(pipe_class_default); |
|
8120 %} |
|
8121 |
|
8122 // Long Division with Registers not containing constants. |
|
8123 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
8124 match(Set dst (DivL src1 src2)); |
|
8125 ins_cost(10*DEFAULT_COST); |
|
8126 |
|
8127 expand %{ |
|
8128 immL16 imm %{ (int)-1 %} |
|
8129 flagsReg tmp1; |
|
8130 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8131 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 |
|
8132 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 |
|
8133 %} |
|
8134 %} |
|
8135 |
|
8136 // Integer Remainder with registers. |
|
8137 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8138 match(Set dst (ModI src1 src2)); |
|
8139 ins_cost(10*DEFAULT_COST); |
|
8140 |
|
8141 expand %{ |
|
8142 immI16 imm %{ (int)-1 %} |
|
8143 flagsReg tmp1; |
|
8144 iRegIdst tmp2; |
|
8145 iRegIdst tmp3; |
|
8146 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8147 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 |
|
8148 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 |
|
8149 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 |
|
8150 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 |
|
8151 %} |
|
8152 %} |
|
8153 |
|
8154 // Long Remainder with registers |
|
8155 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ |
|
8156 match(Set dst (ModL src1 src2)); |
|
8157 ins_cost(10*DEFAULT_COST); |
|
8158 |
|
8159 expand %{ |
|
8160 immL16 imm %{ (int)-1 %} |
|
8161 flagsReg tmp1; |
|
8162 iRegLdst tmp2; |
|
8163 iRegLdst tmp3; |
|
8164 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 |
|
8165 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 |
|
8166 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 |
|
8167 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 |
|
8168 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 |
|
8169 %} |
|
8170 %} |
|
8171 |
|
8172 // Integer Shift Instructions |
|
8173 |
|
8174 // Register Shift Left |
|
8175 |
|
8176 // Clear all but the lowest #mask bits. |
|
8177 // Used to normalize shift amounts in registers. |
|
8178 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ |
|
8179 // no match-rule, false predicate |
|
8180 effect(DEF dst, USE src, USE mask); |
|
8181 predicate(false); |
|
8182 |
|
8183 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} |
|
8184 size(4); |
|
8185 ins_encode %{ |
|
8186 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8187 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); |
|
8188 %} |
|
8189 ins_pipe(pipe_class_default); |
|
8190 %} |
|
8191 |
|
8192 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8193 // no match-rule, false predicate |
|
8194 effect(DEF dst, USE src1, USE src2); |
|
8195 predicate(false); |
|
8196 |
|
8197 format %{ "SLW $dst, $src1, $src2" %} |
|
8198 size(4); |
|
8199 ins_encode %{ |
|
8200 // TODO: PPC port $archOpcode(ppc64Opcode_slw); |
|
8201 __ slw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8202 %} |
|
8203 ins_pipe(pipe_class_default); |
|
8204 %} |
|
8205 |
|
8206 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8207 match(Set dst (LShiftI src1 src2)); |
|
8208 ins_cost(DEFAULT_COST*2); |
|
8209 expand %{ |
|
8210 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} |
|
8211 iRegIdst tmpI; |
|
8212 maskI_reg_imm(tmpI, src2, mask); |
|
8213 lShiftI_reg_reg(dst, src1, tmpI); |
|
8214 %} |
|
8215 %} |
|
8216 |
|
8217 // Register Shift Left Immediate |
|
8218 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ |
|
8219 match(Set dst (LShiftI src1 src2)); |
|
8220 |
|
8221 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} |
|
8222 size(4); |
|
8223 ins_encode %{ |
|
8224 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8225 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); |
|
8226 %} |
|
8227 ins_pipe(pipe_class_default); |
|
8228 %} |
|
8229 |
|
8230 // AndI with negpow2-constant + LShiftI |
|
8231 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ |
|
8232 match(Set dst (LShiftI (AndI src1 src2) src3)); |
|
8233 predicate(UseRotateAndMaskInstructionsPPC64); |
|
8234 |
|
8235 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} |
|
8236 size(4); |
|
8237 ins_encode %{ |
|
8238 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi |
|
8239 long src2 = $src2$$constant; |
|
8240 long src3 = $src3$$constant; |
|
8241 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); |
|
8242 if (maskbits >= 32) { |
|
8243 __ li($dst$$Register, 0); // addi |
|
8244 } else { |
|
8245 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); |
|
8246 } |
|
8247 %} |
|
8248 ins_pipe(pipe_class_default); |
|
8249 %} |
|
8250 |
|
8251 // RShiftI + AndI with negpow2-constant + LShiftI |
|
8252 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ |
|
8253 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); |
|
8254 predicate(UseRotateAndMaskInstructionsPPC64); |
|
8255 |
|
8256 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} |
|
8257 size(4); |
|
8258 ins_encode %{ |
|
8259 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi |
|
8260 long src2 = $src2$$constant; |
|
8261 long src3 = $src3$$constant; |
|
8262 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); |
|
8263 if (maskbits >= 32) { |
|
8264 __ li($dst$$Register, 0); // addi |
|
8265 } else { |
|
8266 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); |
|
8267 } |
|
8268 %} |
|
8269 ins_pipe(pipe_class_default); |
|
8270 %} |
|
8271 |
|
8272 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ |
|
8273 // no match-rule, false predicate |
|
8274 effect(DEF dst, USE src1, USE src2); |
|
8275 predicate(false); |
|
8276 |
|
8277 format %{ "SLD $dst, $src1, $src2" %} |
|
8278 size(4); |
|
8279 ins_encode %{ |
|
8280 // TODO: PPC port $archOpcode(ppc64Opcode_sld); |
|
8281 __ sld($dst$$Register, $src1$$Register, $src2$$Register); |
|
8282 %} |
|
8283 ins_pipe(pipe_class_default); |
|
8284 %} |
|
8285 |
|
8286 // Register Shift Left |
|
8287 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ |
|
8288 match(Set dst (LShiftL src1 src2)); |
|
8289 ins_cost(DEFAULT_COST*2); |
|
8290 expand %{ |
|
8291 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} |
|
8292 iRegIdst tmpI; |
|
8293 maskI_reg_imm(tmpI, src2, mask); |
|
8294 lShiftL_regL_regI(dst, src1, tmpI); |
|
8295 %} |
|
8296 %} |
|
8297 |
|
8298 // Register Shift Left Immediate |
|
8299 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ |
|
8300 match(Set dst (LShiftL src1 src2)); |
|
8301 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} |
|
8302 size(4); |
|
8303 ins_encode %{ |
|
8304 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8305 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8306 %} |
|
8307 ins_pipe(pipe_class_default); |
|
8308 %} |
|
8309 |
|
8310 // If we shift more than 32 bits, we need not convert I2L. |
|
8311 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ |
|
8312 match(Set dst (LShiftL (ConvI2L src1) src2)); |
|
8313 ins_cost(DEFAULT_COST); |
|
8314 |
|
8315 size(4); |
|
8316 format %{ "SLDI $dst, i2l($src1), $src2" %} |
|
8317 ins_encode %{ |
|
8318 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8319 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8320 %} |
|
8321 ins_pipe(pipe_class_default); |
|
8322 %} |
|
8323 |
|
8324 // Shift a postivie int to the left. |
|
8325 // Clrlsldi clears the upper 32 bits and shifts. |
|
8326 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ |
|
8327 match(Set dst (LShiftL (ConvI2L src1) src2)); |
|
8328 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); |
|
8329 |
|
8330 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} |
|
8331 size(4); |
|
8332 ins_encode %{ |
|
8333 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); |
|
8334 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); |
|
8335 %} |
|
8336 ins_pipe(pipe_class_default); |
|
8337 %} |
|
8338 |
|
8339 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8340 // no match-rule, false predicate |
|
8341 effect(DEF dst, USE src1, USE src2); |
|
8342 predicate(false); |
|
8343 |
|
8344 format %{ "SRAW $dst, $src1, $src2" %} |
|
8345 size(4); |
|
8346 ins_encode %{ |
|
8347 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); |
|
8348 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8349 %} |
|
8350 ins_pipe(pipe_class_default); |
|
8351 %} |
|
8352 |
|
8353 // Register Arithmetic Shift Right |
|
8354 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8355 match(Set dst (RShiftI src1 src2)); |
|
8356 ins_cost(DEFAULT_COST*2); |
|
8357 expand %{ |
|
8358 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} |
|
8359 iRegIdst tmpI; |
|
8360 maskI_reg_imm(tmpI, src2, mask); |
|
8361 arShiftI_reg_reg(dst, src1, tmpI); |
|
8362 %} |
|
8363 %} |
|
8364 |
|
8365 // Register Arithmetic Shift Right Immediate |
|
8366 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ |
|
8367 match(Set dst (RShiftI src1 src2)); |
|
8368 |
|
8369 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} |
|
8370 size(4); |
|
8371 ins_encode %{ |
|
8372 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); |
|
8373 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); |
|
8374 %} |
|
8375 ins_pipe(pipe_class_default); |
|
8376 %} |
|
8377 |
|
8378 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ |
|
8379 // no match-rule, false predicate |
|
8380 effect(DEF dst, USE src1, USE src2); |
|
8381 predicate(false); |
|
8382 |
|
8383 format %{ "SRAD $dst, $src1, $src2" %} |
|
8384 size(4); |
|
8385 ins_encode %{ |
|
8386 // TODO: PPC port $archOpcode(ppc64Opcode_srad); |
|
8387 __ srad($dst$$Register, $src1$$Register, $src2$$Register); |
|
8388 %} |
|
8389 ins_pipe(pipe_class_default); |
|
8390 %} |
|
8391 |
|
8392 // Register Shift Right Arithmetic Long |
|
8393 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ |
|
8394 match(Set dst (RShiftL src1 src2)); |
|
8395 ins_cost(DEFAULT_COST*2); |
|
8396 |
|
8397 expand %{ |
|
8398 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} |
|
8399 iRegIdst tmpI; |
|
8400 maskI_reg_imm(tmpI, src2, mask); |
|
8401 arShiftL_regL_regI(dst, src1, tmpI); |
|
8402 %} |
|
8403 %} |
|
8404 |
|
8405 // Register Shift Right Immediate |
|
8406 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ |
|
8407 match(Set dst (RShiftL src1 src2)); |
|
8408 |
|
8409 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} |
|
8410 size(4); |
|
8411 ins_encode %{ |
|
8412 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); |
|
8413 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8414 %} |
|
8415 ins_pipe(pipe_class_default); |
|
8416 %} |
|
8417 |
|
8418 // RShiftL + ConvL2I |
|
8419 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ |
|
8420 match(Set dst (ConvL2I (RShiftL src1 src2))); |
|
8421 |
|
8422 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} |
|
8423 size(4); |
|
8424 ins_encode %{ |
|
8425 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); |
|
8426 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8427 %} |
|
8428 ins_pipe(pipe_class_default); |
|
8429 %} |
|
8430 |
|
8431 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8432 // no match-rule, false predicate |
|
8433 effect(DEF dst, USE src1, USE src2); |
|
8434 predicate(false); |
|
8435 |
|
8436 format %{ "SRW $dst, $src1, $src2" %} |
|
8437 size(4); |
|
8438 ins_encode %{ |
|
8439 // TODO: PPC port $archOpcode(ppc64Opcode_srw); |
|
8440 __ srw($dst$$Register, $src1$$Register, $src2$$Register); |
|
8441 %} |
|
8442 ins_pipe(pipe_class_default); |
|
8443 %} |
|
8444 |
|
8445 // Register Shift Right |
|
8446 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8447 match(Set dst (URShiftI src1 src2)); |
|
8448 ins_cost(DEFAULT_COST*2); |
|
8449 |
|
8450 expand %{ |
|
8451 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} |
|
8452 iRegIdst tmpI; |
|
8453 maskI_reg_imm(tmpI, src2, mask); |
|
8454 urShiftI_reg_reg(dst, src1, tmpI); |
|
8455 %} |
|
8456 %} |
|
8457 |
|
8458 // Register Shift Right Immediate |
|
8459 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ |
|
8460 match(Set dst (URShiftI src1 src2)); |
|
8461 |
|
8462 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} |
|
8463 size(4); |
|
8464 ins_encode %{ |
|
8465 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8466 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); |
|
8467 %} |
|
8468 ins_pipe(pipe_class_default); |
|
8469 %} |
|
8470 |
|
8471 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ |
|
8472 // no match-rule, false predicate |
|
8473 effect(DEF dst, USE src1, USE src2); |
|
8474 predicate(false); |
|
8475 |
|
8476 format %{ "SRD $dst, $src1, $src2" %} |
|
8477 size(4); |
|
8478 ins_encode %{ |
|
8479 // TODO: PPC port $archOpcode(ppc64Opcode_srd); |
|
8480 __ srd($dst$$Register, $src1$$Register, $src2$$Register); |
|
8481 %} |
|
8482 ins_pipe(pipe_class_default); |
|
8483 %} |
|
8484 |
|
8485 // Register Shift Right |
|
8486 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ |
|
8487 match(Set dst (URShiftL src1 src2)); |
|
8488 ins_cost(DEFAULT_COST*2); |
|
8489 |
|
8490 expand %{ |
|
8491 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} |
|
8492 iRegIdst tmpI; |
|
8493 maskI_reg_imm(tmpI, src2, mask); |
|
8494 urShiftL_regL_regI(dst, src1, tmpI); |
|
8495 %} |
|
8496 %} |
|
8497 |
|
8498 // Register Shift Right Immediate |
|
8499 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ |
|
8500 match(Set dst (URShiftL src1 src2)); |
|
8501 |
|
8502 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} |
|
8503 size(4); |
|
8504 ins_encode %{ |
|
8505 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8506 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8507 %} |
|
8508 ins_pipe(pipe_class_default); |
|
8509 %} |
|
8510 |
|
8511 // URShiftL + ConvL2I. |
|
8512 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ |
|
8513 match(Set dst (ConvL2I (URShiftL src1 src2))); |
|
8514 |
|
8515 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} |
|
8516 size(4); |
|
8517 ins_encode %{ |
|
8518 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8519 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8520 %} |
|
8521 ins_pipe(pipe_class_default); |
|
8522 %} |
|
8523 |
|
8524 // Register Shift Right Immediate with a CastP2X |
|
8525 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ |
|
8526 match(Set dst (URShiftL (CastP2X src1) src2)); |
|
8527 |
|
8528 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} |
|
8529 size(4); |
|
8530 ins_encode %{ |
|
8531 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8532 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); |
|
8533 %} |
|
8534 ins_pipe(pipe_class_default); |
|
8535 %} |
|
8536 |
|
8537 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ |
|
8538 match(Set dst (ConvL2I (ConvI2L src))); |
|
8539 |
|
8540 format %{ "EXTSW $dst, $src \t// int->int" %} |
|
8541 size(4); |
|
8542 ins_encode %{ |
|
8543 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); |
|
8544 __ extsw($dst$$Register, $src$$Register); |
|
8545 %} |
|
8546 ins_pipe(pipe_class_default); |
|
8547 %} |
|
8548 |
|
8549 //----------Rotate Instructions------------------------------------------------ |
|
8550 |
|
8551 // Rotate Left by 8-bit immediate |
|
8552 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ |
|
8553 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); |
|
8554 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
8555 |
|
8556 format %{ "ROTLWI $dst, $src, $lshift" %} |
|
8557 size(4); |
|
8558 ins_encode %{ |
|
8559 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8560 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); |
|
8561 %} |
|
8562 ins_pipe(pipe_class_default); |
|
8563 %} |
|
8564 |
|
8565 // Rotate Right by 8-bit immediate |
|
8566 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ |
|
8567 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); |
|
8568 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
|
8569 |
|
8570 format %{ "ROTRWI $dst, $rshift" %} |
|
8571 size(4); |
|
8572 ins_encode %{ |
|
8573 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8574 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); |
|
8575 %} |
|
8576 ins_pipe(pipe_class_default); |
|
8577 %} |
|
8578 |
|
8579 //----------Floating Point Arithmetic Instructions----------------------------- |
|
8580 |
|
8581 // Add float single precision |
|
8582 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
8583 match(Set dst (AddF src1 src2)); |
|
8584 |
|
8585 format %{ "FADDS $dst, $src1, $src2" %} |
|
8586 size(4); |
|
8587 ins_encode %{ |
|
8588 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); |
|
8589 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8590 %} |
|
8591 ins_pipe(pipe_class_default); |
|
8592 %} |
|
8593 |
|
8594 // Add float double precision |
|
8595 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
8596 match(Set dst (AddD src1 src2)); |
|
8597 |
|
8598 format %{ "FADD $dst, $src1, $src2" %} |
|
8599 size(4); |
|
8600 ins_encode %{ |
|
8601 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); |
|
8602 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8603 %} |
|
8604 ins_pipe(pipe_class_default); |
|
8605 %} |
|
8606 |
|
8607 // Sub float single precision |
|
8608 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
8609 match(Set dst (SubF src1 src2)); |
|
8610 |
|
8611 format %{ "FSUBS $dst, $src1, $src2" %} |
|
8612 size(4); |
|
8613 ins_encode %{ |
|
8614 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); |
|
8615 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8616 %} |
|
8617 ins_pipe(pipe_class_default); |
|
8618 %} |
|
8619 |
|
8620 // Sub float double precision |
|
8621 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
8622 match(Set dst (SubD src1 src2)); |
|
8623 format %{ "FSUB $dst, $src1, $src2" %} |
|
8624 size(4); |
|
8625 ins_encode %{ |
|
8626 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); |
|
8627 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8628 %} |
|
8629 ins_pipe(pipe_class_default); |
|
8630 %} |
|
8631 |
|
8632 // Mul float single precision |
|
8633 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
8634 match(Set dst (MulF src1 src2)); |
|
8635 format %{ "FMULS $dst, $src1, $src2" %} |
|
8636 size(4); |
|
8637 ins_encode %{ |
|
8638 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); |
|
8639 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8640 %} |
|
8641 ins_pipe(pipe_class_default); |
|
8642 %} |
|
8643 |
|
8644 // Mul float double precision |
|
8645 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
8646 match(Set dst (MulD src1 src2)); |
|
8647 format %{ "FMUL $dst, $src1, $src2" %} |
|
8648 size(4); |
|
8649 ins_encode %{ |
|
8650 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); |
|
8651 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8652 %} |
|
8653 ins_pipe(pipe_class_default); |
|
8654 %} |
|
8655 |
|
8656 // Div float single precision |
|
8657 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ |
|
8658 match(Set dst (DivF src1 src2)); |
|
8659 format %{ "FDIVS $dst, $src1, $src2" %} |
|
8660 size(4); |
|
8661 ins_encode %{ |
|
8662 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); |
|
8663 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8664 %} |
|
8665 ins_pipe(pipe_class_default); |
|
8666 %} |
|
8667 |
|
8668 // Div float double precision |
|
8669 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ |
|
8670 match(Set dst (DivD src1 src2)); |
|
8671 format %{ "FDIV $dst, $src1, $src2" %} |
|
8672 size(4); |
|
8673 ins_encode %{ |
|
8674 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); |
|
8675 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
8676 %} |
|
8677 ins_pipe(pipe_class_default); |
|
8678 %} |
|
8679 |
|
8680 // Absolute float single precision |
|
8681 instruct absF_reg(regF dst, regF src) %{ |
|
8682 match(Set dst (AbsF src)); |
|
8683 format %{ "FABS $dst, $src \t// float" %} |
|
8684 size(4); |
|
8685 ins_encode %{ |
|
8686 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); |
|
8687 __ fabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8688 %} |
|
8689 ins_pipe(pipe_class_default); |
|
8690 %} |
|
8691 |
|
8692 // Absolute float double precision |
|
8693 instruct absD_reg(regD dst, regD src) %{ |
|
8694 match(Set dst (AbsD src)); |
|
8695 format %{ "FABS $dst, $src \t// double" %} |
|
8696 size(4); |
|
8697 ins_encode %{ |
|
8698 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); |
|
8699 __ fabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8700 %} |
|
8701 ins_pipe(pipe_class_default); |
|
8702 %} |
|
8703 |
|
8704 instruct negF_reg(regF dst, regF src) %{ |
|
8705 match(Set dst (NegF src)); |
|
8706 format %{ "FNEG $dst, $src \t// float" %} |
|
8707 size(4); |
|
8708 ins_encode %{ |
|
8709 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); |
|
8710 __ fneg($dst$$FloatRegister, $src$$FloatRegister); |
|
8711 %} |
|
8712 ins_pipe(pipe_class_default); |
|
8713 %} |
|
8714 |
|
8715 instruct negD_reg(regD dst, regD src) %{ |
|
8716 match(Set dst (NegD src)); |
|
8717 format %{ "FNEG $dst, $src \t// double" %} |
|
8718 size(4); |
|
8719 ins_encode %{ |
|
8720 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); |
|
8721 __ fneg($dst$$FloatRegister, $src$$FloatRegister); |
|
8722 %} |
|
8723 ins_pipe(pipe_class_default); |
|
8724 %} |
|
8725 |
|
8726 // AbsF + NegF. |
|
8727 instruct negF_absF_reg(regF dst, regF src) %{ |
|
8728 match(Set dst (NegF (AbsF src))); |
|
8729 format %{ "FNABS $dst, $src \t// float" %} |
|
8730 size(4); |
|
8731 ins_encode %{ |
|
8732 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); |
|
8733 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8734 %} |
|
8735 ins_pipe(pipe_class_default); |
|
8736 %} |
|
8737 |
|
8738 // AbsD + NegD. |
|
8739 instruct negD_absD_reg(regD dst, regD src) %{ |
|
8740 match(Set dst (NegD (AbsD src))); |
|
8741 format %{ "FNABS $dst, $src \t// double" %} |
|
8742 size(4); |
|
8743 ins_encode %{ |
|
8744 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); |
|
8745 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); |
|
8746 %} |
|
8747 ins_pipe(pipe_class_default); |
|
8748 %} |
|
8749 |
|
8750 // VM_Version::has_sqrt() decides if this node will be used. |
|
8751 // Sqrt float double precision |
|
8752 instruct sqrtD_reg(regD dst, regD src) %{ |
|
8753 match(Set dst (SqrtD src)); |
|
8754 format %{ "FSQRT $dst, $src" %} |
|
8755 size(4); |
|
8756 ins_encode %{ |
|
8757 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); |
|
8758 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); |
|
8759 %} |
|
8760 ins_pipe(pipe_class_default); |
|
8761 %} |
|
8762 |
|
8763 // Single-precision sqrt. |
|
8764 instruct sqrtF_reg(regF dst, regF src) %{ |
|
8765 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
8766 ins_cost(DEFAULT_COST); |
|
8767 |
|
8768 format %{ "FSQRTS $dst, $src" %} |
|
8769 size(4); |
|
8770 ins_encode %{ |
|
8771 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); |
|
8772 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); |
|
8773 %} |
|
8774 ins_pipe(pipe_class_default); |
|
8775 %} |
|
8776 |
|
8777 instruct roundDouble_nop(regD dst) %{ |
|
8778 match(Set dst (RoundDouble dst)); |
|
8779 ins_cost(0); |
|
8780 |
|
8781 format %{ " -- \t// RoundDouble not needed - empty" %} |
|
8782 size(0); |
|
8783 // PPC results are already "rounded" (i.e., normal-format IEEE). |
|
8784 ins_encode( /*empty*/ ); |
|
8785 ins_pipe(pipe_class_default); |
|
8786 %} |
|
8787 |
|
8788 instruct roundFloat_nop(regF dst) %{ |
|
8789 match(Set dst (RoundFloat dst)); |
|
8790 ins_cost(0); |
|
8791 |
|
8792 format %{ " -- \t// RoundFloat not needed - empty" %} |
|
8793 size(0); |
|
8794 // PPC results are already "rounded" (i.e., normal-format IEEE). |
|
8795 ins_encode( /*empty*/ ); |
|
8796 ins_pipe(pipe_class_default); |
|
8797 %} |
|
8798 |
|
8799 //----------Logical Instructions----------------------------------------------- |
|
8800 |
|
8801 // And Instructions |
|
8802 |
|
8803 // Register And |
|
8804 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8805 match(Set dst (AndI src1 src2)); |
|
8806 format %{ "AND $dst, $src1, $src2" %} |
|
8807 size(4); |
|
8808 ins_encode %{ |
|
8809 // TODO: PPC port $archOpcode(ppc64Opcode_and); |
|
8810 __ andr($dst$$Register, $src1$$Register, $src2$$Register); |
|
8811 %} |
|
8812 ins_pipe(pipe_class_default); |
|
8813 %} |
|
8814 |
|
8815 // Immediate And |
|
8816 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ |
|
8817 match(Set dst (AndI src1 src2)); |
|
8818 effect(KILL cr0); |
|
8819 |
|
8820 format %{ "ANDI $dst, $src1, $src2" %} |
|
8821 size(4); |
|
8822 ins_encode %{ |
|
8823 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
8824 // FIXME: avoid andi_ ? |
|
8825 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); |
|
8826 %} |
|
8827 ins_pipe(pipe_class_default); |
|
8828 %} |
|
8829 |
|
8830 // Immediate And where the immediate is a negative power of 2. |
|
8831 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ |
|
8832 match(Set dst (AndI src1 src2)); |
|
8833 format %{ "ANDWI $dst, $src1, $src2" %} |
|
8834 size(4); |
|
8835 ins_encode %{ |
|
8836 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8837 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); |
|
8838 %} |
|
8839 ins_pipe(pipe_class_default); |
|
8840 %} |
|
8841 |
|
8842 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ |
|
8843 match(Set dst (AndI src1 src2)); |
|
8844 format %{ "ANDWI $dst, $src1, $src2" %} |
|
8845 size(4); |
|
8846 ins_encode %{ |
|
8847 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8848 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); |
|
8849 %} |
|
8850 ins_pipe(pipe_class_default); |
|
8851 %} |
|
8852 |
|
8853 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ |
|
8854 match(Set dst (AndI src1 src2)); |
|
8855 predicate(UseRotateAndMaskInstructionsPPC64); |
|
8856 format %{ "ANDWI $dst, $src1, $src2" %} |
|
8857 size(4); |
|
8858 ins_encode %{ |
|
8859 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
8860 __ rlwinm($dst$$Register, $src1$$Register, 0, |
|
8861 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); |
|
8862 %} |
|
8863 ins_pipe(pipe_class_default); |
|
8864 %} |
|
8865 |
|
8866 // Register And Long |
|
8867 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
8868 match(Set dst (AndL src1 src2)); |
|
8869 ins_cost(DEFAULT_COST); |
|
8870 |
|
8871 format %{ "AND $dst, $src1, $src2 \t// long" %} |
|
8872 size(4); |
|
8873 ins_encode %{ |
|
8874 // TODO: PPC port $archOpcode(ppc64Opcode_and); |
|
8875 __ andr($dst$$Register, $src1$$Register, $src2$$Register); |
|
8876 %} |
|
8877 ins_pipe(pipe_class_default); |
|
8878 %} |
|
8879 |
|
8880 // Immediate And long |
|
8881 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ |
|
8882 match(Set dst (AndL src1 src2)); |
|
8883 effect(KILL cr0); |
|
8884 ins_cost(DEFAULT_COST); |
|
8885 |
|
8886 format %{ "ANDI $dst, $src1, $src2 \t// long" %} |
|
8887 size(4); |
|
8888 ins_encode %{ |
|
8889 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
8890 // FIXME: avoid andi_ ? |
|
8891 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); |
|
8892 %} |
|
8893 ins_pipe(pipe_class_default); |
|
8894 %} |
|
8895 |
|
8896 // Immediate And Long where the immediate is a negative power of 2. |
|
8897 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ |
|
8898 match(Set dst (AndL src1 src2)); |
|
8899 format %{ "ANDDI $dst, $src1, $src2" %} |
|
8900 size(4); |
|
8901 ins_encode %{ |
|
8902 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
8903 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); |
|
8904 %} |
|
8905 ins_pipe(pipe_class_default); |
|
8906 %} |
|
8907 |
|
8908 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ |
|
8909 match(Set dst (AndL src1 src2)); |
|
8910 format %{ "ANDDI $dst, $src1, $src2" %} |
|
8911 size(4); |
|
8912 ins_encode %{ |
|
8913 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8914 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); |
|
8915 %} |
|
8916 ins_pipe(pipe_class_default); |
|
8917 %} |
|
8918 |
|
8919 // AndL + ConvL2I. |
|
8920 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ |
|
8921 match(Set dst (ConvL2I (AndL src1 src2))); |
|
8922 ins_cost(DEFAULT_COST); |
|
8923 |
|
8924 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} |
|
8925 size(4); |
|
8926 ins_encode %{ |
|
8927 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
8928 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); |
|
8929 %} |
|
8930 ins_pipe(pipe_class_default); |
|
8931 %} |
|
8932 |
|
8933 // Or Instructions |
|
8934 |
|
8935 // Register Or |
|
8936 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8937 match(Set dst (OrI src1 src2)); |
|
8938 format %{ "OR $dst, $src1, $src2" %} |
|
8939 size(4); |
|
8940 ins_encode %{ |
|
8941 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8942 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8943 %} |
|
8944 ins_pipe(pipe_class_default); |
|
8945 %} |
|
8946 |
|
8947 // Expand does not work with above instruct. (??) |
|
8948 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
8949 // no match-rule |
|
8950 effect(DEF dst, USE src1, USE src2); |
|
8951 format %{ "OR $dst, $src1, $src2" %} |
|
8952 size(4); |
|
8953 ins_encode %{ |
|
8954 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8955 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8956 %} |
|
8957 ins_pipe(pipe_class_default); |
|
8958 %} |
|
8959 |
|
8960 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ |
|
8961 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); |
|
8962 ins_cost(DEFAULT_COST*3); |
|
8963 |
|
8964 expand %{ |
|
8965 // FIXME: we should do this in the ideal world. |
|
8966 iRegIdst tmp1; |
|
8967 iRegIdst tmp2; |
|
8968 orI_reg_reg(tmp1, src1, src2); |
|
8969 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. |
|
8970 orI_reg_reg(dst, tmp1, tmp2); |
|
8971 %} |
|
8972 %} |
|
8973 |
|
8974 // Immediate Or |
|
8975 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ |
|
8976 match(Set dst (OrI src1 src2)); |
|
8977 format %{ "ORI $dst, $src1, $src2" %} |
|
8978 size(4); |
|
8979 ins_encode %{ |
|
8980 // TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
8981 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); |
|
8982 %} |
|
8983 ins_pipe(pipe_class_default); |
|
8984 %} |
|
8985 |
|
8986 // Register Or Long |
|
8987 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
8988 match(Set dst (OrL src1 src2)); |
|
8989 ins_cost(DEFAULT_COST); |
|
8990 |
|
8991 size(4); |
|
8992 format %{ "OR $dst, $src1, $src2 \t// long" %} |
|
8993 ins_encode %{ |
|
8994 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
8995 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
8996 %} |
|
8997 ins_pipe(pipe_class_default); |
|
8998 %} |
|
8999 |
|
9000 // OrL + ConvL2I. |
|
9001 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
9002 match(Set dst (ConvL2I (OrL src1 src2))); |
|
9003 ins_cost(DEFAULT_COST); |
|
9004 |
|
9005 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} |
|
9006 size(4); |
|
9007 ins_encode %{ |
|
9008 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9009 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); |
|
9010 %} |
|
9011 ins_pipe(pipe_class_default); |
|
9012 %} |
|
9013 |
|
9014 // Immediate Or long |
|
9015 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ |
|
9016 match(Set dst (OrL src1 con)); |
|
9017 ins_cost(DEFAULT_COST); |
|
9018 |
|
9019 format %{ "ORI $dst, $src1, $con \t// long" %} |
|
9020 size(4); |
|
9021 ins_encode %{ |
|
9022 // TODO: PPC port $archOpcode(ppc64Opcode_ori); |
|
9023 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); |
|
9024 %} |
|
9025 ins_pipe(pipe_class_default); |
|
9026 %} |
|
9027 |
|
9028 // Xor Instructions |
|
9029 |
|
9030 // Register Xor |
|
9031 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
9032 match(Set dst (XorI src1 src2)); |
|
9033 format %{ "XOR $dst, $src1, $src2" %} |
|
9034 size(4); |
|
9035 ins_encode %{ |
|
9036 // TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9037 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9038 %} |
|
9039 ins_pipe(pipe_class_default); |
|
9040 %} |
|
9041 |
|
9042 // Expand does not work with above instruct. (??) |
|
9043 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
9044 // no match-rule |
|
9045 effect(DEF dst, USE src1, USE src2); |
|
9046 format %{ "XOR $dst, $src1, $src2" %} |
|
9047 size(4); |
|
9048 ins_encode %{ |
|
9049 // TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9050 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9051 %} |
|
9052 ins_pipe(pipe_class_default); |
|
9053 %} |
|
9054 |
|
9055 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ |
|
9056 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); |
|
9057 ins_cost(DEFAULT_COST*3); |
|
9058 |
|
9059 expand %{ |
|
9060 // FIXME: we should do this in the ideal world. |
|
9061 iRegIdst tmp1; |
|
9062 iRegIdst tmp2; |
|
9063 xorI_reg_reg(tmp1, src1, src2); |
|
9064 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. |
|
9065 xorI_reg_reg(dst, tmp1, tmp2); |
|
9066 %} |
|
9067 %} |
|
9068 |
|
9069 // Immediate Xor |
|
9070 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ |
|
9071 match(Set dst (XorI src1 src2)); |
|
9072 format %{ "XORI $dst, $src1, $src2" %} |
|
9073 size(4); |
|
9074 ins_encode %{ |
|
9075 // TODO: PPC port $archOpcode(ppc64Opcode_xori); |
|
9076 __ xori($dst$$Register, $src1$$Register, $src2$$constant); |
|
9077 %} |
|
9078 ins_pipe(pipe_class_default); |
|
9079 %} |
|
9080 |
|
9081 // Register Xor Long |
|
9082 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
9083 match(Set dst (XorL src1 src2)); |
|
9084 ins_cost(DEFAULT_COST); |
|
9085 |
|
9086 format %{ "XOR $dst, $src1, $src2 \t// long" %} |
|
9087 size(4); |
|
9088 ins_encode %{ |
|
9089 // TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9090 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9091 %} |
|
9092 ins_pipe(pipe_class_default); |
|
9093 %} |
|
9094 |
|
9095 // XorL + ConvL2I. |
|
9096 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
9097 match(Set dst (ConvL2I (XorL src1 src2))); |
|
9098 ins_cost(DEFAULT_COST); |
|
9099 |
|
9100 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} |
|
9101 size(4); |
|
9102 ins_encode %{ |
|
9103 // TODO: PPC port $archOpcode(ppc64Opcode_xor); |
|
9104 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); |
|
9105 %} |
|
9106 ins_pipe(pipe_class_default); |
|
9107 %} |
|
9108 |
|
9109 // Immediate Xor Long |
|
9110 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ |
|
9111 match(Set dst (XorL src1 src2)); |
|
9112 ins_cost(DEFAULT_COST); |
|
9113 |
|
9114 format %{ "XORI $dst, $src1, $src2 \t// long" %} |
|
9115 size(4); |
|
9116 ins_encode %{ |
|
9117 // TODO: PPC port $archOpcode(ppc64Opcode_xori); |
|
9118 __ xori($dst$$Register, $src1$$Register, $src2$$constant); |
|
9119 %} |
|
9120 ins_pipe(pipe_class_default); |
|
9121 %} |
|
9122 |
|
9123 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ |
|
9124 match(Set dst (XorI src1 src2)); |
|
9125 ins_cost(DEFAULT_COST); |
|
9126 |
|
9127 format %{ "NOT $dst, $src1 ($src2)" %} |
|
9128 size(4); |
|
9129 ins_encode %{ |
|
9130 // TODO: PPC port $archOpcode(ppc64Opcode_nor); |
|
9131 __ nor($dst$$Register, $src1$$Register, $src1$$Register); |
|
9132 %} |
|
9133 ins_pipe(pipe_class_default); |
|
9134 %} |
|
9135 |
|
9136 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ |
|
9137 match(Set dst (XorL src1 src2)); |
|
9138 ins_cost(DEFAULT_COST); |
|
9139 |
|
9140 format %{ "NOT $dst, $src1 ($src2) \t// long" %} |
|
9141 size(4); |
|
9142 ins_encode %{ |
|
9143 // TODO: PPC port $archOpcode(ppc64Opcode_nor); |
|
9144 __ nor($dst$$Register, $src1$$Register, $src1$$Register); |
|
9145 %} |
|
9146 ins_pipe(pipe_class_default); |
|
9147 %} |
|
9148 |
|
9149 // And-complement |
|
9150 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ |
|
9151 match(Set dst (AndI (XorI src1 src2) src3)); |
|
9152 ins_cost(DEFAULT_COST); |
|
9153 |
|
9154 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} |
|
9155 size(4); |
|
9156 ins_encode( enc_andc(dst, src3, src1) ); |
|
9157 ins_pipe(pipe_class_default); |
|
9158 %} |
|
9159 |
|
9160 // And-complement |
|
9161 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
9162 // no match-rule, false predicate |
|
9163 effect(DEF dst, USE src1, USE src2); |
|
9164 predicate(false); |
|
9165 |
|
9166 format %{ "ANDC $dst, $src1, $src2" %} |
|
9167 size(4); |
|
9168 ins_encode %{ |
|
9169 // TODO: PPC port $archOpcode(ppc64Opcode_andc); |
|
9170 __ andc($dst$$Register, $src1$$Register, $src2$$Register); |
|
9171 %} |
|
9172 ins_pipe(pipe_class_default); |
|
9173 %} |
|
9174 |
|
9175 //----------Moves between int/long and float/double---------------------------- |
|
9176 // |
|
9177 // The following rules move values from int/long registers/stack-locations |
|
9178 // to float/double registers/stack-locations and vice versa, without doing any |
|
9179 // conversions. These rules are used to implement the bit-conversion methods |
|
9180 // of java.lang.Float etc., e.g. |
|
9181 // int floatToIntBits(float value) |
|
9182 // float intBitsToFloat(int bits) |
|
9183 // |
|
9184 // Notes on the implementation on ppc64: |
|
9185 // We only provide rules which move between a register and a stack-location, |
|
9186 // because we always have to go through memory when moving between a float |
|
9187 // register and an integer register. |
|
9188 |
|
9189 //---------- Chain stack slots between similar types -------- |
|
9190 |
|
9191 // These are needed so that the rules below can match. |
|
9192 |
|
9193 // Load integer from stack slot |
|
9194 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ |
|
9195 match(Set dst src); |
|
9196 ins_cost(MEMORY_REF_COST); |
|
9197 |
|
9198 format %{ "LWZ $dst, $src" %} |
|
9199 size(4); |
|
9200 ins_encode( enc_lwz(dst, src) ); |
|
9201 ins_pipe(pipe_class_memory); |
|
9202 %} |
|
9203 |
|
9204 // Store integer to stack slot |
|
9205 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ |
|
9206 match(Set dst src); |
|
9207 ins_cost(MEMORY_REF_COST); |
|
9208 |
|
9209 format %{ "STW $src, $dst \t// stk" %} |
|
9210 size(4); |
|
9211 ins_encode( enc_stw(src, dst) ); // rs=rt |
|
9212 ins_pipe(pipe_class_memory); |
|
9213 %} |
|
9214 |
|
9215 // Load long from stack slot |
|
9216 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ |
|
9217 match(Set dst src); |
|
9218 ins_cost(MEMORY_REF_COST); |
|
9219 |
|
9220 format %{ "LD $dst, $src \t// long" %} |
|
9221 size(4); |
|
9222 ins_encode( enc_ld(dst, src) ); |
|
9223 ins_pipe(pipe_class_memory); |
|
9224 %} |
|
9225 |
|
9226 // Store long to stack slot |
|
9227 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ |
|
9228 match(Set dst src); |
|
9229 ins_cost(MEMORY_REF_COST); |
|
9230 |
|
9231 format %{ "STD $src, $dst \t// long" %} |
|
9232 size(4); |
|
9233 ins_encode( enc_std(src, dst) ); // rs=rt |
|
9234 ins_pipe(pipe_class_memory); |
|
9235 %} |
|
9236 |
|
9237 //----------Moves between int and float |
|
9238 |
|
9239 // Move float value from float stack-location to integer register. |
|
9240 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ |
|
9241 match(Set dst (MoveF2I src)); |
|
9242 ins_cost(MEMORY_REF_COST); |
|
9243 |
|
9244 format %{ "LWZ $dst, $src \t// MoveF2I" %} |
|
9245 size(4); |
|
9246 ins_encode( enc_lwz(dst, src) ); |
|
9247 ins_pipe(pipe_class_memory); |
|
9248 %} |
|
9249 |
|
9250 // Move float value from float register to integer stack-location. |
|
9251 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ |
|
9252 match(Set dst (MoveF2I src)); |
|
9253 ins_cost(MEMORY_REF_COST); |
|
9254 |
|
9255 format %{ "STFS $src, $dst \t// MoveF2I" %} |
|
9256 size(4); |
|
9257 ins_encode( enc_stfs(src, dst) ); |
|
9258 ins_pipe(pipe_class_memory); |
|
9259 %} |
|
9260 |
|
9261 // Move integer value from integer stack-location to float register. |
|
9262 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ |
|
9263 match(Set dst (MoveI2F src)); |
|
9264 ins_cost(MEMORY_REF_COST); |
|
9265 |
|
9266 format %{ "LFS $dst, $src \t// MoveI2F" %} |
|
9267 size(4); |
|
9268 ins_encode %{ |
|
9269 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); |
|
9270 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); |
|
9271 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); |
|
9272 %} |
|
9273 ins_pipe(pipe_class_memory); |
|
9274 %} |
|
9275 |
|
9276 // Move integer value from integer register to float stack-location. |
|
9277 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ |
|
9278 match(Set dst (MoveI2F src)); |
|
9279 ins_cost(MEMORY_REF_COST); |
|
9280 |
|
9281 format %{ "STW $src, $dst \t// MoveI2F" %} |
|
9282 size(4); |
|
9283 ins_encode( enc_stw(src, dst) ); |
|
9284 ins_pipe(pipe_class_memory); |
|
9285 %} |
|
9286 |
|
9287 //----------Moves between long and float |
|
9288 |
|
9289 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ |
|
9290 // no match-rule, false predicate |
|
9291 effect(DEF dst, USE src); |
|
9292 predicate(false); |
|
9293 |
|
9294 format %{ "storeD $src, $dst \t// STACK" %} |
|
9295 size(4); |
|
9296 ins_encode( enc_stfd(src, dst) ); |
|
9297 ins_pipe(pipe_class_default); |
|
9298 %} |
|
9299 |
|
9300 //----------Moves between long and double |
|
9301 |
|
9302 // Move double value from double stack-location to long register. |
|
9303 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ |
|
9304 match(Set dst (MoveD2L src)); |
|
9305 ins_cost(MEMORY_REF_COST); |
|
9306 size(4); |
|
9307 format %{ "LD $dst, $src \t// MoveD2L" %} |
|
9308 ins_encode( enc_ld(dst, src) ); |
|
9309 ins_pipe(pipe_class_memory); |
|
9310 %} |
|
9311 |
|
9312 // Move double value from double register to long stack-location. |
|
9313 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ |
|
9314 match(Set dst (MoveD2L src)); |
|
9315 effect(DEF dst, USE src); |
|
9316 ins_cost(MEMORY_REF_COST); |
|
9317 |
|
9318 format %{ "STFD $src, $dst \t// MoveD2L" %} |
|
9319 size(4); |
|
9320 ins_encode( enc_stfd(src, dst) ); |
|
9321 ins_pipe(pipe_class_memory); |
|
9322 %} |
|
9323 |
|
9324 // Move long value from long stack-location to double register. |
|
9325 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ |
|
9326 match(Set dst (MoveL2D src)); |
|
9327 ins_cost(MEMORY_REF_COST); |
|
9328 |
|
9329 format %{ "LFD $dst, $src \t// MoveL2D" %} |
|
9330 size(4); |
|
9331 ins_encode( enc_lfd(dst, src) ); |
|
9332 ins_pipe(pipe_class_memory); |
|
9333 %} |
|
9334 |
|
9335 // Move long value from long register to double stack-location. |
|
9336 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ |
|
9337 match(Set dst (MoveL2D src)); |
|
9338 ins_cost(MEMORY_REF_COST); |
|
9339 |
|
9340 format %{ "STD $src, $dst \t// MoveL2D" %} |
|
9341 size(4); |
|
9342 ins_encode( enc_std(src, dst) ); |
|
9343 ins_pipe(pipe_class_memory); |
|
9344 %} |
|
9345 |
|
9346 //----------Register Move Instructions----------------------------------------- |
|
9347 |
|
9348 // Replicate for Superword |
|
9349 |
|
9350 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ |
|
9351 predicate(false); |
|
9352 effect(DEF dst, USE src); |
|
9353 |
|
9354 format %{ "MR $dst, $src \t// replicate " %} |
|
9355 // variable size, 0 or 4. |
|
9356 ins_encode %{ |
|
9357 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9358 __ mr_if_needed($dst$$Register, $src$$Register); |
|
9359 %} |
|
9360 ins_pipe(pipe_class_default); |
|
9361 %} |
|
9362 |
|
9363 //----------Cast instructions (Java-level type cast)--------------------------- |
|
9364 |
|
9365 // Cast Long to Pointer for unsafe natives. |
|
9366 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ |
|
9367 match(Set dst (CastX2P src)); |
|
9368 |
|
9369 format %{ "MR $dst, $src \t// Long->Ptr" %} |
|
9370 // variable size, 0 or 4. |
|
9371 ins_encode %{ |
|
9372 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9373 __ mr_if_needed($dst$$Register, $src$$Register); |
|
9374 %} |
|
9375 ins_pipe(pipe_class_default); |
|
9376 %} |
|
9377 |
|
9378 // Cast Pointer to Long for unsafe natives. |
|
9379 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ |
|
9380 match(Set dst (CastP2X src)); |
|
9381 |
|
9382 format %{ "MR $dst, $src \t// Ptr->Long" %} |
|
9383 // variable size, 0 or 4. |
|
9384 ins_encode %{ |
|
9385 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9386 __ mr_if_needed($dst$$Register, $src$$Register); |
|
9387 %} |
|
9388 ins_pipe(pipe_class_default); |
|
9389 %} |
|
9390 |
|
9391 instruct castPP(iRegPdst dst) %{ |
|
9392 match(Set dst (CastPP dst)); |
|
9393 format %{ " -- \t// castPP of $dst" %} |
|
9394 size(0); |
|
9395 ins_encode( /*empty*/ ); |
|
9396 ins_pipe(pipe_class_default); |
|
9397 %} |
|
9398 |
|
9399 instruct castII(iRegIdst dst) %{ |
|
9400 match(Set dst (CastII dst)); |
|
9401 format %{ " -- \t// castII of $dst" %} |
|
9402 size(0); |
|
9403 ins_encode( /*empty*/ ); |
|
9404 ins_pipe(pipe_class_default); |
|
9405 %} |
|
9406 |
|
9407 instruct checkCastPP(iRegPdst dst) %{ |
|
9408 match(Set dst (CheckCastPP dst)); |
|
9409 format %{ " -- \t// checkcastPP of $dst" %} |
|
9410 size(0); |
|
9411 ins_encode( /*empty*/ ); |
|
9412 ins_pipe(pipe_class_default); |
|
9413 %} |
|
9414 |
|
9415 //----------Convert instructions----------------------------------------------- |
|
9416 |
|
9417 // Convert to boolean. |
|
9418 |
|
9419 // int_to_bool(src) : { 1 if src != 0 |
|
9420 // { 0 else |
|
9421 // |
|
9422 // strategy: |
|
9423 // 1) Count leading zeros of 32 bit-value src, |
|
9424 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. |
|
9425 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. |
|
9426 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. |
|
9427 |
|
9428 // convI2Bool |
|
9429 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ |
|
9430 match(Set dst (Conv2B src)); |
|
9431 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9432 ins_cost(DEFAULT_COST); |
|
9433 |
|
9434 expand %{ |
|
9435 immI shiftAmount %{ 0x5 %} |
|
9436 uimmI16 mask %{ 0x1 %} |
|
9437 iRegIdst tmp1; |
|
9438 iRegIdst tmp2; |
|
9439 countLeadingZerosI(tmp1, src); |
|
9440 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); |
|
9441 xorI_reg_uimm16(dst, tmp2, mask); |
|
9442 %} |
|
9443 %} |
|
9444 |
|
9445 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ |
|
9446 match(Set dst (Conv2B src)); |
|
9447 effect(TEMP crx); |
|
9448 predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9449 ins_cost(DEFAULT_COST); |
|
9450 |
|
9451 format %{ "CMPWI $crx, $src, #0 \t// convI2B" |
|
9452 "LI $dst, #0\n\t" |
|
9453 "BEQ $crx, done\n\t" |
|
9454 "LI $dst, #1\n" |
|
9455 "done:" %} |
|
9456 size(16); |
|
9457 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); |
|
9458 ins_pipe(pipe_class_compare); |
|
9459 %} |
|
9460 |
|
9461 // ConvI2B + XorI |
|
9462 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ |
|
9463 match(Set dst (XorI (Conv2B src) mask)); |
|
9464 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9465 ins_cost(DEFAULT_COST); |
|
9466 |
|
9467 expand %{ |
|
9468 immI shiftAmount %{ 0x5 %} |
|
9469 iRegIdst tmp1; |
|
9470 countLeadingZerosI(tmp1, src); |
|
9471 urShiftI_reg_imm(dst, tmp1, shiftAmount); |
|
9472 %} |
|
9473 %} |
|
9474 |
|
9475 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ |
|
9476 match(Set dst (XorI (Conv2B src) mask)); |
|
9477 effect(TEMP crx); |
|
9478 predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9479 ins_cost(DEFAULT_COST); |
|
9480 |
|
9481 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" |
|
9482 "LI $dst, #1\n\t" |
|
9483 "BEQ $crx, done\n\t" |
|
9484 "LI $dst, #0\n" |
|
9485 "done:" %} |
|
9486 size(16); |
|
9487 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); |
|
9488 ins_pipe(pipe_class_compare); |
|
9489 %} |
|
9490 |
|
9491 // AndI 0b0..010..0 + ConvI2B |
|
9492 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ |
|
9493 match(Set dst (Conv2B (AndI src mask))); |
|
9494 predicate(UseRotateAndMaskInstructionsPPC64); |
|
9495 ins_cost(DEFAULT_COST); |
|
9496 |
|
9497 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} |
|
9498 size(4); |
|
9499 ins_encode %{ |
|
9500 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); |
|
9501 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); |
|
9502 %} |
|
9503 ins_pipe(pipe_class_default); |
|
9504 %} |
|
9505 |
|
9506 // Convert pointer to boolean. |
|
9507 // |
|
9508 // ptr_to_bool(src) : { 1 if src != 0 |
|
9509 // { 0 else |
|
9510 // |
|
9511 // strategy: |
|
9512 // 1) Count leading zeros of 64 bit-value src, |
|
9513 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. |
|
9514 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. |
|
9515 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. |
|
9516 |
|
9517 // ConvP2B |
|
9518 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ |
|
9519 match(Set dst (Conv2B src)); |
|
9520 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9521 ins_cost(DEFAULT_COST); |
|
9522 |
|
9523 expand %{ |
|
9524 immI shiftAmount %{ 0x6 %} |
|
9525 uimmI16 mask %{ 0x1 %} |
|
9526 iRegIdst tmp1; |
|
9527 iRegIdst tmp2; |
|
9528 countLeadingZerosP(tmp1, src); |
|
9529 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); |
|
9530 xorI_reg_uimm16(dst, tmp2, mask); |
|
9531 %} |
|
9532 %} |
|
9533 |
|
9534 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ |
|
9535 match(Set dst (Conv2B src)); |
|
9536 effect(TEMP crx); |
|
9537 predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9538 ins_cost(DEFAULT_COST); |
|
9539 |
|
9540 format %{ "CMPDI $crx, $src, #0 \t// convP2B" |
|
9541 "LI $dst, #0\n\t" |
|
9542 "BEQ $crx, done\n\t" |
|
9543 "LI $dst, #1\n" |
|
9544 "done:" %} |
|
9545 size(16); |
|
9546 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); |
|
9547 ins_pipe(pipe_class_compare); |
|
9548 %} |
|
9549 |
|
9550 // ConvP2B + XorI |
|
9551 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ |
|
9552 match(Set dst (XorI (Conv2B src) mask)); |
|
9553 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
9554 ins_cost(DEFAULT_COST); |
|
9555 |
|
9556 expand %{ |
|
9557 immI shiftAmount %{ 0x6 %} |
|
9558 iRegIdst tmp1; |
|
9559 countLeadingZerosP(tmp1, src); |
|
9560 urShiftI_reg_imm(dst, tmp1, shiftAmount); |
|
9561 %} |
|
9562 %} |
|
9563 |
|
9564 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ |
|
9565 match(Set dst (XorI (Conv2B src) mask)); |
|
9566 effect(TEMP crx); |
|
9567 predicate(!UseCountLeadingZerosInstructionsPPC64); |
|
9568 ins_cost(DEFAULT_COST); |
|
9569 |
|
9570 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" |
|
9571 "LI $dst, #1\n\t" |
|
9572 "BEQ $crx, done\n\t" |
|
9573 "LI $dst, #0\n" |
|
9574 "done:" %} |
|
9575 size(16); |
|
9576 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); |
|
9577 ins_pipe(pipe_class_compare); |
|
9578 %} |
|
9579 |
|
9580 // if src1 < src2, return -1 else return 0 |
|
9581 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
9582 match(Set dst (CmpLTMask src1 src2)); |
|
9583 ins_cost(DEFAULT_COST*4); |
|
9584 |
|
9585 expand %{ |
|
9586 iRegIdst src1s; |
|
9587 iRegIdst src2s; |
|
9588 iRegIdst diff; |
|
9589 sxtI_reg(src1s, src1); // ensure proper sign extention |
|
9590 sxtI_reg(src2s, src2); // ensure proper sign extention |
|
9591 subI_reg_reg(diff, src1s, src2s); |
|
9592 // Need to consider >=33 bit result, therefore we need signmaskL. |
|
9593 signmask64I_regI(dst, diff); |
|
9594 %} |
|
9595 %} |
|
9596 |
|
9597 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ |
|
9598 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 |
|
9599 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} |
|
9600 size(4); |
|
9601 ins_encode %{ |
|
9602 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); |
|
9603 __ srawi($dst$$Register, $src1$$Register, 0x1f); |
|
9604 %} |
|
9605 ins_pipe(pipe_class_default); |
|
9606 %} |
|
9607 |
|
9608 //----------Arithmetic Conversion Instructions--------------------------------- |
|
9609 |
|
9610 // Convert to Byte -- nop |
|
9611 // Convert to Short -- nop |
|
9612 |
|
9613 // Convert to Int |
|
9614 |
|
9615 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ |
|
9616 match(Set dst (RShiftI (LShiftI src amount) amount)); |
|
9617 format %{ "EXTSB $dst, $src \t// byte->int" %} |
|
9618 size(4); |
|
9619 ins_encode %{ |
|
9620 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); |
|
9621 __ extsb($dst$$Register, $src$$Register); |
|
9622 %} |
|
9623 ins_pipe(pipe_class_default); |
|
9624 %} |
|
9625 |
|
9626 // LShiftI 16 + RShiftI 16 converts short to int. |
|
9627 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ |
|
9628 match(Set dst (RShiftI (LShiftI src amount) amount)); |
|
9629 format %{ "EXTSH $dst, $src \t// short->int" %} |
|
9630 size(4); |
|
9631 ins_encode %{ |
|
9632 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); |
|
9633 __ extsh($dst$$Register, $src$$Register); |
|
9634 %} |
|
9635 ins_pipe(pipe_class_default); |
|
9636 %} |
|
9637 |
|
9638 // ConvL2I + ConvI2L: Sign extend int in long register. |
|
9639 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ |
|
9640 match(Set dst (ConvI2L (ConvL2I src))); |
|
9641 |
|
9642 format %{ "EXTSW $dst, $src \t// long->long" %} |
|
9643 size(4); |
|
9644 ins_encode %{ |
|
9645 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); |
|
9646 __ extsw($dst$$Register, $src$$Register); |
|
9647 %} |
|
9648 ins_pipe(pipe_class_default); |
|
9649 %} |
|
9650 |
|
9651 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ |
|
9652 match(Set dst (ConvL2I src)); |
|
9653 format %{ "MR $dst, $src \t// long->int" %} |
|
9654 // variable size, 0 or 4 |
|
9655 ins_encode %{ |
|
9656 // TODO: PPC port $archOpcode(ppc64Opcode_or); |
|
9657 __ mr_if_needed($dst$$Register, $src$$Register); |
|
9658 %} |
|
9659 ins_pipe(pipe_class_default); |
|
9660 %} |
|
9661 |
|
9662 instruct convD2IRaw_regD(regD dst, regD src) %{ |
|
9663 // no match-rule, false predicate |
|
9664 effect(DEF dst, USE src); |
|
9665 predicate(false); |
|
9666 |
|
9667 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} |
|
9668 size(4); |
|
9669 ins_encode %{ |
|
9670 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; |
|
9671 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); |
|
9672 %} |
|
9673 ins_pipe(pipe_class_default); |
|
9674 %} |
|
9675 |
|
9676 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{ |
|
9677 // no match-rule, false predicate |
|
9678 effect(DEF dst, USE crx, USE src); |
|
9679 predicate(false); |
|
9680 |
|
9681 ins_variable_size_depending_on_alignment(true); |
|
9682 |
|
9683 format %{ "cmovI $crx, $dst, $src" %} |
|
9684 // Worst case is branch + move + stop, no stop without scheduler. |
|
9685 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); |
|
9686 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); |
|
9687 ins_pipe(pipe_class_default); |
|
9688 %} |
|
9689 |
|
9690 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{ |
|
9691 // no match-rule, false predicate |
|
9692 effect(DEF dst, USE crx, USE mem); |
|
9693 predicate(false); |
|
9694 |
|
9695 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} |
|
9696 postalloc_expand %{ |
|
9697 // |
|
9698 // replaces |
|
9699 // |
|
9700 // region dst crx mem |
|
9701 // \ | | / |
|
9702 // dst=cmovI_bso_stackSlotL_conLvalue0 |
|
9703 // |
|
9704 // with |
|
9705 // |
|
9706 // region dst |
|
9707 // \ / |
|
9708 // dst=loadConI16(0) |
|
9709 // | |
|
9710 // ^ region dst crx mem |
|
9711 // | \ | | / |
|
9712 // dst=cmovI_bso_stackSlotL |
|
9713 // |
|
9714 |
|
9715 // Create new nodes. |
|
9716 MachNode *m1 = new (C) loadConI16Node(); |
|
9717 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode(); |
|
9718 |
|
9719 // inputs for new nodes |
|
9720 m1->add_req(n_region); |
|
9721 m2->add_req(n_region, n_crx, n_mem); |
|
9722 |
|
9723 // precedences for new nodes |
|
9724 m2->add_prec(m1); |
|
9725 |
|
9726 // operands for new nodes |
|
9727 m1->_opnds[0] = op_dst; |
|
9728 m1->_opnds[1] = new (C) immI16Oper(0); |
|
9729 |
|
9730 m2->_opnds[0] = op_dst; |
|
9731 m2->_opnds[1] = op_crx; |
|
9732 m2->_opnds[2] = op_mem; |
|
9733 |
|
9734 // registers for new nodes |
|
9735 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9736 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9737 |
|
9738 // Insert new nodes. |
|
9739 nodes->push(m1); |
|
9740 nodes->push(m2); |
|
9741 %} |
|
9742 %} |
|
9743 |
|
9744 // Double to Int conversion, NaN is mapped to 0. |
|
9745 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ |
|
9746 match(Set dst (ConvD2I src)); |
|
9747 ins_cost(DEFAULT_COST); |
|
9748 |
|
9749 expand %{ |
|
9750 regD tmpD; |
|
9751 stackSlotL tmpS; |
|
9752 flagsReg crx; |
|
9753 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9754 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). |
|
9755 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). |
|
9756 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9757 %} |
|
9758 %} |
|
9759 |
|
9760 instruct convF2IRaw_regF(regF dst, regF src) %{ |
|
9761 // no match-rule, false predicate |
|
9762 effect(DEF dst, USE src); |
|
9763 predicate(false); |
|
9764 |
|
9765 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} |
|
9766 size(4); |
|
9767 ins_encode %{ |
|
9768 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); |
|
9769 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); |
|
9770 %} |
|
9771 ins_pipe(pipe_class_default); |
|
9772 %} |
|
9773 |
|
9774 // Float to Int conversion, NaN is mapped to 0. |
|
9775 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ |
|
9776 match(Set dst (ConvF2I src)); |
|
9777 ins_cost(DEFAULT_COST); |
|
9778 |
|
9779 expand %{ |
|
9780 regF tmpF; |
|
9781 stackSlotL tmpS; |
|
9782 flagsReg crx; |
|
9783 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9784 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). |
|
9785 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). |
|
9786 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9787 %} |
|
9788 %} |
|
9789 |
|
9790 // Convert to Long |
|
9791 |
|
9792 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ |
|
9793 match(Set dst (ConvI2L src)); |
|
9794 format %{ "EXTSW $dst, $src \t// int->long" %} |
|
9795 size(4); |
|
9796 ins_encode %{ |
|
9797 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); |
|
9798 __ extsw($dst$$Register, $src$$Register); |
|
9799 %} |
|
9800 ins_pipe(pipe_class_default); |
|
9801 %} |
|
9802 |
|
9803 // Zero-extend: convert unsigned int to long (convUI2L). |
|
9804 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ |
|
9805 match(Set dst (AndL (ConvI2L src) mask)); |
|
9806 ins_cost(DEFAULT_COST); |
|
9807 |
|
9808 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} |
|
9809 size(4); |
|
9810 ins_encode %{ |
|
9811 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
9812 __ clrldi($dst$$Register, $src$$Register, 32); |
|
9813 %} |
|
9814 ins_pipe(pipe_class_default); |
|
9815 %} |
|
9816 |
|
9817 // Zero-extend: convert unsigned int to long in long register. |
|
9818 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ |
|
9819 match(Set dst (AndL src mask)); |
|
9820 ins_cost(DEFAULT_COST); |
|
9821 |
|
9822 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} |
|
9823 size(4); |
|
9824 ins_encode %{ |
|
9825 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); |
|
9826 __ clrldi($dst$$Register, $src$$Register, 32); |
|
9827 %} |
|
9828 ins_pipe(pipe_class_default); |
|
9829 %} |
|
9830 |
|
9831 instruct convF2LRaw_regF(regF dst, regF src) %{ |
|
9832 // no match-rule, false predicate |
|
9833 effect(DEF dst, USE src); |
|
9834 predicate(false); |
|
9835 |
|
9836 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} |
|
9837 size(4); |
|
9838 ins_encode %{ |
|
9839 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); |
|
9840 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); |
|
9841 %} |
|
9842 ins_pipe(pipe_class_default); |
|
9843 %} |
|
9844 |
|
9845 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{ |
|
9846 // no match-rule, false predicate |
|
9847 effect(DEF dst, USE crx, USE src); |
|
9848 predicate(false); |
|
9849 |
|
9850 ins_variable_size_depending_on_alignment(true); |
|
9851 |
|
9852 format %{ "cmovL $crx, $dst, $src" %} |
|
9853 // Worst case is branch + move + stop, no stop without scheduler. |
|
9854 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); |
|
9855 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); |
|
9856 ins_pipe(pipe_class_default); |
|
9857 %} |
|
9858 |
|
9859 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{ |
|
9860 // no match-rule, false predicate |
|
9861 effect(DEF dst, USE crx, USE mem); |
|
9862 predicate(false); |
|
9863 |
|
9864 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} |
|
9865 postalloc_expand %{ |
|
9866 // |
|
9867 // replaces |
|
9868 // |
|
9869 // region dst crx mem |
|
9870 // \ | | / |
|
9871 // dst=cmovL_bso_stackSlotL_conLvalue0 |
|
9872 // |
|
9873 // with |
|
9874 // |
|
9875 // region dst |
|
9876 // \ / |
|
9877 // dst=loadConL16(0) |
|
9878 // | |
|
9879 // ^ region dst crx mem |
|
9880 // | \ | | / |
|
9881 // dst=cmovL_bso_stackSlotL |
|
9882 // |
|
9883 |
|
9884 // Create new nodes. |
|
9885 MachNode *m1 = new (C) loadConL16Node(); |
|
9886 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode(); |
|
9887 |
|
9888 // inputs for new nodes |
|
9889 m1->add_req(n_region); |
|
9890 m2->add_req(n_region, n_crx, n_mem); |
|
9891 m2->add_prec(m1); |
|
9892 |
|
9893 // operands for new nodes |
|
9894 m1->_opnds[0] = op_dst; |
|
9895 m1->_opnds[1] = new (C) immL16Oper(0); |
|
9896 m2->_opnds[0] = op_dst; |
|
9897 m2->_opnds[1] = op_crx; |
|
9898 m2->_opnds[2] = op_mem; |
|
9899 |
|
9900 // registers for new nodes |
|
9901 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9902 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
9903 |
|
9904 // Insert new nodes. |
|
9905 nodes->push(m1); |
|
9906 nodes->push(m2); |
|
9907 %} |
|
9908 %} |
|
9909 |
|
9910 // Float to Long conversion, NaN is mapped to 0. |
|
9911 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ |
|
9912 match(Set dst (ConvF2L src)); |
|
9913 ins_cost(DEFAULT_COST); |
|
9914 |
|
9915 expand %{ |
|
9916 regF tmpF; |
|
9917 stackSlotL tmpS; |
|
9918 flagsReg crx; |
|
9919 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9920 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). |
|
9921 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). |
|
9922 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9923 %} |
|
9924 %} |
|
9925 |
|
9926 instruct convD2LRaw_regD(regD dst, regD src) %{ |
|
9927 // no match-rule, false predicate |
|
9928 effect(DEF dst, USE src); |
|
9929 predicate(false); |
|
9930 |
|
9931 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} |
|
9932 size(4); |
|
9933 ins_encode %{ |
|
9934 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); |
|
9935 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); |
|
9936 %} |
|
9937 ins_pipe(pipe_class_default); |
|
9938 %} |
|
9939 |
|
9940 // Double to Long conversion, NaN is mapped to 0. |
|
9941 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ |
|
9942 match(Set dst (ConvD2L src)); |
|
9943 ins_cost(DEFAULT_COST); |
|
9944 |
|
9945 expand %{ |
|
9946 regD tmpD; |
|
9947 stackSlotL tmpS; |
|
9948 flagsReg crx; |
|
9949 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. |
|
9950 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). |
|
9951 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). |
|
9952 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. |
|
9953 %} |
|
9954 %} |
|
9955 |
|
9956 // Convert to Float |
|
9957 |
|
9958 // Placed here as needed in expand. |
|
9959 instruct convL2DRaw_regD(regD dst, regD src) %{ |
|
9960 // no match-rule, false predicate |
|
9961 effect(DEF dst, USE src); |
|
9962 predicate(false); |
|
9963 |
|
9964 format %{ "FCFID $dst, $src \t// convL2D" %} |
|
9965 size(4); |
|
9966 ins_encode %{ |
|
9967 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); |
|
9968 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); |
|
9969 %} |
|
9970 ins_pipe(pipe_class_default); |
|
9971 %} |
|
9972 |
|
9973 // Placed here as needed in expand. |
|
9974 instruct convD2F_reg(regF dst, regD src) %{ |
|
9975 match(Set dst (ConvD2F src)); |
|
9976 format %{ "FRSP $dst, $src \t// convD2F" %} |
|
9977 size(4); |
|
9978 ins_encode %{ |
|
9979 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); |
|
9980 __ frsp($dst$$FloatRegister, $src$$FloatRegister); |
|
9981 %} |
|
9982 ins_pipe(pipe_class_default); |
|
9983 %} |
|
9984 |
|
9985 // Integer to Float conversion. |
|
9986 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ |
|
9987 match(Set dst (ConvI2F src)); |
|
9988 predicate(!VM_Version::has_fcfids()); |
|
9989 ins_cost(DEFAULT_COST); |
|
9990 |
|
9991 expand %{ |
|
9992 iRegLdst tmpL; |
|
9993 stackSlotL tmpS; |
|
9994 regD tmpD; |
|
9995 regD tmpD2; |
|
9996 convI2L_reg(tmpL, src); // Sign-extension int to long. |
|
9997 regL_to_stkL(tmpS, tmpL); // Store long to stack. |
|
9998 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
9999 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. |
|
10000 convD2F_reg(dst, tmpD2); // Convert double to float. |
|
10001 %} |
|
10002 %} |
|
10003 |
|
10004 instruct convL2FRaw_regF(regF dst, regD src) %{ |
|
10005 // no match-rule, false predicate |
|
10006 effect(DEF dst, USE src); |
|
10007 predicate(false); |
|
10008 |
|
10009 format %{ "FCFIDS $dst, $src \t// convL2F" %} |
|
10010 size(4); |
|
10011 ins_encode %{ |
|
10012 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); |
|
10013 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); |
|
10014 %} |
|
10015 ins_pipe(pipe_class_default); |
|
10016 %} |
|
10017 |
|
10018 // Integer to Float conversion. Special version for Power7. |
|
10019 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ |
|
10020 match(Set dst (ConvI2F src)); |
|
10021 predicate(VM_Version::has_fcfids()); |
|
10022 ins_cost(DEFAULT_COST); |
|
10023 |
|
10024 expand %{ |
|
10025 iRegLdst tmpL; |
|
10026 stackSlotL tmpS; |
|
10027 regD tmpD; |
|
10028 convI2L_reg(tmpL, src); // Sign-extension int to long. |
|
10029 regL_to_stkL(tmpS, tmpL); // Store long to stack. |
|
10030 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
10031 convL2FRaw_regF(dst, tmpD); // Convert to float. |
|
10032 %} |
|
10033 %} |
|
10034 |
|
10035 // L2F to avoid runtime call. |
|
10036 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ |
|
10037 match(Set dst (ConvL2F src)); |
|
10038 predicate(VM_Version::has_fcfids()); |
|
10039 ins_cost(DEFAULT_COST); |
|
10040 |
|
10041 expand %{ |
|
10042 stackSlotL tmpS; |
|
10043 regD tmpD; |
|
10044 regL_to_stkL(tmpS, src); // Store long to stack. |
|
10045 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
10046 convL2FRaw_regF(dst, tmpD); // Convert to float. |
|
10047 %} |
|
10048 %} |
|
10049 |
|
10050 // Moved up as used in expand. |
|
10051 //instruct convD2F_reg(regF dst, regD src) %{%} |
|
10052 |
|
10053 // Convert to Double |
|
10054 |
|
10055 // Integer to Double conversion. |
|
10056 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ |
|
10057 match(Set dst (ConvI2D src)); |
|
10058 ins_cost(DEFAULT_COST); |
|
10059 |
|
10060 expand %{ |
|
10061 iRegLdst tmpL; |
|
10062 stackSlotL tmpS; |
|
10063 regD tmpD; |
|
10064 convI2L_reg(tmpL, src); // Sign-extension int to long. |
|
10065 regL_to_stkL(tmpS, tmpL); // Store long to stack. |
|
10066 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. |
|
10067 convL2DRaw_regD(dst, tmpD); // Convert to double. |
|
10068 %} |
|
10069 %} |
|
10070 |
|
10071 // Long to Double conversion |
|
10072 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ |
|
10073 match(Set dst (ConvL2D src)); |
|
10074 ins_cost(DEFAULT_COST + MEMORY_REF_COST); |
|
10075 |
|
10076 expand %{ |
|
10077 regD tmpD; |
|
10078 moveL2D_stack_reg(tmpD, src); |
|
10079 convL2DRaw_regD(dst, tmpD); |
|
10080 %} |
|
10081 %} |
|
10082 |
|
10083 instruct convF2D_reg(regD dst, regF src) %{ |
|
10084 match(Set dst (ConvF2D src)); |
|
10085 format %{ "FMR $dst, $src \t// float->double" %} |
|
10086 // variable size, 0 or 4 |
|
10087 ins_encode %{ |
|
10088 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
10089 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); |
|
10090 %} |
|
10091 ins_pipe(pipe_class_default); |
|
10092 %} |
|
10093 |
|
10094 //----------Control Flow Instructions------------------------------------------ |
|
10095 // Compare Instructions |
|
10096 |
|
10097 // Compare Integers |
|
10098 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ |
|
10099 match(Set crx (CmpI src1 src2)); |
|
10100 size(4); |
|
10101 format %{ "CMPW $crx, $src1, $src2" %} |
|
10102 ins_encode %{ |
|
10103 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); |
|
10104 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10105 %} |
|
10106 ins_pipe(pipe_class_compare); |
|
10107 %} |
|
10108 |
|
10109 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ |
|
10110 match(Set crx (CmpI src1 src2)); |
|
10111 format %{ "CMPWI $crx, $src1, $src2" %} |
|
10112 size(4); |
|
10113 ins_encode %{ |
|
10114 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); |
|
10115 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10116 %} |
|
10117 ins_pipe(pipe_class_compare); |
|
10118 %} |
|
10119 |
|
10120 // (src1 & src2) == 0? |
|
10121 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ |
|
10122 match(Set cr0 (CmpI (AndI src1 src2) zero)); |
|
10123 // r0 is killed |
|
10124 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} |
|
10125 size(4); |
|
10126 ins_encode %{ |
|
10127 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
10128 // FIXME: avoid andi_ ? |
|
10129 __ andi_(R0, $src1$$Register, $src2$$constant); |
|
10130 %} |
|
10131 ins_pipe(pipe_class_compare); |
|
10132 %} |
|
10133 |
|
10134 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ |
|
10135 match(Set crx (CmpL src1 src2)); |
|
10136 format %{ "CMPD $crx, $src1, $src2" %} |
|
10137 size(4); |
|
10138 ins_encode %{ |
|
10139 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); |
|
10140 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10141 %} |
|
10142 ins_pipe(pipe_class_compare); |
|
10143 %} |
|
10144 |
|
10145 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ |
|
10146 match(Set crx (CmpL src1 src2)); |
|
10147 format %{ "CMPDI $crx, $src1, $src2" %} |
|
10148 size(4); |
|
10149 ins_encode %{ |
|
10150 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); |
|
10151 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10152 %} |
|
10153 ins_pipe(pipe_class_compare); |
|
10154 %} |
|
10155 |
|
10156 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ |
|
10157 match(Set cr0 (CmpL (AndL src1 src2) zero)); |
|
10158 // r0 is killed |
|
10159 format %{ "AND R0, $src1, $src2 \t// BTST long" %} |
|
10160 size(4); |
|
10161 ins_encode %{ |
|
10162 // TODO: PPC port $archOpcode(ppc64Opcode_and_); |
|
10163 __ and_(R0, $src1$$Register, $src2$$Register); |
|
10164 %} |
|
10165 ins_pipe(pipe_class_compare); |
|
10166 %} |
|
10167 |
|
10168 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ |
|
10169 match(Set cr0 (CmpL (AndL src1 src2) zero)); |
|
10170 // r0 is killed |
|
10171 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} |
|
10172 size(4); |
|
10173 ins_encode %{ |
|
10174 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); |
|
10175 // FIXME: avoid andi_ ? |
|
10176 __ andi_(R0, $src1$$Register, $src2$$constant); |
|
10177 %} |
|
10178 ins_pipe(pipe_class_compare); |
|
10179 %} |
|
10180 |
|
10181 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{ |
|
10182 // no match-rule, false predicate |
|
10183 effect(DEF dst, USE crx); |
|
10184 predicate(false); |
|
10185 |
|
10186 ins_variable_size_depending_on_alignment(true); |
|
10187 |
|
10188 format %{ "cmovI $crx, $dst, -1, 0, +1" %} |
|
10189 // Worst case is branch + move + branch + move + stop, no stop without scheduler. |
|
10190 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); |
|
10191 ins_encode %{ |
|
10192 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); |
|
10193 Label done; |
|
10194 // li(Rdst, 0); // equal -> 0 |
|
10195 __ beq($crx$$CondRegister, done); |
|
10196 __ li($dst$$Register, 1); // greater -> +1 |
|
10197 __ bgt($crx$$CondRegister, done); |
|
10198 __ li($dst$$Register, -1); // unordered or less -> -1 |
|
10199 // TODO: PPC port__ endgroup_if_needed(_size == 20); |
|
10200 __ bind(done); |
|
10201 %} |
|
10202 ins_pipe(pipe_class_compare); |
|
10203 %} |
|
10204 |
|
10205 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{ |
|
10206 // no match-rule, false predicate |
|
10207 effect(DEF dst, USE crx); |
|
10208 predicate(false); |
|
10209 |
|
10210 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} |
|
10211 postalloc_expand %{ |
|
10212 // |
|
10213 // replaces |
|
10214 // |
|
10215 // region crx |
|
10216 // \ | |
|
10217 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 |
|
10218 // |
|
10219 // with |
|
10220 // |
|
10221 // region |
|
10222 // \ |
|
10223 // dst=loadConI16(0) |
|
10224 // | |
|
10225 // ^ region crx |
|
10226 // | \ | |
|
10227 // dst=cmovI_conIvalueMinus1_conIvalue1 |
|
10228 // |
|
10229 |
|
10230 // Create new nodes. |
|
10231 MachNode *m1 = new (C) loadConI16Node(); |
|
10232 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node(); |
|
10233 |
|
10234 // inputs for new nodes |
|
10235 m1->add_req(n_region); |
|
10236 m2->add_req(n_region, n_crx); |
|
10237 m2->add_prec(m1); |
|
10238 |
|
10239 // operands for new nodes |
|
10240 m1->_opnds[0] = op_dst; |
|
10241 m1->_opnds[1] = new (C) immI16Oper(0); |
|
10242 m2->_opnds[0] = op_dst; |
|
10243 m2->_opnds[1] = op_crx; |
|
10244 |
|
10245 // registers for new nodes |
|
10246 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
10247 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst |
|
10248 |
|
10249 // Insert new nodes. |
|
10250 nodes->push(m1); |
|
10251 nodes->push(m2); |
|
10252 %} |
|
10253 %} |
|
10254 |
|
10255 // Manifest a CmpL3 result in an integer register. Very painful. |
|
10256 // This is the test to avoid. |
|
10257 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) |
|
10258 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ |
|
10259 match(Set dst (CmpL3 src1 src2)); |
|
10260 ins_cost(DEFAULT_COST*5+BRANCH_COST); |
|
10261 |
|
10262 expand %{ |
|
10263 flagsReg tmp1; |
|
10264 cmpL_reg_reg(tmp1, src1, src2); |
|
10265 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); |
|
10266 %} |
|
10267 %} |
|
10268 |
|
10269 // Implicit range checks. |
|
10270 // A range check in the ideal world has one of the following shapes: |
|
10271 // - (If le (CmpU length index)), (IfTrue throw exception) |
|
10272 // - (If lt (CmpU index length)), (IfFalse throw exception) |
|
10273 // |
|
10274 // Match range check 'If le (CmpU length index)'. |
|
10275 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ |
|
10276 match(If cmp (CmpU src_length index)); |
|
10277 effect(USE labl); |
|
10278 predicate(TrapBasedRangeChecks && |
|
10279 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && |
|
10280 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && |
|
10281 (Matcher::branches_to_uncommon_trap(_leaf))); |
|
10282 |
|
10283 ins_is_TrapBasedCheckNode(true); |
|
10284 |
|
10285 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} |
|
10286 size(4); |
|
10287 ins_encode %{ |
|
10288 // TODO: PPC port $archOpcode(ppc64Opcode_twi); |
|
10289 if ($cmp$$cmpcode == 0x1 /* less_equal */) { |
|
10290 __ trap_range_check_le($src_length$$Register, $index$$constant); |
|
10291 } else { |
|
10292 // Both successors are uncommon traps, probability is 0. |
|
10293 // Node got flipped during fixup flow. |
|
10294 assert($cmp$$cmpcode == 0x9, "must be greater"); |
|
10295 __ trap_range_check_g($src_length$$Register, $index$$constant); |
|
10296 } |
|
10297 %} |
|
10298 ins_pipe(pipe_class_trap); |
|
10299 %} |
|
10300 |
|
10301 // Match range check 'If lt (CmpU index length)'. |
|
10302 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ |
|
10303 match(If cmp (CmpU src_index src_length)); |
|
10304 effect(USE labl); |
|
10305 predicate(TrapBasedRangeChecks && |
|
10306 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && |
|
10307 _leaf->as_If()->_prob >= PROB_ALWAYS && |
|
10308 (Matcher::branches_to_uncommon_trap(_leaf))); |
|
10309 |
|
10310 ins_is_TrapBasedCheckNode(true); |
|
10311 |
|
10312 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} |
|
10313 size(4); |
|
10314 ins_encode %{ |
|
10315 // TODO: PPC port $archOpcode(ppc64Opcode_tw); |
|
10316 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { |
|
10317 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); |
|
10318 } else { |
|
10319 // Both successors are uncommon traps, probability is 0. |
|
10320 // Node got flipped during fixup flow. |
|
10321 assert($cmp$$cmpcode == 0x8, "must be less"); |
|
10322 __ trap_range_check_l($src_index$$Register, $src_length$$Register); |
|
10323 } |
|
10324 %} |
|
10325 ins_pipe(pipe_class_trap); |
|
10326 %} |
|
10327 |
|
10328 // Match range check 'If lt (CmpU index length)'. |
|
10329 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ |
|
10330 match(If cmp (CmpU src_index length)); |
|
10331 effect(USE labl); |
|
10332 predicate(TrapBasedRangeChecks && |
|
10333 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && |
|
10334 _leaf->as_If()->_prob >= PROB_ALWAYS && |
|
10335 (Matcher::branches_to_uncommon_trap(_leaf))); |
|
10336 |
|
10337 ins_is_TrapBasedCheckNode(true); |
|
10338 |
|
10339 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} |
|
10340 size(4); |
|
10341 ins_encode %{ |
|
10342 // TODO: PPC port $archOpcode(ppc64Opcode_twi); |
|
10343 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { |
|
10344 __ trap_range_check_ge($src_index$$Register, $length$$constant); |
|
10345 } else { |
|
10346 // Both successors are uncommon traps, probability is 0. |
|
10347 // Node got flipped during fixup flow. |
|
10348 assert($cmp$$cmpcode == 0x8, "must be less"); |
|
10349 __ trap_range_check_l($src_index$$Register, $length$$constant); |
|
10350 } |
|
10351 %} |
|
10352 ins_pipe(pipe_class_trap); |
|
10353 %} |
|
10354 |
|
10355 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ |
|
10356 match(Set crx (CmpU src1 src2)); |
|
10357 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} |
|
10358 size(4); |
|
10359 ins_encode %{ |
|
10360 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); |
|
10361 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10362 %} |
|
10363 ins_pipe(pipe_class_compare); |
|
10364 %} |
|
10365 |
|
10366 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ |
|
10367 match(Set crx (CmpU src1 src2)); |
|
10368 size(4); |
|
10369 format %{ "CMPLWI $crx, $src1, $src2" %} |
|
10370 ins_encode %{ |
|
10371 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); |
|
10372 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10373 %} |
|
10374 ins_pipe(pipe_class_compare); |
|
10375 %} |
|
10376 |
|
10377 // Implicit zero checks (more implicit null checks). |
|
10378 // No constant pool entries required. |
|
10379 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ |
|
10380 match(If cmp (CmpN value zero)); |
|
10381 effect(USE labl); |
|
10382 predicate(TrapBasedNullChecks && |
|
10383 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && |
|
10384 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && |
|
10385 Matcher::branches_to_uncommon_trap(_leaf)); |
|
10386 ins_cost(1); |
|
10387 |
|
10388 ins_is_TrapBasedCheckNode(true); |
|
10389 |
|
10390 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} |
|
10391 size(4); |
|
10392 ins_encode %{ |
|
10393 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); |
|
10394 if ($cmp$$cmpcode == 0xA) { |
|
10395 __ trap_null_check($value$$Register); |
|
10396 } else { |
|
10397 // Both successors are uncommon traps, probability is 0. |
|
10398 // Node got flipped during fixup flow. |
|
10399 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); |
|
10400 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); |
|
10401 } |
|
10402 %} |
|
10403 ins_pipe(pipe_class_trap); |
|
10404 %} |
|
10405 |
|
10406 // Compare narrow oops. |
|
10407 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ |
|
10408 match(Set crx (CmpN src1 src2)); |
|
10409 |
|
10410 size(4); |
|
10411 ins_cost(DEFAULT_COST); |
|
10412 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} |
|
10413 ins_encode %{ |
|
10414 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); |
|
10415 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10416 %} |
|
10417 ins_pipe(pipe_class_compare); |
|
10418 %} |
|
10419 |
|
10420 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ |
|
10421 match(Set crx (CmpN src1 src2)); |
|
10422 // Make this more expensive than zeroCheckN_iReg_imm0. |
|
10423 ins_cost(DEFAULT_COST); |
|
10424 |
|
10425 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} |
|
10426 size(4); |
|
10427 ins_encode %{ |
|
10428 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); |
|
10429 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10430 %} |
|
10431 ins_pipe(pipe_class_compare); |
|
10432 %} |
|
10433 |
|
10434 // Implicit zero checks (more implicit null checks). |
|
10435 // No constant pool entries required. |
|
10436 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ |
|
10437 match(If cmp (CmpP value zero)); |
|
10438 effect(USE labl); |
|
10439 predicate(TrapBasedNullChecks && |
|
10440 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && |
|
10441 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && |
|
10442 Matcher::branches_to_uncommon_trap(_leaf)); |
|
10443 |
|
10444 ins_is_TrapBasedCheckNode(true); |
|
10445 |
|
10446 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} |
|
10447 size(4); |
|
10448 ins_encode %{ |
|
10449 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); |
|
10450 if ($cmp$$cmpcode == 0xA) { |
|
10451 __ trap_null_check($value$$Register); |
|
10452 } else { |
|
10453 // Both successors are uncommon traps, probability is 0. |
|
10454 // Node got flipped during fixup flow. |
|
10455 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); |
|
10456 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); |
|
10457 } |
|
10458 %} |
|
10459 ins_pipe(pipe_class_trap); |
|
10460 %} |
|
10461 |
|
10462 // Compare Pointers |
|
10463 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ |
|
10464 match(Set crx (CmpP src1 src2)); |
|
10465 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} |
|
10466 size(4); |
|
10467 ins_encode %{ |
|
10468 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); |
|
10469 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); |
|
10470 %} |
|
10471 ins_pipe(pipe_class_compare); |
|
10472 %} |
|
10473 |
|
10474 // Used in postalloc expand. |
|
10475 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ |
|
10476 // This match rule prevents reordering of node before a safepoint. |
|
10477 // This only makes sense if this instructions is used exclusively |
|
10478 // for the expansion of EncodeP! |
|
10479 match(Set crx (CmpP src1 src2)); |
|
10480 predicate(false); |
|
10481 |
|
10482 format %{ "CMPDI $crx, $src1, $src2" %} |
|
10483 size(4); |
|
10484 ins_encode %{ |
|
10485 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); |
|
10486 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); |
|
10487 %} |
|
10488 ins_pipe(pipe_class_compare); |
|
10489 %} |
|
10490 |
|
10491 //----------Float Compares---------------------------------------------------- |
|
10492 |
|
10493 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ |
|
10494 // no match-rule, false predicate |
|
10495 effect(DEF crx, USE src1, USE src2); |
|
10496 predicate(false); |
|
10497 |
|
10498 format %{ "cmpFUrd $crx, $src1, $src2" %} |
|
10499 size(4); |
|
10500 ins_encode %{ |
|
10501 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); |
|
10502 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
10503 %} |
|
10504 ins_pipe(pipe_class_default); |
|
10505 %} |
|
10506 |
|
10507 instruct cmov_bns_less(flagsReg crx) %{ |
|
10508 // no match-rule, false predicate |
|
10509 effect(DEF crx); |
|
10510 predicate(false); |
|
10511 |
|
10512 ins_variable_size_depending_on_alignment(true); |
|
10513 |
|
10514 format %{ "cmov $crx" %} |
|
10515 // Worst case is branch + move + stop, no stop without scheduler. |
|
10516 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); |
|
10517 ins_encode %{ |
|
10518 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); |
|
10519 Label done; |
|
10520 __ bns($crx$$CondRegister, done); // not unordered -> keep crx |
|
10521 __ li(R0, 0); |
|
10522 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' |
|
10523 // TODO PPC port __ endgroup_if_needed(_size == 16); |
|
10524 __ bind(done); |
|
10525 %} |
|
10526 ins_pipe(pipe_class_default); |
|
10527 %} |
|
10528 |
|
10529 // Compare floating, generate condition code. |
|
10530 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ |
|
10531 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? |
|
10532 // |
|
10533 // The following code sequence occurs a lot in mpegaudio: |
|
10534 // |
|
10535 // block BXX: |
|
10536 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): |
|
10537 // cmpFUrd CCR6, F11, F9 |
|
10538 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): |
|
10539 // cmov CCR6 |
|
10540 // 8: instruct branchConSched: |
|
10541 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 |
|
10542 match(Set crx (CmpF src1 src2)); |
|
10543 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
10544 |
|
10545 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} |
|
10546 postalloc_expand %{ |
|
10547 // |
|
10548 // replaces |
|
10549 // |
|
10550 // region src1 src2 |
|
10551 // \ | | |
|
10552 // crx=cmpF_reg_reg |
|
10553 // |
|
10554 // with |
|
10555 // |
|
10556 // region src1 src2 |
|
10557 // \ | | |
|
10558 // crx=cmpFUnordered_reg_reg |
|
10559 // | |
|
10560 // ^ region |
|
10561 // | \ |
|
10562 // crx=cmov_bns_less |
|
10563 // |
|
10564 |
|
10565 // Create new nodes. |
|
10566 MachNode *m1 = new (C) cmpFUnordered_reg_regNode(); |
|
10567 MachNode *m2 = new (C) cmov_bns_lessNode(); |
|
10568 |
|
10569 // inputs for new nodes |
|
10570 m1->add_req(n_region, n_src1, n_src2); |
|
10571 m2->add_req(n_region); |
|
10572 m2->add_prec(m1); |
|
10573 |
|
10574 // operands for new nodes |
|
10575 m1->_opnds[0] = op_crx; |
|
10576 m1->_opnds[1] = op_src1; |
|
10577 m1->_opnds[2] = op_src2; |
|
10578 m2->_opnds[0] = op_crx; |
|
10579 |
|
10580 // registers for new nodes |
|
10581 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10582 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10583 |
|
10584 // Insert new nodes. |
|
10585 nodes->push(m1); |
|
10586 nodes->push(m2); |
|
10587 %} |
|
10588 %} |
|
10589 |
|
10590 // Compare float, generate -1,0,1 |
|
10591 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ |
|
10592 match(Set dst (CmpF3 src1 src2)); |
|
10593 ins_cost(DEFAULT_COST*5+BRANCH_COST); |
|
10594 |
|
10595 expand %{ |
|
10596 flagsReg tmp1; |
|
10597 cmpFUnordered_reg_reg(tmp1, src1, src2); |
|
10598 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); |
|
10599 %} |
|
10600 %} |
|
10601 |
|
10602 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ |
|
10603 // no match-rule, false predicate |
|
10604 effect(DEF crx, USE src1, USE src2); |
|
10605 predicate(false); |
|
10606 |
|
10607 format %{ "cmpFUrd $crx, $src1, $src2" %} |
|
10608 size(4); |
|
10609 ins_encode %{ |
|
10610 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); |
|
10611 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); |
|
10612 %} |
|
10613 ins_pipe(pipe_class_default); |
|
10614 %} |
|
10615 |
|
10616 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ |
|
10617 match(Set crx (CmpD src1 src2)); |
|
10618 ins_cost(DEFAULT_COST+BRANCH_COST); |
|
10619 |
|
10620 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} |
|
10621 postalloc_expand %{ |
|
10622 // |
|
10623 // replaces |
|
10624 // |
|
10625 // region src1 src2 |
|
10626 // \ | | |
|
10627 // crx=cmpD_reg_reg |
|
10628 // |
|
10629 // with |
|
10630 // |
|
10631 // region src1 src2 |
|
10632 // \ | | |
|
10633 // crx=cmpDUnordered_reg_reg |
|
10634 // | |
|
10635 // ^ region |
|
10636 // | \ |
|
10637 // crx=cmov_bns_less |
|
10638 // |
|
10639 |
|
10640 // create new nodes |
|
10641 MachNode *m1 = new (C) cmpDUnordered_reg_regNode(); |
|
10642 MachNode *m2 = new (C) cmov_bns_lessNode(); |
|
10643 |
|
10644 // inputs for new nodes |
|
10645 m1->add_req(n_region, n_src1, n_src2); |
|
10646 m2->add_req(n_region); |
|
10647 m2->add_prec(m1); |
|
10648 |
|
10649 // operands for new nodes |
|
10650 m1->_opnds[0] = op_crx; |
|
10651 m1->_opnds[1] = op_src1; |
|
10652 m1->_opnds[2] = op_src2; |
|
10653 m2->_opnds[0] = op_crx; |
|
10654 |
|
10655 // registers for new nodes |
|
10656 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10657 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx |
|
10658 |
|
10659 // Insert new nodes. |
|
10660 nodes->push(m1); |
|
10661 nodes->push(m2); |
|
10662 %} |
|
10663 %} |
|
10664 |
|
10665 // Compare double, generate -1,0,1 |
|
10666 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ |
|
10667 match(Set dst (CmpD3 src1 src2)); |
|
10668 ins_cost(DEFAULT_COST*5+BRANCH_COST); |
|
10669 |
|
10670 expand %{ |
|
10671 flagsReg tmp1; |
|
10672 cmpDUnordered_reg_reg(tmp1, src1, src2); |
|
10673 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); |
|
10674 %} |
|
10675 %} |
|
10676 |
|
10677 //----------Branches--------------------------------------------------------- |
|
10678 // Jump |
|
10679 |
|
10680 // Direct Branch. |
|
10681 instruct branch(label labl) %{ |
|
10682 match(Goto); |
|
10683 effect(USE labl); |
|
10684 ins_cost(BRANCH_COST); |
|
10685 |
|
10686 format %{ "B $labl" %} |
|
10687 size(4); |
|
10688 ins_encode %{ |
|
10689 // TODO: PPC port $archOpcode(ppc64Opcode_b); |
|
10690 Label d; // dummy |
|
10691 __ bind(d); |
|
10692 Label* p = $labl$$label; |
|
10693 // `p' is `NULL' when this encoding class is used only to |
|
10694 // determine the size of the encoded instruction. |
|
10695 Label& l = (NULL == p)? d : *(p); |
|
10696 __ b(l); |
|
10697 %} |
|
10698 ins_pipe(pipe_class_default); |
|
10699 %} |
|
10700 |
|
10701 // Conditional Near Branch |
|
10702 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{ |
|
10703 // Same match rule as `branchConFar'. |
|
10704 match(If cmp crx); |
|
10705 effect(USE lbl); |
|
10706 ins_cost(BRANCH_COST); |
|
10707 |
|
10708 // If set to 1 this indicates that the current instruction is a |
|
10709 // short variant of a long branch. This avoids using this |
|
10710 // instruction in first-pass matching. It will then only be used in |
|
10711 // the `Shorten_branches' pass. |
|
10712 ins_short_branch(1); |
|
10713 |
|
10714 format %{ "B$cmp $crx, $lbl" %} |
|
10715 size(4); |
|
10716 ins_encode( enc_bc(crx, cmp, lbl) ); |
|
10717 ins_pipe(pipe_class_default); |
|
10718 %} |
|
10719 |
|
10720 // This is for cases when the ppc64 `bc' instruction does not |
|
10721 // reach far enough. So we emit a far branch here, which is more |
|
10722 // expensive. |
|
10723 // |
|
10724 // Conditional Far Branch |
|
10725 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{ |
|
10726 // Same match rule as `branchCon'. |
|
10727 match(If cmp crx); |
|
10728 effect(USE crx, USE lbl); |
|
10729 predicate(!false /* TODO: PPC port HB_Schedule*/); |
|
10730 // Higher cost than `branchCon'. |
|
10731 ins_cost(5*BRANCH_COST); |
|
10732 |
|
10733 // This is not a short variant of a branch, but the long variant. |
|
10734 ins_short_branch(0); |
|
10735 |
|
10736 format %{ "B_FAR$cmp $crx, $lbl" %} |
|
10737 size(8); |
|
10738 ins_encode( enc_bc_far(crx, cmp, lbl) ); |
|
10739 ins_pipe(pipe_class_default); |
|
10740 %} |
|
10741 |
|
10742 // Conditional Branch used with Power6 scheduler (can be far or short). |
|
10743 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{ |
|
10744 // Same match rule as `branchCon'. |
|
10745 match(If cmp crx); |
|
10746 effect(USE crx, USE lbl); |
|
10747 predicate(false /* TODO: PPC port HB_Schedule*/); |
|
10748 // Higher cost than `branchCon'. |
|
10749 ins_cost(5*BRANCH_COST); |
|
10750 |
|
10751 // Actually size doesn't depend on alignment but on shortening. |
|
10752 ins_variable_size_depending_on_alignment(true); |
|
10753 // long variant. |
|
10754 ins_short_branch(0); |
|
10755 |
|
10756 format %{ "B_FAR$cmp $crx, $lbl" %} |
|
10757 size(8); // worst case |
|
10758 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); |
|
10759 ins_pipe(pipe_class_default); |
|
10760 %} |
|
10761 |
|
10762 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{ |
|
10763 match(CountedLoopEnd cmp crx); |
|
10764 effect(USE labl); |
|
10765 ins_cost(BRANCH_COST); |
|
10766 |
|
10767 // short variant. |
|
10768 ins_short_branch(1); |
|
10769 |
|
10770 format %{ "B$cmp $crx, $labl \t// counted loop end" %} |
|
10771 size(4); |
|
10772 ins_encode( enc_bc(crx, cmp, labl) ); |
|
10773 ins_pipe(pipe_class_default); |
|
10774 %} |
|
10775 |
|
10776 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{ |
|
10777 match(CountedLoopEnd cmp crx); |
|
10778 effect(USE labl); |
|
10779 predicate(!false /* TODO: PPC port HB_Schedule */); |
|
10780 ins_cost(BRANCH_COST); |
|
10781 |
|
10782 // Long variant. |
|
10783 ins_short_branch(0); |
|
10784 |
|
10785 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} |
|
10786 size(8); |
|
10787 ins_encode( enc_bc_far(crx, cmp, labl) ); |
|
10788 ins_pipe(pipe_class_default); |
|
10789 %} |
|
10790 |
|
10791 // Conditional Branch used with Power6 scheduler (can be far or short). |
|
10792 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{ |
|
10793 match(CountedLoopEnd cmp crx); |
|
10794 effect(USE labl); |
|
10795 predicate(false /* TODO: PPC port HB_Schedule */); |
|
10796 // Higher cost than `branchCon'. |
|
10797 ins_cost(5*BRANCH_COST); |
|
10798 |
|
10799 // Actually size doesn't depend on alignment but on shortening. |
|
10800 ins_variable_size_depending_on_alignment(true); |
|
10801 // Long variant. |
|
10802 ins_short_branch(0); |
|
10803 |
|
10804 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} |
|
10805 size(8); // worst case |
|
10806 ins_encode( enc_bc_short_far(crx, cmp, labl) ); |
|
10807 ins_pipe(pipe_class_default); |
|
10808 %} |
|
10809 |
|
10810 // ============================================================================ |
|
10811 // Java runtime operations, intrinsics and other complex operations. |
|
10812 |
|
10813 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass |
|
10814 // array for an instance of the superklass. Set a hidden internal cache on a |
|
10815 // hit (cache is checked with exposed code in gen_subtype_check()). Return |
|
10816 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. |
|
10817 // |
|
10818 // GL TODO: Improve this. |
|
10819 // - result should not be a TEMP |
|
10820 // - Add match rule as on sparc avoiding additional Cmp. |
|
10821 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, |
|
10822 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ |
|
10823 match(Set result (PartialSubtypeCheck subklass superklass)); |
|
10824 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr); |
|
10825 ins_cost(DEFAULT_COST*10); |
|
10826 |
|
10827 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} |
|
10828 ins_encode %{ |
|
10829 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10830 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, |
|
10831 $tmp_klass$$Register, NULL, $result$$Register); |
|
10832 %} |
|
10833 ins_pipe(pipe_class_default); |
|
10834 %} |
|
10835 |
|
10836 // inlined locking and unlocking |
|
10837 |
|
10838 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ |
|
10839 match(Set crx (FastLock oop box)); |
|
10840 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); |
|
10841 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking); |
|
10842 |
|
10843 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %} |
|
10844 ins_encode %{ |
|
10845 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10846 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, |
|
10847 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); |
|
10848 // If locking was successfull, crx should indicate 'EQ'. |
|
10849 // The compiler generates a branch to the runtime call to |
|
10850 // _complete_monitor_locking_Java for the case where crx is 'NE'. |
|
10851 %} |
|
10852 ins_pipe(pipe_class_compare); |
|
10853 %} |
|
10854 |
|
10855 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ |
|
10856 match(Set crx (FastUnlock oop box)); |
|
10857 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); |
|
10858 |
|
10859 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} |
|
10860 ins_encode %{ |
|
10861 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10862 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, |
|
10863 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); |
|
10864 // If unlocking was successfull, crx should indicate 'EQ'. |
|
10865 // The compiler generates a branch to the runtime call to |
|
10866 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. |
|
10867 %} |
|
10868 ins_pipe(pipe_class_compare); |
|
10869 %} |
|
10870 |
|
10871 // Align address. |
|
10872 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ |
|
10873 match(Set dst (CastX2P (AndL (CastP2X src) mask))); |
|
10874 |
|
10875 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} |
|
10876 size(4); |
|
10877 ins_encode %{ |
|
10878 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); |
|
10879 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); |
|
10880 %} |
|
10881 ins_pipe(pipe_class_default); |
|
10882 %} |
|
10883 |
|
10884 // Array size computation. |
|
10885 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ |
|
10886 match(Set dst (SubL (CastP2X end) (CastP2X start))); |
|
10887 |
|
10888 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} |
|
10889 size(4); |
|
10890 ins_encode %{ |
|
10891 // TODO: PPC port $archOpcode(ppc64Opcode_subf); |
|
10892 __ subf($dst$$Register, $start$$Register, $end$$Register); |
|
10893 %} |
|
10894 ins_pipe(pipe_class_default); |
|
10895 %} |
|
10896 |
|
10897 // Clear-array with dynamic array-size. |
|
10898 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ |
|
10899 match(Set dummy (ClearArray cnt base)); |
|
10900 effect(USE_KILL cnt, USE_KILL base, KILL ctr); |
|
10901 ins_cost(MEMORY_REF_COST); |
|
10902 |
|
10903 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
10904 |
|
10905 format %{ "ClearArray $cnt, $base" %} |
|
10906 ins_encode %{ |
|
10907 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10908 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 |
|
10909 %} |
|
10910 ins_pipe(pipe_class_default); |
|
10911 %} |
|
10912 |
|
10913 // String_IndexOf for needle of length 1. |
|
10914 // |
|
10915 // Match needle into immediate operands: no loadConP node needed. Saves one |
|
10916 // register and two instructions over string_indexOf_imm1Node. |
|
10917 // |
|
10918 // Assumes register result differs from all input registers. |
|
10919 // |
|
10920 // Preserves registers haystack, haycnt |
|
10921 // Kills registers tmp1, tmp2 |
|
10922 // Defines registers result |
|
10923 // |
|
10924 // Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
10925 // |
|
10926 // Unfortunately this does not match too often. In many situations the AddP is used |
|
10927 // by several nodes, even several StrIndexOf nodes, breaking the match tree. |
|
10928 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, |
|
10929 immP needleImm, immL offsetImm, immI_1 needlecntImm, |
|
10930 iRegIdst tmp1, iRegIdst tmp2, |
|
10931 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ |
|
10932 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported |
|
10933 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); |
|
10934 |
|
10935 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); |
|
10936 |
|
10937 ins_cost(150); |
|
10938 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" |
|
10939 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} |
|
10940 |
|
10941 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted |
|
10942 ins_encode %{ |
|
10943 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10944 immPOper *needleOper = (immPOper *)$needleImm; |
|
10945 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); |
|
10946 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * |
|
10947 |
|
10948 __ string_indexof_1($result$$Register, |
|
10949 $haystack$$Register, $haycnt$$Register, |
|
10950 R0, needle_values->char_at(0), |
|
10951 $tmp1$$Register, $tmp2$$Register); |
|
10952 %} |
|
10953 ins_pipe(pipe_class_compare); |
|
10954 %} |
|
10955 |
|
10956 // String_IndexOf for needle of length 1. |
|
10957 // |
|
10958 // Special case requires less registers and emits less instructions. |
|
10959 // |
|
10960 // Assumes register result differs from all input registers. |
|
10961 // |
|
10962 // Preserves registers haystack, haycnt |
|
10963 // Kills registers tmp1, tmp2, needle |
|
10964 // Defines registers result |
|
10965 // |
|
10966 // Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
10967 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, |
|
10968 rscratch2RegP needle, immI_1 needlecntImm, |
|
10969 iRegIdst tmp1, iRegIdst tmp2, |
|
10970 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ |
|
10971 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
10972 effect(USE_KILL needle, /* TDEF needle, */ TEMP result, |
|
10973 TEMP tmp1, TEMP tmp2); |
|
10974 // Required for EA: check if it is still a type_array. |
|
10975 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && |
|
10976 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); |
|
10977 ins_cost(180); |
|
10978 |
|
10979 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
10980 |
|
10981 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" |
|
10982 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} |
|
10983 ins_encode %{ |
|
10984 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
10985 Node *ndl = in(operand_index($needle)); // The node that defines needle. |
|
10986 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); |
|
10987 guarantee(needle_values, "sanity"); |
|
10988 if (needle_values != NULL) { |
|
10989 __ string_indexof_1($result$$Register, |
|
10990 $haystack$$Register, $haycnt$$Register, |
|
10991 R0, needle_values->char_at(0), |
|
10992 $tmp1$$Register, $tmp2$$Register); |
|
10993 } else { |
|
10994 __ string_indexof_1($result$$Register, |
|
10995 $haystack$$Register, $haycnt$$Register, |
|
10996 $needle$$Register, 0, |
|
10997 $tmp1$$Register, $tmp2$$Register); |
|
10998 } |
|
10999 %} |
|
11000 ins_pipe(pipe_class_compare); |
|
11001 %} |
|
11002 |
|
11003 // String_IndexOf. |
|
11004 // |
|
11005 // Length of needle as immediate. This saves instruction loading constant needle |
|
11006 // length. |
|
11007 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle |
|
11008 // completely or do it in vector instruction. This should save registers for |
|
11009 // needlecnt and needle. |
|
11010 // |
|
11011 // Assumes register result differs from all input registers. |
|
11012 // Overwrites haycnt, needlecnt. |
|
11013 // Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
11014 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, |
|
11015 iRegPsrc needle, uimmI15 needlecntImm, |
|
11016 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, |
|
11017 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ |
|
11018 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); |
|
11019 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result, |
|
11020 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); |
|
11021 // Required for EA: check if it is still a type_array. |
|
11022 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && |
|
11023 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); |
|
11024 ins_cost(250); |
|
11025 |
|
11026 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11027 |
|
11028 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" |
|
11029 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} |
|
11030 ins_encode %{ |
|
11031 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11032 Node *ndl = in(operand_index($needle)); // The node that defines needle. |
|
11033 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); |
|
11034 |
|
11035 __ string_indexof($result$$Register, |
|
11036 $haystack$$Register, $haycnt$$Register, |
|
11037 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, |
|
11038 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); |
|
11039 %} |
|
11040 ins_pipe(pipe_class_compare); |
|
11041 %} |
|
11042 |
|
11043 // StrIndexOf node. |
|
11044 // |
|
11045 // Assumes register result differs from all input registers. |
|
11046 // Overwrites haycnt, needlecnt. |
|
11047 // Use dst register classes if register gets killed, as it is the case for tmp registers! |
|
11048 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, |
|
11049 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, |
|
11050 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ |
|
11051 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); |
|
11052 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ |
|
11053 TEMP result, |
|
11054 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); |
|
11055 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. |
|
11056 ins_cost(300); |
|
11057 |
|
11058 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11059 |
|
11060 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" |
|
11061 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} |
|
11062 ins_encode %{ |
|
11063 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11064 __ string_indexof($result$$Register, |
|
11065 $haystack$$Register, $haycnt$$Register, |
|
11066 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. |
|
11067 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); |
|
11068 %} |
|
11069 ins_pipe(pipe_class_compare); |
|
11070 %} |
|
11071 |
|
11072 // String equals with immediate. |
|
11073 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, |
|
11074 iRegPdst tmp1, iRegPdst tmp2, |
|
11075 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ |
|
11076 match(Set result (StrEquals (Binary str1 str2) cntImm)); |
|
11077 effect(TEMP result, TEMP tmp1, TEMP tmp2, |
|
11078 KILL cr0, KILL cr6, KILL ctr); |
|
11079 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. |
|
11080 ins_cost(250); |
|
11081 |
|
11082 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11083 |
|
11084 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" |
|
11085 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} |
|
11086 ins_encode %{ |
|
11087 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11088 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, |
|
11089 $result$$Register, $tmp1$$Register, $tmp2$$Register); |
|
11090 %} |
|
11091 ins_pipe(pipe_class_compare); |
|
11092 %} |
|
11093 |
|
11094 // String equals. |
|
11095 // Use dst register classes if register gets killed, as it is the case for TEMP operands! |
|
11096 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, |
|
11097 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, |
|
11098 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ |
|
11099 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
11100 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, |
|
11101 KILL cr0, KILL cr1, KILL cr6, KILL ctr); |
|
11102 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. |
|
11103 ins_cost(300); |
|
11104 |
|
11105 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11106 |
|
11107 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" |
|
11108 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} |
|
11109 ins_encode %{ |
|
11110 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11111 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, |
|
11112 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); |
|
11113 %} |
|
11114 ins_pipe(pipe_class_compare); |
|
11115 %} |
|
11116 |
|
11117 // String compare. |
|
11118 // Char[] pointers are passed in. |
|
11119 // Use dst register classes if register gets killed, as it is the case for TEMP operands! |
|
11120 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, |
|
11121 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ |
|
11122 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
11123 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr); |
|
11124 ins_cost(300); |
|
11125 |
|
11126 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. |
|
11127 |
|
11128 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" |
|
11129 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} |
|
11130 ins_encode %{ |
|
11131 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11132 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, |
|
11133 $result$$Register, $tmp$$Register); |
|
11134 %} |
|
11135 ins_pipe(pipe_class_compare); |
|
11136 %} |
|
11137 |
|
11138 //---------- Min/Max Instructions --------------------------------------------- |
|
11139 |
|
11140 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
11141 match(Set dst (MinI src1 src2)); |
|
11142 ins_cost(DEFAULT_COST*6); |
|
11143 |
|
11144 expand %{ |
|
11145 iRegIdst src1s; |
|
11146 iRegIdst src2s; |
|
11147 iRegIdst diff; |
|
11148 iRegIdst sm; |
|
11149 iRegIdst doz; // difference or zero |
|
11150 sxtI_reg(src1s, src1); // Ensure proper sign extention. |
|
11151 sxtI_reg(src2s, src2); // Ensure proper sign extention. |
|
11152 subI_reg_reg(diff, src2s, src1s); |
|
11153 // Need to consider >=33 bit result, therefore we need signmaskL. |
|
11154 signmask64I_regI(sm, diff); |
|
11155 andI_reg_reg(doz, diff, sm); // <=0 |
|
11156 addI_reg_reg(dst, doz, src1s); |
|
11157 %} |
|
11158 %} |
|
11159 |
|
11160 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ |
|
11161 match(Set dst (MaxI src1 src2)); |
|
11162 ins_cost(DEFAULT_COST*6); |
|
11163 |
|
11164 expand %{ |
|
11165 immI_minus1 m1 %{ -1 %} |
|
11166 iRegIdst src1s; |
|
11167 iRegIdst src2s; |
|
11168 iRegIdst diff; |
|
11169 iRegIdst sm; |
|
11170 iRegIdst doz; // difference or zero |
|
11171 sxtI_reg(src1s, src1); // Ensure proper sign extention. |
|
11172 sxtI_reg(src2s, src2); // Ensure proper sign extention. |
|
11173 subI_reg_reg(diff, src2s, src1s); |
|
11174 // Need to consider >=33 bit result, therefore we need signmaskL. |
|
11175 signmask64I_regI(sm, diff); |
|
11176 andcI_reg_reg(doz, sm, m1, diff); // >=0 |
|
11177 addI_reg_reg(dst, doz, src1s); |
|
11178 %} |
|
11179 %} |
|
11180 |
|
11181 //---------- Population Count Instructions ------------------------------------ |
|
11182 |
|
11183 // Popcnt for Power7. |
|
11184 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ |
|
11185 match(Set dst (PopCountI src)); |
|
11186 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); |
|
11187 ins_cost(DEFAULT_COST); |
|
11188 |
|
11189 format %{ "POPCNTW $dst, $src" %} |
|
11190 size(4); |
|
11191 ins_encode %{ |
|
11192 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); |
|
11193 __ popcntw($dst$$Register, $src$$Register); |
|
11194 %} |
|
11195 ins_pipe(pipe_class_default); |
|
11196 %} |
|
11197 |
|
11198 // Popcnt for Power7. |
|
11199 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ |
|
11200 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); |
|
11201 match(Set dst (PopCountL src)); |
|
11202 ins_cost(DEFAULT_COST); |
|
11203 |
|
11204 format %{ "POPCNTD $dst, $src" %} |
|
11205 size(4); |
|
11206 ins_encode %{ |
|
11207 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); |
|
11208 __ popcntd($dst$$Register, $src$$Register); |
|
11209 %} |
|
11210 ins_pipe(pipe_class_default); |
|
11211 %} |
|
11212 |
|
11213 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ |
|
11214 match(Set dst (CountLeadingZerosI src)); |
|
11215 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. |
|
11216 ins_cost(DEFAULT_COST); |
|
11217 |
|
11218 format %{ "CNTLZW $dst, $src" %} |
|
11219 size(4); |
|
11220 ins_encode %{ |
|
11221 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); |
|
11222 __ cntlzw($dst$$Register, $src$$Register); |
|
11223 %} |
|
11224 ins_pipe(pipe_class_default); |
|
11225 %} |
|
11226 |
|
11227 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ |
|
11228 match(Set dst (CountLeadingZerosL src)); |
|
11229 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. |
|
11230 ins_cost(DEFAULT_COST); |
|
11231 |
|
11232 format %{ "CNTLZD $dst, $src" %} |
|
11233 size(4); |
|
11234 ins_encode %{ |
|
11235 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); |
|
11236 __ cntlzd($dst$$Register, $src$$Register); |
|
11237 %} |
|
11238 ins_pipe(pipe_class_default); |
|
11239 %} |
|
11240 |
|
11241 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ |
|
11242 // no match-rule, false predicate |
|
11243 effect(DEF dst, USE src); |
|
11244 predicate(false); |
|
11245 |
|
11246 format %{ "CNTLZD $dst, $src" %} |
|
11247 size(4); |
|
11248 ins_encode %{ |
|
11249 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); |
|
11250 __ cntlzd($dst$$Register, $src$$Register); |
|
11251 %} |
|
11252 ins_pipe(pipe_class_default); |
|
11253 %} |
|
11254 |
|
11255 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ |
|
11256 match(Set dst (CountTrailingZerosI src)); |
|
11257 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
11258 ins_cost(DEFAULT_COST); |
|
11259 |
|
11260 expand %{ |
|
11261 immI16 imm1 %{ (int)-1 %} |
|
11262 immI16 imm2 %{ (int)32 %} |
|
11263 immI_minus1 m1 %{ -1 %} |
|
11264 iRegIdst tmpI1; |
|
11265 iRegIdst tmpI2; |
|
11266 iRegIdst tmpI3; |
|
11267 addI_reg_imm16(tmpI1, src, imm1); |
|
11268 andcI_reg_reg(tmpI2, src, m1, tmpI1); |
|
11269 countLeadingZerosI(tmpI3, tmpI2); |
|
11270 subI_imm16_reg(dst, imm2, tmpI3); |
|
11271 %} |
|
11272 %} |
|
11273 |
|
11274 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ |
|
11275 match(Set dst (CountTrailingZerosL src)); |
|
11276 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
11277 ins_cost(DEFAULT_COST); |
|
11278 |
|
11279 expand %{ |
|
11280 immL16 imm1 %{ (long)-1 %} |
|
11281 immI16 imm2 %{ (int)64 %} |
|
11282 iRegLdst tmpL1; |
|
11283 iRegLdst tmpL2; |
|
11284 iRegIdst tmpL3; |
|
11285 addL_reg_imm16(tmpL1, src, imm1); |
|
11286 andcL_reg_reg(tmpL2, tmpL1, src); |
|
11287 countLeadingZerosL(tmpL3, tmpL2); |
|
11288 subI_imm16_reg(dst, imm2, tmpL3); |
|
11289 %} |
|
11290 %} |
|
11291 |
|
11292 // Expand nodes for byte_reverse_int. |
|
11293 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ |
|
11294 effect(DEF dst, USE src, USE pos, USE shift); |
|
11295 predicate(false); |
|
11296 |
|
11297 format %{ "INSRWI $dst, $src, $pos, $shift" %} |
|
11298 size(4); |
|
11299 ins_encode %{ |
|
11300 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); |
|
11301 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); |
|
11302 %} |
|
11303 ins_pipe(pipe_class_default); |
|
11304 %} |
|
11305 |
|
11306 // As insrwi_a, but with USE_DEF. |
|
11307 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ |
|
11308 effect(USE_DEF dst, USE src, USE pos, USE shift); |
|
11309 predicate(false); |
|
11310 |
|
11311 format %{ "INSRWI $dst, $src, $pos, $shift" %} |
|
11312 size(4); |
|
11313 ins_encode %{ |
|
11314 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); |
|
11315 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); |
|
11316 %} |
|
11317 ins_pipe(pipe_class_default); |
|
11318 %} |
|
11319 |
|
11320 // Just slightly faster than java implementation. |
|
11321 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ |
|
11322 match(Set dst (ReverseBytesI src)); |
|
11323 predicate(UseCountLeadingZerosInstructionsPPC64); |
|
11324 ins_cost(DEFAULT_COST); |
|
11325 |
|
11326 expand %{ |
|
11327 immI16 imm24 %{ (int) 24 %} |
|
11328 immI16 imm16 %{ (int) 16 %} |
|
11329 immI16 imm8 %{ (int) 8 %} |
|
11330 immI16 imm4 %{ (int) 4 %} |
|
11331 immI16 imm0 %{ (int) 0 %} |
|
11332 iRegLdst tmpI1; |
|
11333 iRegLdst tmpI2; |
|
11334 iRegLdst tmpI3; |
|
11335 |
|
11336 urShiftI_reg_imm(tmpI1, src, imm24); |
|
11337 insrwi_a(dst, tmpI1, imm24, imm8); |
|
11338 urShiftI_reg_imm(tmpI2, src, imm16); |
|
11339 insrwi(dst, tmpI2, imm8, imm16); |
|
11340 urShiftI_reg_imm(tmpI3, src, imm8); |
|
11341 insrwi(dst, tmpI3, imm8, imm8); |
|
11342 insrwi(dst, src, imm0, imm8); |
|
11343 %} |
|
11344 %} |
|
11345 |
|
11346 //---------- Replicate Vector Instructions ------------------------------------ |
|
11347 |
|
11348 // Insrdi does replicate if src == dst. |
|
11349 instruct repl32(iRegLdst dst) %{ |
|
11350 predicate(false); |
|
11351 effect(USE_DEF dst); |
|
11352 |
|
11353 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} |
|
11354 size(4); |
|
11355 ins_encode %{ |
|
11356 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); |
|
11357 __ insrdi($dst$$Register, $dst$$Register, 32, 0); |
|
11358 %} |
|
11359 ins_pipe(pipe_class_default); |
|
11360 %} |
|
11361 |
|
11362 // Insrdi does replicate if src == dst. |
|
11363 instruct repl48(iRegLdst dst) %{ |
|
11364 predicate(false); |
|
11365 effect(USE_DEF dst); |
|
11366 |
|
11367 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} |
|
11368 size(4); |
|
11369 ins_encode %{ |
|
11370 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); |
|
11371 __ insrdi($dst$$Register, $dst$$Register, 48, 0); |
|
11372 %} |
|
11373 ins_pipe(pipe_class_default); |
|
11374 %} |
|
11375 |
|
11376 // Insrdi does replicate if src == dst. |
|
11377 instruct repl56(iRegLdst dst) %{ |
|
11378 predicate(false); |
|
11379 effect(USE_DEF dst); |
|
11380 |
|
11381 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} |
|
11382 size(4); |
|
11383 ins_encode %{ |
|
11384 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); |
|
11385 __ insrdi($dst$$Register, $dst$$Register, 56, 0); |
|
11386 %} |
|
11387 ins_pipe(pipe_class_default); |
|
11388 %} |
|
11389 |
|
11390 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ |
|
11391 match(Set dst (ReplicateB src)); |
|
11392 predicate(n->as_Vector()->length() == 8); |
|
11393 expand %{ |
|
11394 moveReg(dst, src); |
|
11395 repl56(dst); |
|
11396 repl48(dst); |
|
11397 repl32(dst); |
|
11398 %} |
|
11399 %} |
|
11400 |
|
11401 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ |
|
11402 match(Set dst (ReplicateB zero)); |
|
11403 predicate(n->as_Vector()->length() == 8); |
|
11404 format %{ "LI $dst, #0 \t// replicate8B" %} |
|
11405 size(4); |
|
11406 ins_encode %{ |
|
11407 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11408 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); |
|
11409 %} |
|
11410 ins_pipe(pipe_class_default); |
|
11411 %} |
|
11412 |
|
11413 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ |
|
11414 match(Set dst (ReplicateB src)); |
|
11415 predicate(n->as_Vector()->length() == 8); |
|
11416 format %{ "LI $dst, #-1 \t// replicate8B" %} |
|
11417 size(4); |
|
11418 ins_encode %{ |
|
11419 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11420 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
11421 %} |
|
11422 ins_pipe(pipe_class_default); |
|
11423 %} |
|
11424 |
|
11425 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ |
|
11426 match(Set dst (ReplicateS src)); |
|
11427 predicate(n->as_Vector()->length() == 4); |
|
11428 expand %{ |
|
11429 moveReg(dst, src); |
|
11430 repl48(dst); |
|
11431 repl32(dst); |
|
11432 %} |
|
11433 %} |
|
11434 |
|
11435 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ |
|
11436 match(Set dst (ReplicateS zero)); |
|
11437 predicate(n->as_Vector()->length() == 4); |
|
11438 format %{ "LI $dst, #0 \t// replicate4C" %} |
|
11439 size(4); |
|
11440 ins_encode %{ |
|
11441 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11442 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); |
|
11443 %} |
|
11444 ins_pipe(pipe_class_default); |
|
11445 %} |
|
11446 |
|
11447 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ |
|
11448 match(Set dst (ReplicateS src)); |
|
11449 predicate(n->as_Vector()->length() == 4); |
|
11450 format %{ "LI $dst, -1 \t// replicate4C" %} |
|
11451 size(4); |
|
11452 ins_encode %{ |
|
11453 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11454 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
11455 %} |
|
11456 ins_pipe(pipe_class_default); |
|
11457 %} |
|
11458 |
|
11459 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ |
|
11460 match(Set dst (ReplicateI src)); |
|
11461 predicate(n->as_Vector()->length() == 2); |
|
11462 ins_cost(2 * DEFAULT_COST); |
|
11463 expand %{ |
|
11464 moveReg(dst, src); |
|
11465 repl32(dst); |
|
11466 %} |
|
11467 %} |
|
11468 |
|
11469 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ |
|
11470 match(Set dst (ReplicateI zero)); |
|
11471 predicate(n->as_Vector()->length() == 2); |
|
11472 format %{ "LI $dst, #0 \t// replicate4C" %} |
|
11473 size(4); |
|
11474 ins_encode %{ |
|
11475 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11476 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); |
|
11477 %} |
|
11478 ins_pipe(pipe_class_default); |
|
11479 %} |
|
11480 |
|
11481 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ |
|
11482 match(Set dst (ReplicateI src)); |
|
11483 predicate(n->as_Vector()->length() == 2); |
|
11484 format %{ "LI $dst, -1 \t// replicate4C" %} |
|
11485 size(4); |
|
11486 ins_encode %{ |
|
11487 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11488 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); |
|
11489 %} |
|
11490 ins_pipe(pipe_class_default); |
|
11491 %} |
|
11492 |
|
11493 // Move float to int register via stack, replicate. |
|
11494 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ |
|
11495 match(Set dst (ReplicateF src)); |
|
11496 predicate(n->as_Vector()->length() == 2); |
|
11497 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); |
|
11498 expand %{ |
|
11499 stackSlotL tmpS; |
|
11500 iRegIdst tmpI; |
|
11501 moveF2I_reg_stack(tmpS, src); // Move float to stack. |
|
11502 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. |
|
11503 moveReg(dst, tmpI); // Move int to long reg. |
|
11504 repl32(dst); // Replicate bitpattern. |
|
11505 %} |
|
11506 %} |
|
11507 |
|
11508 // Replicate scalar constant to packed float values in Double register |
|
11509 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ |
|
11510 match(Set dst (ReplicateF src)); |
|
11511 predicate(n->as_Vector()->length() == 2); |
|
11512 ins_cost(5 * DEFAULT_COST); |
|
11513 |
|
11514 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} |
|
11515 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); |
|
11516 %} |
|
11517 |
|
11518 // Replicate scalar zero constant to packed float values in Double register |
|
11519 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ |
|
11520 match(Set dst (ReplicateF zero)); |
|
11521 predicate(n->as_Vector()->length() == 2); |
|
11522 |
|
11523 format %{ "LI $dst, #0 \t// replicate2F" %} |
|
11524 ins_encode %{ |
|
11525 // TODO: PPC port $archOpcode(ppc64Opcode_addi); |
|
11526 __ li($dst$$Register, 0x0); |
|
11527 %} |
|
11528 ins_pipe(pipe_class_default); |
|
11529 %} |
|
11530 |
|
11531 // ============================================================================ |
|
11532 // Safepoint Instruction |
|
11533 |
|
11534 instruct safePoint_poll(iRegPdst poll) %{ |
|
11535 match(SafePoint poll); |
|
11536 predicate(LoadPollAddressFromThread); |
|
11537 |
|
11538 // It caused problems to add the effect that r0 is killed, but this |
|
11539 // effect no longer needs to be mentioned, since r0 is not contained |
|
11540 // in a reg_class. |
|
11541 |
|
11542 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} |
|
11543 size(4); |
|
11544 ins_encode( enc_poll(0x0, poll) ); |
|
11545 ins_pipe(pipe_class_default); |
|
11546 %} |
|
11547 |
|
11548 // Safepoint without per-thread support. Load address of page to poll |
|
11549 // as constant. |
|
11550 // Rscratch2RegP is R12. |
|
11551 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be |
|
11552 // a seperate node so that the oop map is at the right location. |
|
11553 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ |
|
11554 match(SafePoint poll); |
|
11555 predicate(!LoadPollAddressFromThread); |
|
11556 |
|
11557 // It caused problems to add the effect that r0 is killed, but this |
|
11558 // effect no longer needs to be mentioned, since r0 is not contained |
|
11559 // in a reg_class. |
|
11560 |
|
11561 format %{ "LD R12, addr of polling page\n\t" |
|
11562 "LD R0, #0, R12 \t// Safepoint poll for GC" %} |
|
11563 ins_encode( enc_poll(0x0, poll) ); |
|
11564 ins_pipe(pipe_class_default); |
|
11565 %} |
|
11566 |
|
11567 // ============================================================================ |
|
11568 // Call Instructions |
|
11569 |
|
11570 // Call Java Static Instruction |
|
11571 |
|
11572 // Schedulable version of call static node. |
|
11573 instruct CallStaticJavaDirect(method meth) %{ |
|
11574 match(CallStaticJava); |
|
11575 effect(USE meth); |
|
11576 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
11577 ins_cost(CALL_COST); |
|
11578 |
|
11579 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); |
|
11580 |
|
11581 format %{ "CALL,static $meth \t// ==> " %} |
|
11582 size(4); |
|
11583 ins_encode( enc_java_static_call(meth) ); |
|
11584 ins_pipe(pipe_class_call); |
|
11585 %} |
|
11586 |
|
11587 // Schedulable version of call static node. |
|
11588 instruct CallStaticJavaDirectHandle(method meth) %{ |
|
11589 match(CallStaticJava); |
|
11590 effect(USE meth); |
|
11591 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
11592 ins_cost(CALL_COST); |
|
11593 |
|
11594 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); |
|
11595 |
|
11596 format %{ "CALL,static $meth \t// ==> " %} |
|
11597 ins_encode( enc_java_handle_call(meth) ); |
|
11598 ins_pipe(pipe_class_call); |
|
11599 %} |
|
11600 |
|
11601 // Call Java Dynamic Instruction |
|
11602 |
|
11603 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). |
|
11604 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable |
|
11605 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. |
|
11606 // The call destination must still be placed in the constant pool. |
|
11607 instruct CallDynamicJavaDirectSched(method meth) %{ |
|
11608 match(CallDynamicJava); // To get all the data fields we need ... |
|
11609 effect(USE meth); |
|
11610 predicate(false); // ... but never match. |
|
11611 |
|
11612 ins_field_load_ic_hi_node(loadConL_hiNode*); |
|
11613 ins_field_load_ic_node(loadConLNode*); |
|
11614 ins_num_consts(1 /* 1 patchable constant: call destination */); |
|
11615 |
|
11616 format %{ "BL \t// dynamic $meth ==> " %} |
|
11617 size(4); |
|
11618 ins_encode( enc_java_dynamic_call_sched(meth) ); |
|
11619 ins_pipe(pipe_class_call); |
|
11620 %} |
|
11621 |
|
11622 // Schedulable (i.e. postalloc expanded) version of call dynamic java. |
|
11623 // We use postalloc expanded calls if we use inline caches |
|
11624 // and do not update method data. |
|
11625 // |
|
11626 // This instruction has two constants: inline cache (IC) and call destination. |
|
11627 // Loading the inline cache will be postalloc expanded, thus leaving a call with |
|
11628 // one constant. |
|
11629 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ |
|
11630 match(CallDynamicJava); |
|
11631 effect(USE meth); |
|
11632 predicate(UseInlineCaches); |
|
11633 ins_cost(CALL_COST); |
|
11634 |
|
11635 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); |
|
11636 |
|
11637 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} |
|
11638 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); |
|
11639 %} |
|
11640 |
|
11641 // Compound version of call dynamic java |
|
11642 // We use postalloc expanded calls if we use inline caches |
|
11643 // and do not update method data. |
|
11644 instruct CallDynamicJavaDirect(method meth) %{ |
|
11645 match(CallDynamicJava); |
|
11646 effect(USE meth); |
|
11647 predicate(!UseInlineCaches); |
|
11648 ins_cost(CALL_COST); |
|
11649 |
|
11650 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). |
|
11651 ins_num_consts(4); |
|
11652 |
|
11653 format %{ "CALL,dynamic $meth \t// ==> " %} |
|
11654 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); |
|
11655 ins_pipe(pipe_class_call); |
|
11656 %} |
|
11657 |
|
11658 // Call Runtime Instruction |
|
11659 |
|
11660 instruct CallRuntimeDirect(method meth) %{ |
|
11661 match(CallRuntime); |
|
11662 effect(USE meth); |
|
11663 ins_cost(CALL_COST); |
|
11664 |
|
11665 // Enc_java_to_runtime_call needs up to 3 constants: call target, |
|
11666 // env for callee, C-toc. |
|
11667 ins_num_consts(3); |
|
11668 |
|
11669 format %{ "CALL,runtime" %} |
|
11670 ins_encode( enc_java_to_runtime_call(meth) ); |
|
11671 ins_pipe(pipe_class_call); |
|
11672 %} |
|
11673 |
|
11674 // Call Leaf |
|
11675 |
|
11676 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). |
|
11677 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ |
|
11678 effect(DEF dst, USE src); |
|
11679 |
|
11680 ins_num_consts(1); |
|
11681 |
|
11682 format %{ "MTCTR $src" %} |
|
11683 size(4); |
|
11684 ins_encode( enc_leaf_call_mtctr(src) ); |
|
11685 ins_pipe(pipe_class_default); |
|
11686 %} |
|
11687 |
|
11688 // Used by postalloc expand of CallLeafDirect_Ex (actual call). |
|
11689 instruct CallLeafDirect(method meth) %{ |
|
11690 match(CallLeaf); // To get the data all the data fields we need ... |
|
11691 effect(USE meth); |
|
11692 predicate(false); // but never match. |
|
11693 |
|
11694 format %{ "BCTRL \t// leaf call $meth ==> " %} |
|
11695 size(4); |
|
11696 ins_encode %{ |
|
11697 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); |
|
11698 __ bctrl(); |
|
11699 %} |
|
11700 ins_pipe(pipe_class_call); |
|
11701 %} |
|
11702 |
|
11703 // postalloc expand of CallLeafDirect. |
|
11704 // Load adress to call from TOC, then bl to it. |
|
11705 instruct CallLeafDirect_Ex(method meth) %{ |
|
11706 match(CallLeaf); |
|
11707 effect(USE meth); |
|
11708 ins_cost(CALL_COST); |
|
11709 |
|
11710 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, |
|
11711 // env for callee, C-toc. |
|
11712 ins_num_consts(3); |
|
11713 |
|
11714 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} |
|
11715 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); |
|
11716 %} |
|
11717 |
|
11718 // Call runtime without safepoint - same as CallLeaf. |
|
11719 // postalloc expand of CallLeafNoFPDirect. |
|
11720 // Load adress to call from TOC, then bl to it. |
|
11721 instruct CallLeafNoFPDirect_Ex(method meth) %{ |
|
11722 match(CallLeafNoFP); |
|
11723 effect(USE meth); |
|
11724 ins_cost(CALL_COST); |
|
11725 |
|
11726 // Enc_java_to_runtime_call needs up to 3 constants: call target, |
|
11727 // env for callee, C-toc. |
|
11728 ins_num_consts(3); |
|
11729 |
|
11730 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} |
|
11731 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); |
|
11732 %} |
|
11733 |
|
11734 // Tail Call; Jump from runtime stub to Java code. |
|
11735 // Also known as an 'interprocedural jump'. |
|
11736 // Target of jump will eventually return to caller. |
|
11737 // TailJump below removes the return address. |
|
11738 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ |
|
11739 match(TailCall jump_target method_oop); |
|
11740 ins_cost(CALL_COST); |
|
11741 |
|
11742 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" |
|
11743 "BCTR \t// tail call" %} |
|
11744 size(8); |
|
11745 ins_encode %{ |
|
11746 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11747 __ mtctr($jump_target$$Register); |
|
11748 __ bctr(); |
|
11749 %} |
|
11750 ins_pipe(pipe_class_call); |
|
11751 %} |
|
11752 |
|
11753 // Return Instruction |
|
11754 instruct Ret() %{ |
|
11755 match(Return); |
|
11756 format %{ "BLR \t// branch to link register" %} |
|
11757 size(4); |
|
11758 ins_encode %{ |
|
11759 // TODO: PPC port $archOpcode(ppc64Opcode_blr); |
|
11760 // LR is restored in MachEpilogNode. Just do the RET here. |
|
11761 __ blr(); |
|
11762 %} |
|
11763 ins_pipe(pipe_class_default); |
|
11764 %} |
|
11765 |
|
11766 // Tail Jump; remove the return address; jump to target. |
|
11767 // TailCall above leaves the return address around. |
|
11768 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). |
|
11769 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a |
|
11770 // "restore" before this instruction (in Epilogue), we need to materialize it |
|
11771 // in %i0. |
|
11772 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ |
|
11773 match(TailJump jump_target ex_oop); |
|
11774 ins_cost(CALL_COST); |
|
11775 |
|
11776 format %{ "LD R4_ARG2 = LR\n\t" |
|
11777 "MTCTR $jump_target\n\t" |
|
11778 "BCTR \t// TailJump, exception oop: $ex_oop" %} |
|
11779 size(12); |
|
11780 ins_encode %{ |
|
11781 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11782 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); |
|
11783 __ mtctr($jump_target$$Register); |
|
11784 __ bctr(); |
|
11785 %} |
|
11786 ins_pipe(pipe_class_call); |
|
11787 %} |
|
11788 |
|
11789 // Create exception oop: created by stack-crawling runtime code. |
|
11790 // Created exception is now available to this handler, and is setup |
|
11791 // just prior to jumping to this handler. No code emitted. |
|
11792 instruct CreateException(rarg1RegP ex_oop) %{ |
|
11793 match(Set ex_oop (CreateEx)); |
|
11794 ins_cost(0); |
|
11795 |
|
11796 format %{ " -- \t// exception oop; no code emitted" %} |
|
11797 size(0); |
|
11798 ins_encode( /*empty*/ ); |
|
11799 ins_pipe(pipe_class_default); |
|
11800 %} |
|
11801 |
|
11802 // Rethrow exception: The exception oop will come in the first |
|
11803 // argument position. Then JUMP (not call) to the rethrow stub code. |
|
11804 instruct RethrowException() %{ |
|
11805 match(Rethrow); |
|
11806 ins_cost(CALL_COST); |
|
11807 |
|
11808 format %{ "Jmp rethrow_stub" %} |
|
11809 ins_encode %{ |
|
11810 // TODO: PPC port $archOpcode(ppc64Opcode_compound); |
|
11811 cbuf.set_insts_mark(); |
|
11812 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); |
|
11813 %} |
|
11814 ins_pipe(pipe_class_call); |
|
11815 %} |
|
11816 |
|
11817 // Die now. |
|
11818 instruct ShouldNotReachHere() %{ |
|
11819 match(Halt); |
|
11820 ins_cost(CALL_COST); |
|
11821 |
|
11822 format %{ "ShouldNotReachHere" %} |
|
11823 size(4); |
|
11824 ins_encode %{ |
|
11825 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); |
|
11826 __ trap_should_not_reach_here(); |
|
11827 %} |
|
11828 ins_pipe(pipe_class_default); |
|
11829 %} |
|
11830 |
|
11831 // This name is KNOWN by the ADLC and cannot be changed. The ADLC |
|
11832 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. |
|
11833 // Get a DEF on threadRegP, no costs, no encoding, use |
|
11834 // 'ins_should_rematerialize(true)' to avoid spilling. |
|
11835 instruct tlsLoadP(threadRegP dst) %{ |
|
11836 match(Set dst (ThreadLocal)); |
|
11837 ins_cost(0); |
|
11838 |
|
11839 ins_should_rematerialize(true); |
|
11840 |
|
11841 format %{ " -- \t// $dst=Thread::current(), empty" %} |
|
11842 size(0); |
|
11843 ins_encode( /*empty*/ ); |
|
11844 ins_pipe(pipe_class_empty); |
|
11845 %} |
|
11846 |
|
11847 //---Some PPC specific nodes--------------------------------------------------- |
|
11848 |
|
11849 // Stop a group. |
|
11850 instruct endGroup() %{ |
|
11851 ins_cost(0); |
|
11852 |
|
11853 ins_is_nop(true); |
|
11854 |
|
11855 format %{ "End Bundle (ori r1, r1, 0)" %} |
|
11856 size(4); |
|
11857 ins_encode %{ |
|
11858 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); |
|
11859 __ endgroup(); |
|
11860 %} |
|
11861 ins_pipe(pipe_class_default); |
|
11862 %} |
|
11863 |
|
11864 // Nop instructions |
|
11865 |
|
11866 instruct fxNop() %{ |
|
11867 ins_cost(0); |
|
11868 |
|
11869 ins_is_nop(true); |
|
11870 |
|
11871 format %{ "fxNop" %} |
|
11872 size(4); |
|
11873 ins_encode %{ |
|
11874 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
11875 __ nop(); |
|
11876 %} |
|
11877 ins_pipe(pipe_class_default); |
|
11878 %} |
|
11879 |
|
11880 instruct fpNop0() %{ |
|
11881 ins_cost(0); |
|
11882 |
|
11883 ins_is_nop(true); |
|
11884 |
|
11885 format %{ "fpNop0" %} |
|
11886 size(4); |
|
11887 ins_encode %{ |
|
11888 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
11889 __ fpnop0(); |
|
11890 %} |
|
11891 ins_pipe(pipe_class_default); |
|
11892 %} |
|
11893 |
|
11894 instruct fpNop1() %{ |
|
11895 ins_cost(0); |
|
11896 |
|
11897 ins_is_nop(true); |
|
11898 |
|
11899 format %{ "fpNop1" %} |
|
11900 size(4); |
|
11901 ins_encode %{ |
|
11902 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); |
|
11903 __ fpnop1(); |
|
11904 %} |
|
11905 ins_pipe(pipe_class_default); |
|
11906 %} |
|
11907 |
|
11908 instruct brNop0() %{ |
|
11909 ins_cost(0); |
|
11910 size(4); |
|
11911 format %{ "brNop0" %} |
|
11912 ins_encode %{ |
|
11913 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); |
|
11914 __ brnop0(); |
|
11915 %} |
|
11916 ins_is_nop(true); |
|
11917 ins_pipe(pipe_class_default); |
|
11918 %} |
|
11919 |
|
11920 instruct brNop1() %{ |
|
11921 ins_cost(0); |
|
11922 |
|
11923 ins_is_nop(true); |
|
11924 |
|
11925 format %{ "brNop1" %} |
|
11926 size(4); |
|
11927 ins_encode %{ |
|
11928 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); |
|
11929 __ brnop1(); |
|
11930 %} |
|
11931 ins_pipe(pipe_class_default); |
|
11932 %} |
|
11933 |
|
11934 instruct brNop2() %{ |
|
11935 ins_cost(0); |
|
11936 |
|
11937 ins_is_nop(true); |
|
11938 |
|
11939 format %{ "brNop2" %} |
|
11940 size(4); |
|
11941 ins_encode %{ |
|
11942 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); |
|
11943 __ brnop2(); |
|
11944 %} |
|
11945 ins_pipe(pipe_class_default); |
|
11946 %} |
|
11947 |
|
11948 //----------PEEPHOLE RULES----------------------------------------------------- |
|
11949 // These must follow all instruction definitions as they use the names |
|
11950 // defined in the instructions definitions. |
|
11951 // |
|
11952 // peepmatch ( root_instr_name [preceeding_instruction]* ); |
|
11953 // |
|
11954 // peepconstraint %{ |
|
11955 // (instruction_number.operand_name relational_op instruction_number.operand_name |
|
11956 // [, ...] ); |
|
11957 // // instruction numbers are zero-based using left to right order in peepmatch |
|
11958 // |
|
11959 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); |
|
11960 // // provide an instruction_number.operand_name for each operand that appears |
|
11961 // // in the replacement instruction's match rule |
|
11962 // |
|
11963 // ---------VM FLAGS--------------------------------------------------------- |
|
11964 // |
|
11965 // All peephole optimizations can be turned off using -XX:-OptoPeephole |
|
11966 // |
|
11967 // Each peephole rule is given an identifying number starting with zero and |
|
11968 // increasing by one in the order seen by the parser. An individual peephole |
|
11969 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# |
|
11970 // on the command-line. |
|
11971 // |
|
11972 // ---------CURRENT LIMITATIONS---------------------------------------------- |
|
11973 // |
|
11974 // Only match adjacent instructions in same basic block |
|
11975 // Only equality constraints |
|
11976 // Only constraints between operands, not (0.dest_reg == EAX_enc) |
|
11977 // Only one replacement instruction |
|
11978 // |
|
11979 // ---------EXAMPLE---------------------------------------------------------- |
|
11980 // |
|
11981 // // pertinent parts of existing instructions in architecture description |
|
11982 // instruct movI(eRegI dst, eRegI src) %{ |
|
11983 // match(Set dst (CopyI src)); |
|
11984 // %} |
|
11985 // |
|
11986 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ |
|
11987 // match(Set dst (AddI dst src)); |
|
11988 // effect(KILL cr); |
|
11989 // %} |
|
11990 // |
|
11991 // // Change (inc mov) to lea |
|
11992 // peephole %{ |
|
11993 // // increment preceeded by register-register move |
|
11994 // peepmatch ( incI_eReg movI ); |
|
11995 // // require that the destination register of the increment |
|
11996 // // match the destination register of the move |
|
11997 // peepconstraint ( 0.dst == 1.dst ); |
|
11998 // // construct a replacement instruction that sets |
|
11999 // // the destination to ( move's source register + one ) |
|
12000 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
12001 // %} |
|
12002 // |
|
12003 // Implementation no longer uses movX instructions since |
|
12004 // machine-independent system no longer uses CopyX nodes. |
|
12005 // |
|
12006 // peephole %{ |
|
12007 // peepmatch ( incI_eReg movI ); |
|
12008 // peepconstraint ( 0.dst == 1.dst ); |
|
12009 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
12010 // %} |
|
12011 // |
|
12012 // peephole %{ |
|
12013 // peepmatch ( decI_eReg movI ); |
|
12014 // peepconstraint ( 0.dst == 1.dst ); |
|
12015 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
12016 // %} |
|
12017 // |
|
12018 // peephole %{ |
|
12019 // peepmatch ( addI_eReg_imm movI ); |
|
12020 // peepconstraint ( 0.dst == 1.dst ); |
|
12021 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); |
|
12022 // %} |
|
12023 // |
|
12024 // peephole %{ |
|
12025 // peepmatch ( addP_eReg_imm movP ); |
|
12026 // peepconstraint ( 0.dst == 1.dst ); |
|
12027 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); |
|
12028 // %} |
|
12029 |
|
12030 // // Change load of spilled value to only a spill |
|
12031 // instruct storeI(memory mem, eRegI src) %{ |
|
12032 // match(Set mem (StoreI mem src)); |
|
12033 // %} |
|
12034 // |
|
12035 // instruct loadI(eRegI dst, memory mem) %{ |
|
12036 // match(Set dst (LoadI mem)); |
|
12037 // %} |
|
12038 // |
|
12039 peephole %{ |
|
12040 peepmatch ( loadI storeI ); |
|
12041 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); |
|
12042 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); |
|
12043 %} |
|
12044 |
|
12045 peephole %{ |
|
12046 peepmatch ( loadL storeL ); |
|
12047 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); |
|
12048 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); |
|
12049 %} |
|
12050 |
|
12051 peephole %{ |
|
12052 peepmatch ( loadP storeP ); |
|
12053 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); |
|
12054 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); |
|
12055 %} |
|
12056 |
|
12057 //----------SMARTSPILL RULES--------------------------------------------------- |
|
12058 // These must follow all instruction definitions as they use the names |
|
12059 // defined in the instructions definitions. |