jdk-sandbox: comparison src/hotspot/cpu/sparc/assembler

equal deleted inserted replaced

-:e4a5b535c0d2
+:f59f0e51ef8a
 saved_op3    = 0x31,
 fpop1_op3    = 0x34,
 fpop2_op3    = 0x35,
 impdep1_op3  = 0x36,
+addx_op3     = 0x36,
 aes3_op3     = 0x36,
 sha_op3      = 0x36,
 bmask_op3    = 0x36,
 bshuffle_op3   = 0x36,
 alignaddr_op3  = 0x36,
 flog3_op3    = 0x36,
 edge_op3     = 0x36,
 fzero_op3    = 0x36,
 fsrc_op3     = 0x36,
 fnot_op3     = 0x36,
+mpmul_op3    = 0x36,
+umulx_op3    = 0x36,
 xmulx_op3    = 0x36,
 crc32c_op3   = 0x36,
 impdep2_op3  = 0x37,
 stpartialf_op3 = 0x37,
 jmpl_op3     = 0x38,
 fmovd_opf          = 0x02,
 fnegs_opf          = 0x05,
 fnegd_opf          = 0x06,
+addxc_opf          = 0x11,
+addxccc_opf        = 0x13,
+umulxhi_opf        = 0x16,
 alignaddr_opf      = 0x18,
 bmask_opf          = 0x19,
 fadds_opf          = 0x41,
 faddd_opf          = 0x42,
 sha1_opf           = 0x141,
 sha256_opf         = 0x142,
 sha512_opf         = 0x143,
-crc32c_opf         = 0x147
+crc32c_opf         = 0x147,
+mpmul_opf          = 0x148
 };
 enum op5s {
 aes_eround01_op5   = 0x00,
 aes_eround23_op5   = 0x01,
 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 assert((x & 3) == 0, "not word aligned");
 assert_signed_range(x, nbits + 2);
 }
-static void assert_unsigned_const(int x, int nbits) {
+static void assert_unsigned_range(int x, int nbits) {
 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
 }
 // fields: note bits numbered from LSB = 0, fields known by inclusive bit range
 static int simm(int x, int nbits) {
 assert_signed_range(x, nbits);
 return x & ((1 << nbits) - 1);
 }
+// unsigned immediate, in low bits, at most nbits long.
+static int uimm(int x, int nbits) {
+assert_unsigned_range(x, nbits);
+return x & ((1 << nbits) - 1);
+}
 // compute inverse of wdisp16
 static intptr_t inv_wdisp16(int x, intptr_t pos) {
 int lo = x & ((1 << 14) - 1);
 int hi = (x >> 20) & 3;
 if (hi >= 2) hi |= ~1;
 // CRC32C instruction supported only on certain processors
 static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
 // FMAf instructions supported only on certain processors
 static void fmaf_only() { assert(VM_Version::has_fmaf(), "This instruction only works on SPARC with FMAf"); }
+// MPMUL instruction supported only on certain processors
+static void mpmul_only() { assert( VM_Version::has_mpmul(), "This instruction only works on SPARC with MPMUL"); }
 // instruction only in VIS1
 static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
 // instruction only in VIS2
 validate_no_pipeline_hazards();
 #endif
 AbstractAssembler::flush();
 }
-inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
+inline void emit_int32(int32_t);  // shadows AbstractAssembler::emit_int32
-inline void emit_data(int);
+inline void emit_data(int32_t);
-inline void emit_data(int, RelocationHolder const &rspec);
+inline void emit_data(int32_t, RelocationHolder const&);
-inline void emit_data(int, relocInfo::relocType rtype);
+inline void emit_data(int32_t, relocInfo::relocType rtype);
-// helper for above functions
+// Helper for the above functions.
 inline void check_delay();
 public:
 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d,
 RelocationHolder const &rspec = RelocationHolder());
+inline void ldd(Register s1, Register s2, FloatRegister d);
+inline void ldd(Register s1, int simm13a, FloatRegister d);
 inline void ldfsr(Register s1, Register s2);
 inline void ldfsr(Register s1, int simm13a);
 inline void ldxfsr(Register s1, Register s2);
 inline void ldxfsr(Register s1, int simm13a);
 inline void lduh(Register s1, int simm13a, Register d);
 inline void lduw(Register s1, Register s2, Register d);
 inline void lduw(Register s1, int simm13a, Register d);
 inline void ldx(Register s1, Register s2, Register d);
 inline void ldx(Register s1, int simm13a, Register d);
-inline void ldd(Register s1, Register s2, Register d);
-inline void ldd(Register s1, int simm13a, Register d);
 // pp 177
 inline void ldsba(Register s1, Register s2, int ia, Register d);
 inline void ldsba(Register s1, int simm13a,         Register d);
 // pp 222
 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
+inline void std(FloatRegister d, Register s1, Register s2);
+inline void std(FloatRegister d, Register s1, int simm13a);
 inline void stfsr(Register s1, Register s2);
 inline void stfsr(Register s1, int simm13a);
 inline void stxfsr(Register s1, Register s2);
 inline void stxfsr(Register s1, int simm13a);
 inline void sth(Register d, Register s1, int simm13a);
 inline void stw(Register d, Register s1, Register s2);
 inline void stw(Register d, Register s1, int simm13a);
 inline void stx(Register d, Register s1, Register s2);
 inline void stx(Register d, Register s1, int simm13a);
-inline void std(Register d, Register s1, Register s2);
-inline void std(Register d, Register s1, int simm13a);
 // pp 177
 inline void stba(Register d, Register s1, Register s2, int ia);
 inline void stba(Register d, Register s1, int simm13a);
 inline void bmask(Register s1, Register s2, Register d);
 inline void bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d);
 // VIS3 instructions
+inline void addxc(Register s1, Register s2, Register d);
+inline void addxccc(Register s1, Register s2, Register d);
 inline void movstosw(FloatRegister s, Register d);
 inline void movstouw(FloatRegister s, Register d);
 inline void movdtox(FloatRegister s, Register d);
 inline void movwtos(Register s, FloatRegister d);
 inline void movxtod(Register s, FloatRegister d);
 inline void xmulx(Register s1, Register s2, Register d);
 inline void xmulxhi(Register s1, Register s2, Register d);
+inline void umulxhi(Register s1, Register s2, Register d);
 // Crypto SHA instructions
 inline void sha1();
 inline void sha256();
 inline void sha512();
 // CRC32C instruction
 inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d);
+// MPMUL instruction
+inline void mpmul(int uimm5);
 // Creation
 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 #ifdef VALIDATE_PIPELINE
 _delay_state  = NoDelay;

changeset 47561	f59f0e51ef8a
parent 47216	71c04702a3d5
child 47563	bbd116ac5ef3