1 /*

     2  * Copyright 1997-2008 Sun Microsystems, Inc.  All Rights Reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

    20  * CA 95054 USA or visit www.sun.com if you need additional information or

    21  * have any questions.

    22  *

    23  */

    24 

    25 #include "incls/_precompiled.incl"

    26 #include "incls/_assembler_x86_32.cpp.incl"

    27 

    28 // Implementation of AddressLiteral

    29 

    30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {

    31   _is_lval = false;

    32   _target = target;

    33   switch (rtype) {

    34   case relocInfo::oop_type:

    35     // Oops are a special case. Normally they would be their own section

    36     // but in cases like icBuffer they are literals in the code stream that

    37     // we don't have a section for. We use none so that we get a literal address

    38     // which is always patchable.

    39     break;

    40   case relocInfo::external_word_type:

    41     _rspec = external_word_Relocation::spec(target);

    42     break;

    43   case relocInfo::internal_word_type:

    44     _rspec = internal_word_Relocation::spec(target);

    45     break;

    46   case relocInfo::opt_virtual_call_type:

    47     _rspec = opt_virtual_call_Relocation::spec();

    48     break;

    49   case relocInfo::static_call_type:

    50     _rspec = static_call_Relocation::spec();

    51     break;

    52   case relocInfo::runtime_call_type:

    53     _rspec = runtime_call_Relocation::spec();

    54     break;

    55   case relocInfo::poll_type:

    56   case relocInfo::poll_return_type:

    57     _rspec = Relocation::spec_simple(rtype);

    58     break;

    59   case relocInfo::none:

    60     break;

    61   default:

    62     ShouldNotReachHere();

    63     break;

    64   }

    65 }

    66 

    67 // Implementation of Address

    68 

    69 Address Address::make_array(ArrayAddress adr) {

    70 #ifdef _LP64

    71   // Not implementable on 64bit machines

    72   // Should have been handled higher up the call chain.

    73   ShouldNotReachHere();

    74 #else

    75   AddressLiteral base = adr.base();

    76   Address index = adr.index();

    77   assert(index._disp == 0, "must not have disp"); // maybe it can?

    78   Address array(index._base, index._index, index._scale, (intptr_t) base.target());

    79   array._rspec = base._rspec;

    80   return array;

    81 #endif // _LP64

    82 }

    83 

    84 #ifndef _LP64

    85 

    86 // exceedingly dangerous constructor

    87 Address::Address(address loc, RelocationHolder spec) {

    88   _base  = noreg;

    89   _index = noreg;

    90   _scale = no_scale;

    91   _disp  = (intptr_t) loc;

    92   _rspec = spec;

    93 }

    94 #endif // _LP64

    95 

    96 // Convert the raw encoding form into the form expected by the constructor for

    97 // Address.  An index of 4 (rsp) corresponds to having no index, so convert

    98 // that to noreg for the Address constructor.

    99 Address Address::make_raw(int base, int index, int scale, int disp) {

   100   bool valid_index = index != rsp->encoding();

   101   if (valid_index) {

   102     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));

   103     return madr;

   104   } else {

   105     Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));

   106     return madr;

   107   }

   108 }

   109 

   110 // Implementation of Assembler

   111 

   112 int AbstractAssembler::code_fill_byte() {

   113   return (u_char)'\xF4'; // hlt

   114 }

   115 

   116 // make this go away someday

   117 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {

   118   if (rtype == relocInfo::none)

   119         emit_long(data);

   120   else  emit_data(data, Relocation::spec_simple(rtype), format);

   121 }

   122 

   123 

   124 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {

   125   assert(imm32_operand == 0, "default format must be imm32 in this file");

   126   assert(inst_mark() != NULL, "must be inside InstructionMark");

   127   if (rspec.type() !=  relocInfo::none) {

   128     #ifdef ASSERT

   129       check_relocation(rspec, format);

   130     #endif

   131     // Do not use AbstractAssembler::relocate, which is not intended for

   132     // embedded words.  Instead, relocate to the enclosing instruction.

   133 

   134     // hack. call32 is too wide for mask so use disp32

   135     if (format == call32_operand)

   136       code_section()->relocate(inst_mark(), rspec, disp32_operand);

   137     else

   138       code_section()->relocate(inst_mark(), rspec, format);

   139   }

   140   emit_long(data);

   141 }

   142 

   143 

   144 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {

   145   assert(dst->has_byte_register(), "must have byte register");

   146   assert(isByte(op1) && isByte(op2), "wrong opcode");

   147   assert(isByte(imm8), "not a byte");

   148   assert((op1 & 0x01) == 0, "should be 8bit operation");

   149   emit_byte(op1);

   150   emit_byte(op2 | dst->encoding());

   151   emit_byte(imm8);

   152 }

   153 

   154 

   155 void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {

   156   assert(isByte(op1) && isByte(op2), "wrong opcode");

   157   assert((op1 & 0x01) == 1, "should be 32bit operation");

   158   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

   159   if (is8bit(imm32)) {

   160     emit_byte(op1 | 0x02); // set sign bit

   161     emit_byte(op2 | dst->encoding());

   162     emit_byte(imm32 & 0xFF);

   163   } else {

   164     emit_byte(op1);

   165     emit_byte(op2 | dst->encoding());

   166     emit_long(imm32);

   167   }

   168 }

   169 

   170 // immediate-to-memory forms

   171 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) {

   172   assert((op1 & 0x01) == 1, "should be 32bit operation");

   173   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

   174   if (is8bit(imm32)) {

   175     emit_byte(op1 | 0x02); // set sign bit

   176     emit_operand(rm,adr);

   177     emit_byte(imm32 & 0xFF);

   178   } else {

   179     emit_byte(op1);

   180     emit_operand(rm,adr);

   181     emit_long(imm32);

   182   }

   183 }

   184 

   185 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {

   186   assert(isByte(op1) && isByte(op2), "wrong opcode");

   187   assert((op1 & 0x01) == 1, "should be 32bit operation");

   188   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

   189   InstructionMark im(this);

   190   emit_byte(op1);

   191   emit_byte(op2 | dst->encoding());

   192   emit_data((int)obj, relocInfo::oop_type, 0);

   193 }

   194 

   195 

   196 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {

   197   assert(isByte(op1) && isByte(op2), "wrong opcode");

   198   emit_byte(op1);

   199   emit_byte(op2 | dst->encoding() << 3 | src->encoding());

   200 }

   201 

   202 

   203 void Assembler::emit_operand(Register reg,

   204                              Register base,

   205                              Register index,

   206                              Address::ScaleFactor scale,

   207                              int disp,

   208                              RelocationHolder const& rspec) {

   209 

   210   relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();

   211   if (base->is_valid()) {

   212     if (index->is_valid()) {

   213       assert(scale != Address::no_scale, "inconsistent address");

   214       // [base + index*scale + disp]

   215       if (disp == 0 && rtype == relocInfo::none && base != rbp) {

   216         // [base + index*scale]

   217         // [00 reg 100][ss index base]

   218         assert(index != rsp, "illegal addressing mode");

   219         emit_byte(0x04 | reg->encoding() << 3);

   220         emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());

   221       } else if (is8bit(disp) && rtype == relocInfo::none) {

   222         // [base + index*scale + imm8]

   223         // [01 reg 100][ss index base] imm8

   224         assert(index != rsp, "illegal addressing mode");

   225         emit_byte(0x44 | reg->encoding() << 3);

   226         emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());

   227         emit_byte(disp & 0xFF);

   228       } else {

   229         // [base + index*scale + imm32]

   230         // [10 reg 100][ss index base] imm32

   231         assert(index != rsp, "illegal addressing mode");

   232         emit_byte(0x84 | reg->encoding() << 3);

   233         emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());

   234         emit_data(disp, rspec, disp32_operand);

   235       }

   236     } else if (base == rsp) {

   237       // [esp + disp]

   238       if (disp == 0 && rtype == relocInfo::none) {

   239         // [esp]

   240         // [00 reg 100][00 100 100]

   241         emit_byte(0x04 | reg->encoding() << 3);

   242         emit_byte(0x24);

   243       } else if (is8bit(disp) && rtype == relocInfo::none) {

   244         // [esp + imm8]

   245         // [01 reg 100][00 100 100] imm8

   246         emit_byte(0x44 | reg->encoding() << 3);

   247         emit_byte(0x24);

   248         emit_byte(disp & 0xFF);

   249       } else {

   250         // [esp + imm32]

   251         // [10 reg 100][00 100 100] imm32

   252         emit_byte(0x84 | reg->encoding() << 3);

   253         emit_byte(0x24);

   254         emit_data(disp, rspec, disp32_operand);

   255       }

   256     } else {

   257       // [base + disp]

   258       assert(base != rsp, "illegal addressing mode");

   259       if (disp == 0 && rtype == relocInfo::none && base != rbp) {

   260         // [base]

   261         // [00 reg base]

   262         assert(base != rbp, "illegal addressing mode");

   263         emit_byte(0x00 | reg->encoding() << 3 | base->encoding());

   264       } else if (is8bit(disp) && rtype == relocInfo::none) {

   265         // [base + imm8]

   266         // [01 reg base] imm8

   267         emit_byte(0x40 | reg->encoding() << 3 | base->encoding());

   268         emit_byte(disp & 0xFF);

   269       } else {

   270         // [base + imm32]

   271         // [10 reg base] imm32

   272         emit_byte(0x80 | reg->encoding() << 3 | base->encoding());

   273         emit_data(disp, rspec, disp32_operand);

   274       }

   275     }

   276   } else {

   277     if (index->is_valid()) {

   278       assert(scale != Address::no_scale, "inconsistent address");

   279       // [index*scale + disp]

   280       // [00 reg 100][ss index 101] imm32

   281       assert(index != rsp, "illegal addressing mode");

   282       emit_byte(0x04 | reg->encoding() << 3);

   283       emit_byte(scale << 6 | index->encoding() << 3 | 0x05);

   284       emit_data(disp, rspec, disp32_operand);

   285     } else {

   286       // [disp]

   287       // [00 reg 101] imm32

   288       emit_byte(0x05 | reg->encoding() << 3);

   289       emit_data(disp, rspec, disp32_operand);

   290     }

   291   }

   292 }

   293 

   294 // Secret local extension to Assembler::WhichOperand:

   295 #define end_pc_operand (_WhichOperand_limit)

   296 

   297 address Assembler::locate_operand(address inst, WhichOperand which) {

   298   // Decode the given instruction, and return the address of

   299   // an embedded 32-bit operand word.

   300 

   301   // If "which" is disp32_operand, selects the displacement portion

   302   // of an effective address specifier.

   303   // If "which" is imm32_operand, selects the trailing immediate constant.

   304   // If "which" is call32_operand, selects the displacement of a call or jump.

   305   // Caller is responsible for ensuring that there is such an operand,

   306   // and that it is 32 bits wide.

   307 

   308   // If "which" is end_pc_operand, find the end of the instruction.

   309 

   310   address ip = inst;

   311 

   312   debug_only(bool has_imm32 = false);

   313   int tail_size = 0;    // other random bytes (#32, #16, etc.) at end of insn

   314 

   315  again_after_prefix:

   316   switch (0xFF & *ip++) {

   317 

   318   // These convenience macros generate groups of "case" labels for the switch.

   319   #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3

   320   #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \

   321              case (x)+4: case (x)+5: case (x)+6: case (x)+7

   322   #define REP16(x) REP8((x)+0): \

   323               case REP8((x)+8)

   324 

   325   case CS_segment:

   326   case SS_segment:

   327   case DS_segment:

   328   case ES_segment:

   329   case FS_segment:

   330   case GS_segment:

   331     assert(ip == inst+1, "only one prefix allowed");

   332     goto again_after_prefix;

   333 

   334   case 0xFF: // pushl a; decl a; incl a; call a; jmp a

   335   case 0x88: // movb a, r

   336   case 0x89: // movl a, r

   337   case 0x8A: // movb r, a

   338   case 0x8B: // movl r, a

   339   case 0x8F: // popl a

   340     break;

   341 

   342   case 0x68: // pushl #32(oop?)

   343     if (which == end_pc_operand)  return ip + 4;

   344     assert(which == imm32_operand, "pushl has no disp32");

   345     return ip;                  // not produced by emit_operand

   346 

   347   case 0x66: // movw ... (size prefix)

   348     switch (0xFF & *ip++) {

   349     case 0x8B: // movw r, a

   350     case 0x89: // movw a, r

   351       break;

   352     case 0xC7: // movw a, #16

   353       tail_size = 2;  // the imm16

   354       break;

   355     case 0x0F: // several SSE/SSE2 variants

   356       ip--;    // reparse the 0x0F

   357       goto again_after_prefix;

   358     default:

   359       ShouldNotReachHere();

   360     }

   361     break;

   362 

   363   case REP8(0xB8): // movl r, #32(oop?)

   364     if (which == end_pc_operand)  return ip + 4;

   365     assert(which == imm32_operand || which == disp32_operand, "");

   366     return ip;

   367 

   368   case 0x69: // imul r, a, #32

   369   case 0xC7: // movl a, #32(oop?)

   370     tail_size = 4;

   371     debug_only(has_imm32 = true); // has both kinds of operands!

   372     break;

   373 

   374   case 0x0F: // movx..., etc.

   375     switch (0xFF & *ip++) {

   376     case 0x12: // movlps

   377     case 0x28: // movaps

   378     case 0x2E: // ucomiss

   379     case 0x2F: // comiss

   380     case 0x54: // andps

   381     case 0x55: // andnps

   382     case 0x56: // orps

   383     case 0x57: // xorps

   384     case 0x6E: // movd

   385     case 0x7E: // movd

   386     case 0xAE: // ldmxcsr   a

   387       // amd side says it these have both operands but that doesn't

   388       // appear to be true.

   389       // debug_only(has_imm32 = true); // has both kinds of operands!

   390       break;

   391 

   392     case 0xAD: // shrd r, a, %cl

   393     case 0xAF: // imul r, a

   394     case 0xBE: // movsxb r, a

   395     case 0xBF: // movsxw r, a

   396     case 0xB6: // movzxb r, a

   397     case 0xB7: // movzxw r, a

   398     case REP16(0x40): // cmovl cc, r, a

   399     case 0xB0: // cmpxchgb

   400     case 0xB1: // cmpxchg

   401     case 0xC1: // xaddl

   402     case 0xC7: // cmpxchg8

   403     case REP16(0x90): // setcc a

   404       // fall out of the switch to decode the address

   405       break;

   406     case 0xAC: // shrd r, a, #8

   407       tail_size = 1;  // the imm8

   408       break;

   409     case REP16(0x80): // jcc rdisp32

   410       if (which == end_pc_operand)  return ip + 4;

   411       assert(which == call32_operand, "jcc has no disp32 or imm32");

   412       return ip;

   413     default:

   414       ShouldNotReachHere();

   415     }

   416     break;

   417 

   418   case 0x81: // addl a, #32; addl r, #32

   419     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl

   420     // in the case of cmpl, the imm32 might be an oop

   421     tail_size = 4;

   422     debug_only(has_imm32 = true); // has both kinds of operands!

   423     break;

   424 

   425   case 0x85: // test r/m, r

   426     break;

   427 

   428   case 0x83: // addl a, #8; addl r, #8

   429     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl

   430     tail_size = 1;

   431     break;

   432 

   433   case 0x9B:

   434     switch (0xFF & *ip++) {

   435     case 0xD9: // fnstcw a

   436       break;

   437     default:

   438       ShouldNotReachHere();

   439     }

   440     break;

   441 

   442   case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a

   443   case REP4(0x10): // adc...

   444   case REP4(0x20): // and...

   445   case REP4(0x30): // xor...

   446   case REP4(0x08): // or...

   447   case REP4(0x18): // sbb...

   448   case REP4(0x28): // sub...

   449   case REP4(0x38): // cmp...

   450   case 0xF7: // mull a

   451   case 0x8D: // leal r, a

   452   case 0x87: // xchg r, a

   453     break;

   454 

   455   case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8

   456   case 0xC6: // movb a, #8

   457   case 0x80: // cmpb a, #8

   458   case 0x6B: // imul r, a, #8

   459     tail_size = 1; // the imm8

   460     break;

   461 

   462   case 0xE8: // call rdisp32

   463   case 0xE9: // jmp  rdisp32

   464     if (which == end_pc_operand)  return ip + 4;

   465     assert(which == call32_operand, "call has no disp32 or imm32");

   466     return ip;

   467 

   468   case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1

   469   case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl

   470   case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a

   471   case 0xDD: // fld_d a; fst_d a; fstp_d a

   472   case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a

   473   case 0xDF: // fild_d a; fistp_d a

   474   case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a

   475   case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a

   476   case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a

   477     break;

   478 

   479   case 0xF3:                    // For SSE

   480   case 0xF2:                    // For SSE2

   481     ip++; ip++;

   482     break;

   483 

   484   default:

   485     ShouldNotReachHere();

   486 

   487   #undef REP8

   488   #undef REP16

   489   }

   490 

   491   assert(which != call32_operand, "instruction is not a call, jmp, or jcc");

   492   assert(which != imm32_operand || has_imm32, "instruction has no imm32 field");

   493 

   494   // parse the output of emit_operand

   495   int op2 = 0xFF & *ip++;

   496   int base = op2 & 0x07;

   497   int op3 = -1;

   498   const int b100 = 4;

   499   const int b101 = 5;

   500   if (base == b100 && (op2 >> 6) != 3) {

   501     op3 = 0xFF & *ip++;

   502     base = op3 & 0x07;   // refetch the base

   503   }

   504   // now ip points at the disp (if any)

   505 

   506   switch (op2 >> 6) {

   507   case 0:

   508     // [00 reg  100][ss index base]

   509     // [00 reg  100][00   100  rsp]

   510     // [00 reg base]

   511     // [00 reg  100][ss index  101][disp32]

   512     // [00 reg  101]               [disp32]

   513 

   514     if (base == b101) {

   515       if (which == disp32_operand)

   516         return ip;              // caller wants the disp32

   517       ip += 4;                  // skip the disp32

   518     }

   519     break;

   520 

   521   case 1:

   522     // [01 reg  100][ss index base][disp8]

   523     // [01 reg  100][00   100  rsp][disp8]

   524     // [01 reg base]               [disp8]

   525     ip += 1;                    // skip the disp8

   526     break;

   527 

   528   case 2:

   529     // [10 reg  100][ss index base][disp32]

   530     // [10 reg  100][00   100  rsp][disp32]

   531     // [10 reg base]               [disp32]

   532     if (which == disp32_operand)

   533       return ip;                // caller wants the disp32

   534     ip += 4;                    // skip the disp32

   535     break;

   536 

   537   case 3:

   538     // [11 reg base]  (not a memory addressing mode)

   539     break;

   540   }

   541 

   542   if (which == end_pc_operand) {

   543     return ip + tail_size;

   544   }

   545 

   546   assert(which == imm32_operand, "instruction has only an imm32 field");

   547   return ip;

   548 }

   549 

   550 address Assembler::locate_next_instruction(address inst) {

   551   // Secretly share code with locate_operand:

   552   return locate_operand(inst, end_pc_operand);

   553 }

   554 

   555 

   556 #ifdef ASSERT

   557 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {

   558   address inst = inst_mark();

   559   assert(inst != NULL && inst < pc(), "must point to beginning of instruction");

   560   address opnd;

   561 

   562   Relocation* r = rspec.reloc();

   563   if (r->type() == relocInfo::none) {

   564     return;

   565   } else if (r->is_call() || format == call32_operand) {

   566     // assert(format == imm32_operand, "cannot specify a nonzero format");

   567     opnd = locate_operand(inst, call32_operand);

   568   } else if (r->is_data()) {

   569     assert(format == imm32_operand || format == disp32_operand, "format ok");

   570     opnd = locate_operand(inst, (WhichOperand)format);

   571   } else {

   572     assert(format == imm32_operand, "cannot specify a format");

   573     return;

   574   }

   575   assert(opnd == pc(), "must put operand where relocs can find it");

   576 }

   577 #endif

   578 

   579 

   580 

   581 void Assembler::emit_operand(Register reg, Address adr) {

   582   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);

   583 }

   584 

   585 

   586 void Assembler::emit_farith(int b1, int b2, int i) {

   587   assert(isByte(b1) && isByte(b2), "wrong opcode");

   588   assert(0 <= i &&  i < 8, "illegal stack offset");

   589   emit_byte(b1);

   590   emit_byte(b2 + i);

   591 }

   592 

   593 

   594 void Assembler::pushad() {

   595   emit_byte(0x60);

   596 }

   597 

   598 void Assembler::popad() {

   599   emit_byte(0x61);

   600 }

   601 

   602 void Assembler::pushfd() {

   603   emit_byte(0x9C);

   604 }

   605 

   606 void Assembler::popfd() {

   607   emit_byte(0x9D);

   608 }

   609 

   610 void Assembler::pushl(int imm32) {

   611   emit_byte(0x68);

   612   emit_long(imm32);

   613 }

   614 

   615 #ifndef _LP64

   616 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {

   617   InstructionMark im(this);

   618   emit_byte(0x68);

   619   emit_data(imm32, rspec, 0);

   620 }

   621 #endif // _LP64

   622 

   623 void Assembler::pushl(Register src) {

   624   emit_byte(0x50 | src->encoding());

   625 }

   626 

   627 

   628 void Assembler::pushl(Address src) {

   629   InstructionMark im(this);

   630   emit_byte(0xFF);

   631   emit_operand(rsi, src);

   632 }

   633 

   634 void Assembler::popl(Register dst) {

   635   emit_byte(0x58 | dst->encoding());

   636 }

   637 

   638 

   639 void Assembler::popl(Address dst) {

   640   InstructionMark im(this);

   641   emit_byte(0x8F);

   642   emit_operand(rax, dst);

   643 }

   644 

   645 

   646 void Assembler::prefix(Prefix p) {

   647   a_byte(p);

   648 }

   649 

   650 

   651 void Assembler::movb(Register dst, Address src) {

   652   assert(dst->has_byte_register(), "must have byte register");

   653   InstructionMark im(this);

   654   emit_byte(0x8A);

   655   emit_operand(dst, src);

   656 }

   657 

   658 

   659 void Assembler::movb(Address dst, int imm8) {

   660   InstructionMark im(this);

   661   emit_byte(0xC6);

   662   emit_operand(rax, dst);

   663   emit_byte(imm8);

   664 }

   665 

   666 

   667 void Assembler::movb(Address dst, Register src) {

   668   assert(src->has_byte_register(), "must have byte register");

   669   InstructionMark im(this);

   670   emit_byte(0x88);

   671   emit_operand(src, dst);

   672 }

   673 

   674 

   675 void Assembler::movw(Address dst, int imm16) {

   676   InstructionMark im(this);

   677 

   678   emit_byte(0x66); // switch to 16-bit mode

   679   emit_byte(0xC7);

   680   emit_operand(rax, dst);

   681   emit_word(imm16);

   682 }

   683 

   684 

   685 void Assembler::movw(Register dst, Address src) {

   686   InstructionMark im(this);

   687   emit_byte(0x66);

   688   emit_byte(0x8B);

   689   emit_operand(dst, src);

   690 }

   691 

   692 

   693 void Assembler::movw(Address dst, Register src) {

   694   InstructionMark im(this);

   695   emit_byte(0x66);

   696   emit_byte(0x89);

   697   emit_operand(src, dst);

   698 }

   699 

   700 

   701 void Assembler::movl(Register dst, int imm32) {

   702   emit_byte(0xB8 | dst->encoding());

   703   emit_long(imm32);

   704 }

   705 

   706 #ifndef _LP64

   707 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {

   708 

   709   InstructionMark im(this);

   710   emit_byte(0xB8 | dst->encoding());

   711   emit_data((int)imm32, rspec, 0);

   712 }

   713 #endif // _LP64

   714 

   715 void Assembler::movl(Register dst, Register src) {

   716   emit_byte(0x8B);

   717   emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());

   718 }

   719 

   720 

   721 void Assembler::movl(Register dst, Address src) {

   722   InstructionMark im(this);

   723   emit_byte(0x8B);

   724   emit_operand(dst, src);

   725 }

   726 

   727 

   728 void Assembler::movl(Address dst, int imm32) {

   729   InstructionMark im(this);

   730   emit_byte(0xC7);

   731   emit_operand(rax, dst);

   732   emit_long(imm32);

   733 }

   734 

   735 #ifndef _LP64

   736 void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {

   737   InstructionMark im(this);

   738   emit_byte(0xC7);

   739   emit_operand(rax, dst);

   740   emit_data((int)imm32, rspec, 0);

   741 }

   742 #endif // _LP64

   743 

   744 void Assembler::movl(Address dst, Register src) {

   745   InstructionMark im(this);

   746   emit_byte(0x89);

   747   emit_operand(src, dst);

   748 }

   749 

   750 void Assembler::movsxb(Register dst, Address src) {

   751   InstructionMark im(this);

   752   emit_byte(0x0F);

   753   emit_byte(0xBE);

   754   emit_operand(dst, src);

   755 }

   756 

   757 void Assembler::movsxb(Register dst, Register src) {

   758   assert(src->has_byte_register(), "must have byte register");

   759   emit_byte(0x0F);

   760   emit_byte(0xBE);

   761   emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());

   762 }

   763 

   764 

   765 void Assembler::movsxw(Register dst, Address src) {

   766   InstructionMark im(this);

   767   emit_byte(0x0F);

   768   emit_byte(0xBF);

   769   emit_operand(dst, src);

   770 }

   771 

   772 

   773 void Assembler::movsxw(Register dst, Register src) {

   774   emit_byte(0x0F);

   775   emit_byte(0xBF);

   776   emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());

   777 }

   778 

   779 

   780 void Assembler::movzxb(Register dst, Address src) {

   781   InstructionMark im(this);

   782   emit_byte(0x0F);

   783   emit_byte(0xB6);

   784   emit_operand(dst, src);

   785 }

   786 

   787 

   788 void Assembler::movzxb(Register dst, Register src) {

   789   assert(src->has_byte_register(), "must have byte register");

   790   emit_byte(0x0F);

   791   emit_byte(0xB6);

   792   emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());

   793 }

   794 

   795 

   796 void Assembler::movzxw(Register dst, Address src) {

   797   InstructionMark im(this);

   798   emit_byte(0x0F);

   799   emit_byte(0xB7);

   800   emit_operand(dst, src);

   801 }

   802 

   803 

   804 void Assembler::movzxw(Register dst, Register src) {

   805   emit_byte(0x0F);

   806   emit_byte(0xB7);

   807   emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());

   808 }

   809 

   810 

   811 void Assembler::cmovl(Condition cc, Register dst, Register src) {

   812   guarantee(VM_Version::supports_cmov(), "illegal instruction");

   813   emit_byte(0x0F);

   814   emit_byte(0x40 | cc);

   815   emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());

   816 }

   817 

   818 

   819 void Assembler::cmovl(Condition cc, Register dst, Address src) {

   820   guarantee(VM_Version::supports_cmov(), "illegal instruction");

   821   // The code below seems to be wrong - however the manual is inconclusive

   822   // do not use for now (remember to enable all callers when fixing this)

   823   Unimplemented();

   824   // wrong bytes?

   825   InstructionMark im(this);

   826   emit_byte(0x0F);

   827   emit_byte(0x40 | cc);

   828   emit_operand(dst, src);

   829 }

   830 

   831 

   832 void Assembler::prefetcht0(Address src) {

   833   assert(VM_Version::supports_sse(), "must support");

   834   InstructionMark im(this);

   835   emit_byte(0x0F);

   836   emit_byte(0x18);

   837   emit_operand(rcx, src); // 1, src

   838 }

   839 

   840 

   841 void Assembler::prefetcht1(Address src) {

   842   assert(VM_Version::supports_sse(), "must support");

   843   InstructionMark im(this);

   844   emit_byte(0x0F);

   845   emit_byte(0x18);

   846   emit_operand(rdx, src); // 2, src

   847 }

   848 

   849 

   850 void Assembler::prefetcht2(Address src) {

   851   assert(VM_Version::supports_sse(), "must support");

   852   InstructionMark im(this);

   853   emit_byte(0x0F);

   854   emit_byte(0x18);

   855   emit_operand(rbx, src); // 3, src

   856 }

   857 

   858 

   859 void Assembler::prefetchnta(Address src) {

   860   assert(VM_Version::supports_sse2(), "must support");

   861   InstructionMark im(this);

   862   emit_byte(0x0F);

   863   emit_byte(0x18);

   864   emit_operand(rax, src); // 0, src

   865 }

   866 

   867 

   868 void Assembler::prefetchw(Address src) {

   869   assert(VM_Version::supports_3dnow(), "must support");

   870   InstructionMark im(this);

   871   emit_byte(0x0F);

   872   emit_byte(0x0D);

   873   emit_operand(rcx, src); // 1, src

   874 }

   875 

   876 

   877 void Assembler::prefetchr(Address src) {

   878   assert(VM_Version::supports_3dnow(), "must support");

   879   InstructionMark im(this);

   880   emit_byte(0x0F);

   881   emit_byte(0x0D);

   882   emit_operand(rax, src); // 0, src

   883 }

   884 

   885 

   886 void Assembler::adcl(Register dst, int imm32) {

   887   emit_arith(0x81, 0xD0, dst, imm32);

   888 }

   889 

   890 

   891 void Assembler::adcl(Register dst, Address src) {

   892   InstructionMark im(this);

   893   emit_byte(0x13);

   894   emit_operand(dst, src);

   895 }

   896 

   897 

   898 void Assembler::adcl(Register dst, Register src) {

   899   emit_arith(0x13, 0xC0, dst, src);

   900 }

   901 

   902 

   903 void Assembler::addl(Address dst, int imm32) {

   904   InstructionMark im(this);

   905   emit_arith_operand(0x81,rax,dst,imm32);

   906 }

   907 

   908 

   909 void Assembler::addl(Address dst, Register src) {

   910   InstructionMark im(this);

   911   emit_byte(0x01);

   912   emit_operand(src, dst);

   913 }

   914 

   915 

   916 void Assembler::addl(Register dst, int imm32) {

   917   emit_arith(0x81, 0xC0, dst, imm32);

   918 }

   919 

   920 

   921 void Assembler::addl(Register dst, Address src) {

   922   InstructionMark im(this);

   923   emit_byte(0x03);

   924   emit_operand(dst, src);

   925 }

   926 

   927 

   928 void Assembler::addl(Register dst, Register src) {

   929   emit_arith(0x03, 0xC0, dst, src);

   930 }

   931 

   932 

   933 void Assembler::andl(Register dst, int imm32) {

   934   emit_arith(0x81, 0xE0, dst, imm32);

   935 }

   936 

   937 

   938 void Assembler::andl(Register dst, Address src) {

   939   InstructionMark im(this);

   940   emit_byte(0x23);

   941   emit_operand(dst, src);

   942 }

   943 

   944 

   945 void Assembler::andl(Register dst, Register src) {

   946   emit_arith(0x23, 0xC0, dst, src);

   947 }

   948 

   949 

   950 void Assembler::cmpb(Address dst, int imm8) {

   951   InstructionMark im(this);

   952   emit_byte(0x80);

   953   emit_operand(rdi, dst);

   954   emit_byte(imm8);

   955 }

   956 

   957 void Assembler::cmpw(Address dst, int imm16) {

   958   InstructionMark im(this);

   959   emit_byte(0x66);

   960   emit_byte(0x81);

   961   emit_operand(rdi, dst);

   962   emit_word(imm16);

   963 }

   964 

   965 void Assembler::cmpl(Address dst, int imm32) {

   966   InstructionMark im(this);

   967   emit_byte(0x81);

   968   emit_operand(rdi, dst);

   969   emit_long(imm32);

   970 }

   971 

   972 #ifndef _LP64

   973 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {

   974   InstructionMark im(this);

   975   emit_byte(0x81);

   976   emit_byte(0xF8 | src1->encoding());

   977   emit_data(imm32, rspec, 0);

   978 }

   979 

   980 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {

   981   InstructionMark im(this);

   982   emit_byte(0x81);

   983   emit_operand(rdi, src1);

   984   emit_data(imm32, rspec, 0);

   985 }

   986 #endif // _LP64

   987 

   988 

   989 void Assembler::cmpl(Register dst, int imm32) {

   990   emit_arith(0x81, 0xF8, dst, imm32);

   991 }

   992 

   993 

   994 void Assembler::cmpl(Register dst, Register src) {

   995   emit_arith(0x3B, 0xC0, dst, src);

   996 }

   997 

   998 

   999 void Assembler::cmpl(Register dst, Address  src) {

  1000   InstructionMark im(this);

  1001   emit_byte(0x3B);

  1002   emit_operand(dst, src);

  1003 }

  1004 

  1005 

  1006 void Assembler::decl(Register dst) {

  1007   // Don't use it directly. Use MacroAssembler::decrement() instead.

  1008   emit_byte(0x48 | dst->encoding());

  1009 }

  1010 

  1011 

  1012 void Assembler::decl(Address dst) {

  1013   // Don't use it directly. Use MacroAssembler::decrement() instead.

  1014   InstructionMark im(this);

  1015   emit_byte(0xFF);

  1016   emit_operand(rcx, dst);

  1017 }

  1018 

  1019 

  1020 void Assembler::idivl(Register src) {

  1021   emit_byte(0xF7);

  1022   emit_byte(0xF8 | src->encoding());

  1023 }

  1024 

  1025 

  1026 void Assembler::cdql() {

  1027   emit_byte(0x99);

  1028 }

  1029 

  1030 

  1031 void Assembler::imull(Register dst, Register src) {

  1032   emit_byte(0x0F);

  1033   emit_byte(0xAF);

  1034   emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());

  1035 }

  1036 

  1037 

  1038 void Assembler::imull(Register dst, Register src, int value) {

  1039   if (is8bit(value)) {

  1040     emit_byte(0x6B);

  1041     emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());

  1042     emit_byte(value);

  1043   } else {

  1044     emit_byte(0x69);

  1045     emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());

  1046     emit_long(value);

  1047   }

  1048 }

  1049 

  1050 

  1051 void Assembler::incl(Register dst) {

  1052   // Don't use it directly. Use MacroAssembler::increment() instead.

  1053   emit_byte(0x40 | dst->encoding());

  1054 }

  1055 

  1056 

  1057 void Assembler::incl(Address dst) {

  1058   // Don't use it directly. Use MacroAssembler::increment() instead.

  1059   InstructionMark im(this);

  1060   emit_byte(0xFF);

  1061   emit_operand(rax, dst);

  1062 }

  1063 

  1064 

  1065 void Assembler::leal(Register dst, Address src) {

  1066   InstructionMark im(this);

  1067   emit_byte(0x8D);

  1068   emit_operand(dst, src);

  1069 }

  1070 

  1071 void Assembler::mull(Address src) {

  1072   InstructionMark im(this);

  1073   emit_byte(0xF7);

  1074   emit_operand(rsp, src);

  1075 }

  1076 

  1077 

  1078 void Assembler::mull(Register src) {

  1079   emit_byte(0xF7);

  1080   emit_byte(0xE0 | src->encoding());

  1081 }

  1082 

  1083 

  1084 void Assembler::negl(Register dst) {

  1085   emit_byte(0xF7);

  1086   emit_byte(0xD8 | dst->encoding());

  1087 }

  1088 

  1089 

  1090 void Assembler::notl(Register dst) {

  1091   emit_byte(0xF7);

  1092   emit_byte(0xD0 | dst->encoding());

  1093 }

  1094 

  1095 

  1096 void Assembler::orl(Address dst, int imm32) {

  1097   InstructionMark im(this);

  1098   emit_byte(0x81);

  1099   emit_operand(rcx, dst);

  1100   emit_long(imm32);

  1101 }

  1102 

  1103 void Assembler::orl(Register dst, int imm32) {

  1104   emit_arith(0x81, 0xC8, dst, imm32);

  1105 }

  1106 

  1107 

  1108 void Assembler::orl(Register dst, Address src) {

  1109   InstructionMark im(this);

  1110   emit_byte(0x0B);

  1111   emit_operand(dst, src);

  1112 }

  1113 

  1114 

  1115 void Assembler::orl(Register dst, Register src) {

  1116   emit_arith(0x0B, 0xC0, dst, src);

  1117 }

  1118 

  1119 

  1120 void Assembler::rcll(Register dst, int imm8) {

  1121   assert(isShiftCount(imm8), "illegal shift count");

  1122   if (imm8 == 1) {

  1123     emit_byte(0xD1);

  1124     emit_byte(0xD0 | dst->encoding());

  1125   } else {

  1126     emit_byte(0xC1);

  1127     emit_byte(0xD0 | dst->encoding());

  1128     emit_byte(imm8);

  1129   }

  1130 }

  1131 

  1132 

  1133 void Assembler::sarl(Register dst, int imm8) {

  1134   assert(isShiftCount(imm8), "illegal shift count");