1 /*

     2  * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    24 

    25 #ifndef CPU_X86_GC_G1_BARRIERSETASSEMBLER_X86_HPP

    26 #define CPU_X86_GC_G1_BARRIERSETASSEMBLER_X86_HPP

    27 

    28 #include "asm/macroAssembler.hpp"

    29 #include "memory/allocation.hpp"

    30 #include "oops/access.hpp"

    31 

    32 class InterpreterMacroAssembler;

    33 

    34 class BarrierSetAssembler: public CHeapObj<mtGC> {

    35 protected:

    36 public:

    37   virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,

    38                                   Register src, Register dst, Register count) {}

    39   virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,

    40                                   Register src, Register dst, Register count) {}

    41 };

    42 

    43 #endif // CPU_X86_GC_G1_BARRIERSETASSEMBLER_X86_HPP