1 /*

     2  * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved.

     3  * Copyright (c) 2018, SAP SE. All rights reserved.

     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     5  *

     6  * This code is free software; you can redistribute it and/or modify it

     7  * under the terms of the GNU General Public License version 2 only, as

     8  * published by the Free Software Foundation.

     9  *

    10  * This code is distributed in the hope that it will be useful, but WITHOUT

    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    13  * version 2 for more details (a copy is included in the LICENSE file that

    14  * accompanied this code).

    15  *

    16  * You should have received a copy of the GNU General Public License version

    17  * 2 along with this work; if not, write to the Free Software Foundation,

    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    19  *

    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    21  * or visit www.oracle.com if you need additional information or have any

    22  * questions.

    23  *

    24  */

    25 

    26 #ifndef CPU_PPC_GC_SHARED_BARRIERSETASSEMBLER_PPC_HPP

    27 #define CPU_PPC_GC_SHARED_BARRIERSETASSEMBLER_PPC_HPP

    28 

    29 #include "asm/macroAssembler.hpp"

    30 #include "memory/allocation.hpp"

    31 #include "oops/access.hpp"

    32 

    33 class InterpreterMacroAssembler;

    34 

    35 class BarrierSetAssembler: public CHeapObj<mtGC> {

    36 public:

    37   virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,

    38                                   Register src, Register dst, Register count, Register preserve1, Register preserve2) {}

    39   virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,

    40                                   Register dst, Register count, Register preserve) {}

    41 };

    42 

    43 #endif // CPU_PPC_GC_SHARED_BARRIERSETASSEMBLER_PPC_HPP