jdk-sandbox: comparison src/hotspot/os_cpu/linux_ppc/atomic_linux

equal deleted inserted replaced

-:28eaf7a99a8c
+:ea0a16ba6ac0
 /*
-* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
+* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
-* Copyright (c) 2012, 2014 SAP SE. All rights reserved.
+* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 *
 * This code is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 only, as
 * published by the Free Software Foundation.
 #define strasm_acquire                    strasm_lwsync
 #define strasm_fence                      strasm_sync
 #define strasm_nobarrier                  ""
 #define strasm_nobarrier_clobber_memory   ""
+inline void pre_membar(atomic_memory_order order) {
+switch (order) {
+case memory_order_relaxed:
+case memory_order_acquire: break;
+case memory_order_release:
+case memory_order_acq_rel: __asm__ __volatile__ (strasm_lwsync); break;
+default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
+}
+}
+inline void post_membar(atomic_memory_order order) {
+switch (order) {
+case memory_order_relaxed:
+case memory_order_release: break;
+case memory_order_acquire:
+case memory_order_acq_rel: __asm__ __volatile__ (strasm_isync); break;
+default /*conservative*/ : __asm__ __volatile__ (strasm_sync); break;
+}
+}
 template<size_t byte_size>
 struct Atomic::PlatformAdd
 : Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> >
 {
 template<typename I, typename D>
-D add_and_fetch(I add_value, D volatile* dest) const;
+D add_and_fetch(I add_value, D volatile* dest, atomic_memory_order order) const;
 };
 template<>
 template<typename I, typename D>
-inline D Atomic::PlatformAdd<4>::add_and_fetch(I add_value, D volatile* dest) const {
+inline D Atomic::PlatformAdd<4>::add_and_fetch(I add_value, D volatile* dest,
+atomic_memory_order order) const {
 STATIC_ASSERT(4 == sizeof(I));
 STATIC_ASSERT(4 == sizeof(D));
 D result;
-__asm__ __volatile__ (
+pre_membar(order);
-strasm_lwsync
+__asm__ __volatile__ (
 "1: lwarx   %0,  0, %2    \n"
 "   add     %0, %0, %1    \n"
 "   stwcx.  %0,  0, %2    \n"
 "   bne-    1b            \n"
-strasm_isync
 : /*%0*/"=&r" (result)
 : /*%1*/"r" (add_value), /*%2*/"r" (dest)
 : "cc", "memory" );
+post_membar(order);
 return result;
 }
 template<>
 template<typename I, typename D>
-inline D Atomic::PlatformAdd<8>::add_and_fetch(I add_value, D volatile* dest) const {
+inline D Atomic::PlatformAdd<8>::add_and_fetch(I add_value, D volatile* dest,
+atomic_memory_order order) const {
 STATIC_ASSERT(8 == sizeof(I));
 STATIC_ASSERT(8 == sizeof(D));
 D result;
-__asm__ __volatile__ (
+pre_membar(order);
-strasm_lwsync
+__asm__ __volatile__ (
 "1: ldarx   %0,  0, %2    \n"
 "   add     %0, %0, %1    \n"
 "   stdcx.  %0,  0, %2    \n"
 "   bne-    1b            \n"
-strasm_isync
 : /*%0*/"=&r" (result)
 : /*%1*/"r" (add_value), /*%2*/"r" (dest)
 : "cc", "memory" );
+post_membar(order);
 return result;
 }
 template<>
 template<typename T>
 inline T Atomic::PlatformXchg<4>::operator()(T exchange_value,
-T volatile* dest) const {
+T volatile* dest,
+atomic_memory_order order) const {
 // Note that xchg doesn't necessarily do an acquire
 // (see synchronizer.cpp).
 T old_value;
 const uint64_t zero = 0;
-__asm__ __volatile__ (
+pre_membar(order);
-/* lwsync */
-strasm_lwsync
+__asm__ __volatile__ (
 /* atomic loop */
 "1:                                                 \n"
 "   lwarx   %[old_value], %[dest], %[zero]          \n"
 "   stwcx.  %[exchange_value], %[dest], %[zero]     \n"
 "   bne-    1b                                      \n"
-/* isync */
-strasm_sync
 /* exit */
 "2:                                                 \n"
 /* out */
 : [old_value]       "=&r"   (old_value),
 "=m"    (*dest)
 /* clobber */
 : "cc",
 "memory"
 );
+post_membar(order);
 return old_value;
 }
 template<>
 template<typename T>
 inline T Atomic::PlatformXchg<8>::operator()(T exchange_value,
-T volatile* dest) const {
+T volatile* dest,
+atomic_memory_order order) const {
 STATIC_ASSERT(8 == sizeof(T));
 // Note that xchg doesn't necessarily do an acquire
 // (see synchronizer.cpp).
 T old_value;
 const uint64_t zero = 0;
-__asm__ __volatile__ (
+pre_membar(order);
-/* lwsync */
-strasm_lwsync
+__asm__ __volatile__ (
 /* atomic loop */
 "1:                                                 \n"
 "   ldarx   %[old_value], %[dest], %[zero]          \n"
 "   stdcx.  %[exchange_value], %[dest], %[zero]     \n"
 "   bne-    1b                                      \n"
-/* isync */
-strasm_sync
 /* exit */
 "2:                                                 \n"
 /* out */
 : [old_value]       "=&r"   (old_value),
 "=m"    (*dest)
 /* clobber */
 : "cc",
 "memory"
 );
+post_membar(order);
 return old_value;
-}
-inline void cmpxchg_pre_membar(cmpxchg_memory_order order) {
-if (order != memory_order_relaxed) {
-__asm__ __volatile__ (
-/* fence */
-strasm_sync
-);
-}
-}
-inline void cmpxchg_post_membar(cmpxchg_memory_order order) {
-if (order != memory_order_relaxed) {
-__asm__ __volatile__ (
-/* fence */
-strasm_sync
-);
-}
 }
 template<>
 template<typename T>
 inline T Atomic::PlatformCmpxchg<1>::operator()(T exchange_value,
 T volatile* dest,
 T compare_value,
-cmpxchg_memory_order order) const {
+atomic_memory_order order) const {
 STATIC_ASSERT(1 == sizeof(T));
 // Note that cmpxchg guarantees a two-way memory barrier across
 // the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
 // specified otherwise (see atomic.hpp).
 masked_exchange_val = ((unsigned int)(unsigned char)exchange_value),
 xor_value           = (masked_compare_val ^ masked_exchange_val) << shift_amount;
 unsigned int old_value, value32;
-cmpxchg_pre_membar(order);
+pre_membar(order);
 __asm__ __volatile__ (
 /* simple guard */
 "   lbz     %[old_value], 0(%[dest])                  \n"
 "   cmpw    %[masked_compare_val], %[old_value]       \n"
 /* clobber */
 : "cc",
 "memory"
 );
-cmpxchg_post_membar(order);
+post_membar(order);
 return PrimitiveConversions::cast<T>((unsigned char)old_value);
 }
 template<>
 template<typename T>
 inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value,
 T volatile* dest,
 T compare_value,
-cmpxchg_memory_order order) const {
+atomic_memory_order order) const {
 STATIC_ASSERT(4 == sizeof(T));
 // Note that cmpxchg guarantees a two-way memory barrier across
 // the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
 // specified otherwise (see atomic.hpp).
 T old_value;
 const uint64_t zero = 0;
-cmpxchg_pre_membar(order);
+pre_membar(order);
 __asm__ __volatile__ (
 /* simple guard */
 "   lwz     %[old_value], 0(%[dest])                \n"
 "   cmpw    %[compare_value], %[old_value]          \n"
 /* clobber */
 : "cc",
 "memory"
 );
-cmpxchg_post_membar(order);
+post_membar(order);
 return old_value;
 }
 template<>
 template<typename T>
 inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
 T volatile* dest,
 T compare_value,
-cmpxchg_memory_order order) const {
+atomic_memory_order order) const {
 STATIC_ASSERT(8 == sizeof(T));
 // Note that cmpxchg guarantees a two-way memory barrier across
 // the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
 // specified otherwise (see atomic.hpp).
 T old_value;
 const uint64_t zero = 0;
-cmpxchg_pre_membar(order);
+pre_membar(order);
 __asm__ __volatile__ (
 /* simple guard */
 "   ld      %[old_value], 0(%[dest])                \n"
 "   cmpd    %[compare_value], %[old_value]          \n"
 /* clobber */
 : "cc",
 "memory"
 );
-cmpxchg_post_membar(order);
+post_membar(order);
 return old_value;
 }
 #undef strasm_sync

changeset 50029	ea0a16ba6ac0
parent 47634	6a0c42c40cd1
child 53244	9807daeb47c4