4105 // Shorts/Chars vector logical right shift produces incorrect Java result

  4105 // Shorts vector logical right shift produces incorrect Java result

  4107 // sign extension before a shift.

  4107 // sign extension before a shift. But char vectors are fine since chars are

  4108 // unsigned values.

  4109 

  4110 instruct vsrl2S(vecS dst, vecS shift) %{

  4111   predicate(n->as_Vector()->length() == 2);

  4112   match(Set dst (URShiftVS dst shift));

  4113   format %{ "psrlw   $dst,$shift\t! logical right shift packed2S" %}

  4114   ins_encode %{

  4115     __ psrlw($dst$$XMMRegister, $shift$$XMMRegister);

  4116   %}

  4117   ins_pipe( pipe_slow );

  4118 %}

  4119 

  4120 instruct vsrl2S_imm(vecS dst, immI8 shift) %{

  4121   predicate(n->as_Vector()->length() == 2);

  4122   match(Set dst (URShiftVS dst shift));

  4123   format %{ "psrlw   $dst,$shift\t! logical right shift packed2S" %}

  4124   ins_encode %{

  4125     __ psrlw($dst$$XMMRegister, (int)$shift$$constant);

  4126   %}

  4127   ins_pipe( pipe_slow );

  4128 %}

  4129 

  4130 instruct vsrl2S_reg(vecS dst, vecS src, vecS shift) %{

  4131   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);

  4132   match(Set dst (URShiftVS src shift));

  4133   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed2S" %}

  4134   ins_encode %{

  4135     bool vector256 = false;

  4136     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);

  4137   %}

  4138   ins_pipe( pipe_slow );

  4139 %}

  4140 

  4141 instruct vsrl2S_reg_imm(vecS dst, vecS src, immI8 shift) %{

  4142   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);

  4143   match(Set dst (URShiftVS src shift));

  4144   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed2S" %}

  4145   ins_encode %{

  4146     bool vector256 = false;

  4147     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);

  4148   %}

  4149   ins_pipe( pipe_slow );

  4150 %}

  4151 

  4152 instruct vsrl4S(vecD dst, vecS shift) %{

  4153   predicate(n->as_Vector()->length() == 4);

  4154   match(Set dst (URShiftVS dst shift));

  4155   format %{ "psrlw   $dst,$shift\t! logical right shift packed4S" %}

  4156   ins_encode %{

  4157     __ psrlw($dst$$XMMRegister, $shift$$XMMRegister);

  4158   %}

  4159   ins_pipe( pipe_slow );

  4160 %}

  4161 

  4162 instruct vsrl4S_imm(vecD dst, immI8 shift) %{

  4163   predicate(n->as_Vector()->length() == 4);

  4164   match(Set dst (URShiftVS dst shift));

  4165   format %{ "psrlw   $dst,$shift\t! logical right shift packed4S" %}

  4166   ins_encode %{

  4167     __ psrlw($dst$$XMMRegister, (int)$shift$$constant);

  4168   %}

  4169   ins_pipe( pipe_slow );

  4170 %}

  4171 

  4172 instruct vsrl4S_reg(vecD dst, vecD src, vecS shift) %{

  4173   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);

  4174   match(Set dst (URShiftVS src shift));

  4175   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed4S" %}

  4176   ins_encode %{

  4177     bool vector256 = false;

  4178     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);

  4179   %}

  4180   ins_pipe( pipe_slow );

  4181 %}

  4182 

  4183 instruct vsrl4S_reg_imm(vecD dst, vecD src, immI8 shift) %{

  4184   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);

  4185   match(Set dst (URShiftVS src shift));

  4186   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed4S" %}

  4187   ins_encode %{

  4188     bool vector256 = false;

  4189     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);

  4190   %}

  4191   ins_pipe( pipe_slow );

  4192 %}

  4193 

  4194 instruct vsrl8S(vecX dst, vecS shift) %{

  4195   predicate(n->as_Vector()->length() == 8);

  4196   match(Set dst (URShiftVS dst shift));

  4197   format %{ "psrlw   $dst,$shift\t! logical right shift packed8S" %}

  4198   ins_encode %{

  4199     __ psrlw($dst$$XMMRegister, $shift$$XMMRegister);

  4200   %}

  4201   ins_pipe( pipe_slow );

  4202 %}

  4203 

  4204 instruct vsrl8S_imm(vecX dst, immI8 shift) %{

  4205   predicate(n->as_Vector()->length() == 8);

  4206   match(Set dst (URShiftVS dst shift));

  4207   format %{ "psrlw   $dst,$shift\t! logical right shift packed8S" %}

  4208   ins_encode %{

  4209     __ psrlw($dst$$XMMRegister, (int)$shift$$constant);

  4210   %}

  4211   ins_pipe( pipe_slow );

  4212 %}

  4213 

  4214 instruct vsrl8S_reg(vecX dst, vecX src, vecS shift) %{

  4215   predicate(UseAVX > 0 && n->as_Vector()->length() == 8);

  4216   match(Set dst (URShiftVS src shift));

  4217   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed8S" %}

  4218   ins_encode %{

  4219     bool vector256 = false;

  4220     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);

  4221   %}

  4222   ins_pipe( pipe_slow );

  4223 %}

  4224 

  4225 instruct vsrl8S_reg_imm(vecX dst, vecX src, immI8 shift) %{

  4226   predicate(UseAVX > 0 && n->as_Vector()->length() == 8);

  4227   match(Set dst (URShiftVS src shift));

  4228   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed8S" %}

  4229   ins_encode %{

  4230     bool vector256 = false;

  4231     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);

  4232   %}

  4233   ins_pipe( pipe_slow );

  4234 %}

  4235 

  4236 instruct vsrl16S_reg(vecY dst, vecY src, vecS shift) %{

  4237   predicate(UseAVX > 1 && n->as_Vector()->length() == 16);

  4238   match(Set dst (URShiftVS src shift));

  4239   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed16S" %}

  4240   ins_encode %{

  4241     bool vector256 = true;

  4242     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256);

  4243   %}

  4244   ins_pipe( pipe_slow );

  4245 %}

  4246 

  4247 instruct vsrl16S_reg_imm(vecY dst, vecY src, immI8 shift) %{

  4248   predicate(UseAVX > 1 && n->as_Vector()->length() == 16);

  4249   match(Set dst (URShiftVS src shift));

  4250   format %{ "vpsrlw  $dst,$src,$shift\t! logical right shift packed16S" %}

  4251   ins_encode %{

  4252     bool vector256 = true;

  4253     __ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256);

  4254   %}

  4255   ins_pipe( pipe_slow );

  4256 %}