2698 

  2699 operand flagsRegUL_LTGE() %{

  2700   constraint(ALLOC_IN_RC(int_flags));

  2701   match(RegFlags);

  2702 

  2703   format %{ "apsr_UL_LTGE" %}

  2704   interface(REG_INTER);

  2705 %}

  2706 

  2707 operand flagsRegUL_EQNE() %{

  2708   constraint(ALLOC_IN_RC(int_flags));

  2709   match(RegFlags);

  2710 

  2711   format %{ "apsr_UL_EQNE" %}

  2712   interface(REG_INTER);

  2713 %}

  2714 

  2715 operand flagsRegUL_LEGT() %{

  2716   constraint(ALLOC_IN_RC(int_flags));

  2717   match(RegFlags);

  2718 

  2719   format %{ "apsr_UL_LEGT" %}

  2720   interface(REG_INTER);

  2721 %}

  3275 

  3276 operand cmpOpUL() %{

  3277   match(Bool);

  3278 

  3279   format %{ "UL" %}

  3280   interface(COND_INTER) %{

  3281     equal(0x0);

  3282     not_equal(0x1);

  3283     less(0x3);

  3284     greater_equal(0x2);

  3285     less_equal(0x9);

  3286     greater(0x8);

  3287     overflow(0x0); // unsupported/unimplemented

  3288     no_overflow(0x0); // unsupported/unimplemented

  3289   %}

  3290 %}

  3291 

  3292 operand cmpOpUL_commute() %{

  3293   match(Bool);

  3294 

  3295   format %{ "UL" %}

  3296   interface(COND_INTER) %{

  3297     equal(0x0);

  3298     not_equal(0x1);

  3299     less(0x8);

  3300     greater_equal(0x9);

  3301     less_equal(0x2);

  3302     greater(0x3);

  3303     overflow(0x0); // unsupported/unimplemented

  3304     no_overflow(0x0); // unsupported/unimplemented

  3305   %}

  3306 %}

  3307 

 10527 

 10528 instruct compUL_iReg(flagsRegU xcc, iRegL op1, iRegL op2) %{

 10529   match(Set xcc (CmpUL op1 op2));

 10530 

 10531   size(4);

 10532   format %{ "CMP     $op1,$op2\t! unsigned long" %}

 10533   ins_encode %{

 10534     __ cmp($op1$$Register, $op2$$Register);

 10535   %}

 10536   ins_pipe(ialu_cconly_reg_reg);

 10537 %}

 10552 

 10553 instruct compUL_reg_reg_LTGE(flagsRegUL_LTGE xcc, iRegL op1, iRegL op2, iRegL tmp) %{

 10554   match(Set xcc (CmpUL op1 op2));

 10555   effect(DEF xcc, USE op1, USE op2, TEMP tmp);

 10556 

 10557   size(8);

 10558   format %{ "SUBS    $tmp,$op1.low,$op2.low\t\t! unsigned long\n\t"

 10559             "SBCS    $tmp,$op1.hi,$op2.hi" %}

 10560   ins_encode %{

 10561     __ subs($tmp$$Register, $op1$$Register, $op2$$Register);

 10562     __ sbcs($tmp$$Register->successor(), $op1$$Register->successor(), $op2$$Register->successor());

 10563   %}

 10564   ins_pipe(ialu_cconly_reg_reg);

 10565 %}

 10575   ins_encode %{

 10576     __ cmp($op1$$Register, $con$$constant);

 10577   %}

 10578 

 10579   ins_pipe(ialu_cconly_reg_imm);

 10580 %}

 10581 

 10582 instruct compUL_reg_con(flagsRegU xcc, iRegL op1, aimmL con) %{

 10583   match(Set xcc (CmpUL op1 con));

 10584   effect(DEF xcc, USE op1, USE con);

 10585 

 10586   size(8);

 10587   format %{ "CMP     $op1,$con\t\t! unsigned long"  %}

 10665             "RSCS    $tmp,$op1.hi,0" %}

 10666   ins_encode %{

 10667     __ rsbs($tmp$$Register, $op1$$Register, $con$$constant);

 10668     __ rscs($tmp$$Register->successor(), $op1$$Register->successor(), 0);

 10669   %}

 10670 

 10671   ins_pipe(ialu_cconly_reg_reg);

 10672 %}

 10673 

 10674 instruct compUL_reg_reg_EQNE(flagsRegUL_EQNE xcc, iRegL op1, iRegL op2) %{

 10675   match(Set xcc (CmpUL op1 op2));

 10676   effect(DEF xcc, USE op1, USE op2);

 10677 

 10678   size(8);

 10679   format %{ "TEQ    $op1.hi,$op2.hi\t\t! unsigned long\n\t"

 10680             "TEQ.eq $op1.lo,$op2.lo" %}

 10681   ins_encode %{

 10682     __ teq($op1$$Register->successor(), $op2$$Register->successor());

 10683     __ teq($op1$$Register, $op2$$Register, eq);

 10684   %}

 10685   ins_pipe(ialu_cconly_reg_reg);

 10686 %}

 10687 

 10688 instruct compUL_reg_reg_LEGT(flagsRegUL_LEGT xcc, iRegL op1, iRegL op2, iRegL tmp) %{

 10689   match(Set xcc (CmpUL op1 op2));

 10690   effect(DEF xcc, USE op1, USE op2, TEMP tmp);

 10691 

 10692   size(8);

 10693   format %{ "SUBS    $tmp,$op2.low,$op1.low\t\t! unsigned long\n\t"

 10694             "SBCS    $tmp,$op2.hi,$op1.hi" %}

 10695   ins_encode %{

 10696     __ subs($tmp$$Register, $op2$$Register, $op1$$Register);

 10697     __ sbcs($tmp$$Register->successor(), $op2$$Register->successor(), $op1$$Register->successor());

 10698   %}

 10699   ins_pipe(ialu_cconly_reg_reg);

 10700 %}

 10701 

 10702 // TODO: try immLRot2 instead, (0, $con$$constant) becomes

 10703 // (hi($con$$constant), lo($con$$constant)) becomes

 10704 instruct compUL_reg_con_LTGE(flagsRegUL_LTGE xcc, iRegL op1, immLlowRot con, iRegL tmp) %{

 10705   match(Set xcc (CmpUL op1 con));

 10706   effect(DEF xcc, USE op1, USE con, TEMP tmp);

 10707 

 10708   size(8);

 10709   format %{ "SUBS    $tmp,$op1.low,$con\t\t! unsigned long\n\t"

 10710             "SBCS    $tmp,$op1.hi,0" %}

 10711   ins_encode %{

 10712     __ subs($tmp$$Register, $op1$$Register, $con$$constant);

 10713     __ sbcs($tmp$$Register->successor(), $op1$$Register->successor(), 0);

 10714   %}

 10715 

 10716   ins_pipe(ialu_cconly_reg_reg);

 10717 %}

 10718 

 10719 // TODO: try immLRot2 instead, (0, $con$$constant) becomes

 10720 // (hi($con$$constant), lo($con$$constant)) becomes

 10721 instruct compUL_reg_con_EQNE(flagsRegUL_EQNE xcc, iRegL op1, immLlowRot con) %{

 10722   match(Set xcc (CmpUL op1 con));

 10723   effect(DEF xcc, USE op1, USE con);

 10724 

 10725   size(8);

 10726   format %{ "TEQ    $op1.hi,0\t\t! unsigned long\n\t"

 10727             "TEQ.eq $op1.lo,$con" %}

 10728   ins_encode %{

 10729     __ teq($op1$$Register->successor(), 0);

 10730     __ teq($op1$$Register, $con$$constant, eq);

 10731   %}

 10732 

 10733   ins_pipe(ialu_cconly_reg_reg);

 10734 %}

 10735 

 10736 // TODO: try immLRot2 instead, (0, $con$$constant) becomes

 10737 // (hi($con$$constant), lo($con$$constant)) becomes

 10738 instruct compUL_reg_con_LEGT(flagsRegUL_LEGT xcc, iRegL op1, immLlowRot con, iRegL tmp) %{

 10739   match(Set xcc (CmpUL op1 con));

 10740   effect(DEF xcc, USE op1, USE con, TEMP tmp);

 10741 

 10742   size(8);

 10743   format %{ "RSBS    $tmp,$op1.low,$con\t\t! unsigned long\n\t"

 11294 

 11295   size(4);

 11296   ins_cost(BRANCH_COST);

 11297   format %{ "B$cmp  $xcc,$labl" %}

 11298   ins_encode %{

 11299     __ b(*($labl$$label), (AsmCondition)($cmp$$cmpcode));

 11300   %}

 11301   ins_pipe(br_cc);

 11302 %}

 11303 

 11304 instruct branchConUL_LTGE(cmpOpUL cmp, flagsRegUL_LTGE xcc, label labl) %{

 11305   match(If cmp xcc);

 11306   effect(USE labl);

 11307   predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge);

 11308 

 11309   size(4);

 11310   ins_cost(BRANCH_COST);

 11311   format %{ "B$cmp  $xcc,$labl" %}

 11312   ins_encode %{

 11313     __ b(*($labl$$label), (AsmCondition)($cmp$$cmpcode));

 11314   %}

 11315   ins_pipe(br_cc);

 11316 %}

 11317 

 11318 instruct branchConUL_EQNE(cmpOpUL cmp, flagsRegUL_EQNE xcc, label labl) %{

 11319   match(If cmp xcc);

 11320   effect(USE labl);

 11321   predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);

 11322 

 11323   size(4);

 11324   ins_cost(BRANCH_COST);

 11325   format %{ "B$cmp  $xcc,$labl" %}

 11326   ins_encode %{

 11327     __ b(*($labl$$label), (AsmCondition)($cmp$$cmpcode));

 11328   %}

 11329   ins_pipe(br_cc);

 11330 %}

 11331 

 11332 instruct branchConUL_LEGT(cmpOpUL_commute cmp, flagsRegUL_LEGT xcc, label labl) %{

 11333   match(If cmp xcc);

 11334   effect(USE labl);

 11335   predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le);