hotspot/src/cpu/arm/vm/interp_masm_arm.hpp
changeset 44093 e22e0d071bf9
parent 44088 fb5421685295
child 46338 e84b501fa52e
child 44406 a46a6c4d1dd9
equal deleted inserted replaced
44092:bc842cc2356b 44093:e22e0d071bf9
     1 /*
     1 /*
     2  * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
     2  * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  *
     4  *
     5  * This code is free software; you can redistribute it and/or modify it
     5  * This code is free software; you can redistribute it and/or modify it
     6  * under the terms of the GNU General Public License version 2 only, as
     6  * under the terms of the GNU General Public License version 2 only, as
     7  * published by the Free Software Foundation.
     7  * published by the Free Software Foundation.
   143 
   143 
   144   void store_check_part1(Register card_table_base);                // Sets card_table_base register.
   144   void store_check_part1(Register card_table_base);                // Sets card_table_base register.
   145   void store_check_part2(Register obj, Register card_table_base, Register tmp);
   145   void store_check_part2(Register obj, Register card_table_base, Register tmp);
   146 
   146 
   147   void set_card(Register card_table_base, Address card_table_addr, Register tmp);
   147   void set_card(Register card_table_base, Address card_table_addr, Register tmp);
       
   148 
       
   149 #if INCLUDE_ALL_GCS
       
   150   // G1 pre-barrier.
       
   151   // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
       
   152   // If store_addr != noreg, then previous value is loaded from [store_addr];
       
   153   // in such case store_addr and new_val registers are preserved;
       
   154   // otherwise pre_val register is preserved.
       
   155   void g1_write_barrier_pre(Register store_addr,
       
   156                             Register new_val,
       
   157                             Register pre_val,
       
   158                             Register tmp1,
       
   159                             Register tmp2);
       
   160 
       
   161   // G1 post-barrier.
       
   162   // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
       
   163   void g1_write_barrier_post(Register store_addr,
       
   164                              Register new_val,
       
   165                              Register tmp1,
       
   166                              Register tmp2,
       
   167                              Register tmp3);
       
   168 #endif // INCLUDE_ALL_GCS
   148 
   169 
   149   void pop_ptr(Register r);
   170   void pop_ptr(Register r);
   150   void pop_i(Register r = R0_tos);
   171   void pop_i(Register r = R0_tos);
   151 #ifdef AARCH64
   172 #ifdef AARCH64
   152   void pop_l(Register r = R0_tos);
   173   void pop_l(Register r = R0_tos);