equal
deleted
inserted
replaced
6478 // Integer DIVMOD with Register, both quotient and mod results |
6478 // Integer DIVMOD with Register, both quotient and mod results |
6479 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{ |
6479 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{ |
6480 match(DivModI dst1src1 src2); |
6480 match(DivModI dst1src1 src2); |
6481 effect(KILL cr); |
6481 effect(KILL cr); |
6482 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6482 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6483 size(VM_Version::has_CompareBranch() ? 24 : 26); |
6483 size((VM_Version::has_CompareBranch() ? 24 : 26)); |
6484 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %} |
6484 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %} |
6485 ins_encode %{ |
6485 ins_encode %{ |
6486 Register d1s1 = $dst1src1$$Register; |
6486 Register d1s1 = $dst1src1$$Register; |
6487 Register d2 = $dst2$$Register; |
6487 Register d2 = $dst2$$Register; |
6488 Register s2 = $src2$$Register; |
6488 Register s2 = $src2$$Register; |
6511 // Register Division |
6511 // Register Division |
6512 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{ |
6512 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{ |
6513 match(Set dst (DivI src1 src2)); |
6513 match(Set dst (DivI src1 src2)); |
6514 effect(KILL tmp, KILL cr); |
6514 effect(KILL tmp, KILL cr); |
6515 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6515 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6516 size(VM_Version::has_CompareBranch() ? 20 : 22); |
6516 size((VM_Version::has_CompareBranch() ? 20 : 22)); |
6517 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %} |
6517 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %} |
6518 ins_encode %{ |
6518 ins_encode %{ |
6519 Register a = $src1$$Register; |
6519 Register a = $src1$$Register; |
6520 Register b = $src2$$Register; |
6520 Register b = $src2$$Register; |
6521 Register t = $dst$$Register; |
6521 Register t = $dst$$Register; |
6562 // Long DIVMOD with Register, both quotient and mod results |
6562 // Long DIVMOD with Register, both quotient and mod results |
6563 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{ |
6563 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{ |
6564 match(DivModL dst1src1 src2); |
6564 match(DivModL dst1src1 src2); |
6565 effect(KILL cr); |
6565 effect(KILL cr); |
6566 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6566 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6567 size(VM_Version::has_CompareBranch() ? 22 : 24); |
6567 size((VM_Version::has_CompareBranch() ? 22 : 24)); |
6568 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %} |
6568 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %} |
6569 ins_encode %{ |
6569 ins_encode %{ |
6570 Register d1s1 = $dst1src1$$Register; |
6570 Register d1s1 = $dst1src1$$Register; |
6571 Register d2 = $dst2$$Register; |
6571 Register d2 = $dst2$$Register; |
6572 Register s2 = $src2$$Register; |
6572 Register s2 = $src2$$Register; |
6592 // Register Long Division |
6592 // Register Long Division |
6593 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{ |
6593 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{ |
6594 match(Set dst (DivL dst src)); |
6594 match(Set dst (DivL dst src)); |
6595 effect(KILL tmp, KILL cr); |
6595 effect(KILL tmp, KILL cr); |
6596 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6596 ins_cost(2 * DEFAULT_COST + BRANCH_COST); |
6597 size(VM_Version::has_CompareBranch() ? 18 : 20); |
6597 size((VM_Version::has_CompareBranch() ? 18 : 20)); |
6598 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %} |
6598 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %} |
6599 ins_encode %{ |
6599 ins_encode %{ |
6600 Register b = $src$$Register; |
6600 Register b = $src$$Register; |
6601 Register t = $dst$$Register; |
6601 Register t = $dst$$Register; |
6602 |
6602 |