jdk-sandbox: comparison hotspot/src/cpu/sparc/vm/sparc.ad

equal deleted inserted replaced

-:9e8daec25638
+:d602ad6538bd
 // Calls to the runtime or native may not be reachable from compiled code,
 // so we generate the far call sequence on 64 bit sparc.
 // This code sequence is relocatable to any address, even on LP64.
 if ( force_far_call ) {
 __ relocate(rtype);
-Address dest(O7, (address)entry_point);
+AddressLiteral dest(entry_point);
-__ jumpl_to(dest, O7);
+__ jumpl_to(dest, O7, O7);
 }
 else
 #endif
 {
 __ call((address)entry_point, rtype);
 //=============================================================================
 // REQUIRED FUNCTIONALITY for encoding
 void emit_lo(CodeBuffer &cbuf, int val) {  }
 void emit_hi(CodeBuffer &cbuf, int val) {  }
-void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) {
-MacroAssembler _masm(&cbuf);
-if (ForceRelocatable) {
-Address addr(reg, (address)val);
-__ sethi(addr, ForceRelocatable);
-__ add(addr, reg);
-} else {
-__ set(val, reg);
-}
-}
 //=============================================================================
 #ifndef PRODUCT
 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
 __ verify_thread();
 // If this does safepoint polling, then do it here
 if( do_polling() && ra_->C->is_method_compilation() ) {
-Address polling_page(L0, (address)os::get_polling_page());
+AddressLiteral polling_page(os::get_polling_page());
-__ sethi(polling_page, false);
+__ sethi(polling_page, L0);
 __ relocate(relocInfo::poll_return_type);
 __ ld_ptr( L0, 0, G0 );
 }
 // If this is a return, then stuff the restore in the delay slot
 __ relocate(static_stub_Relocation::spec(mark));
 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
 __ set_inst_mark();
-Address a(G3, (address)-1);
+AddressLiteral addrlit(-1);
-__ JUMP(a, 0);
+__ JUMP(addrlit, G3, 0);
 __ delayed()->nop();
 // Update current stubs pointer and restore code_end.
 __ end_a_stub();
 }
 // Emit exception handler code.
 int emit_exception_handler(CodeBuffer& cbuf) {
 Register temp_reg = G3;
-Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin());
+AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
 MacroAssembler _masm(&cbuf);
 address base =
 __ start_a_stub(size_exception_handler());
 if (base == NULL)  return 0;  // CodeBuffer::expand failed
 int offset = __ offset();
-__ JUMP(exception_blob, 0); // sethi;jmp
+__ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
 __ delayed()->nop();
 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 __ end_a_stub();
 int emit_deopt_handler(CodeBuffer& cbuf) {
 // Can't use any of the current frame's registers as we may have deopted
 // at a poll and everything (including G3) can be live.
 Register temp_reg = L0;
-Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack());
+AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
 MacroAssembler _masm(&cbuf);
 address base =
 __ start_a_stub(size_deopt_handler());
 if (base == NULL)  return 0;  // CodeBuffer::expand failed
 int offset = __ offset();
 __ save_frame(0);
-__ JUMP(deopt_blob, 0); // sethi;jmp
+__ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
 __ delayed()->restore();
 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 __ end_a_stub();
 Register table_reg        = O7;
 address table_base = __ address_table_constant(_index2label);
 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
-// Load table address
+// Move table address into a register.
-Address the_pc(table_reg, table_base, rspec);
+__ set(table_base, table_reg, rspec);
-__ load_address(the_pc);
 // Jump to base address + switch value
 __ ld_ptr(table_reg, switch_reg, table_reg);
 __ jmp(table_reg, G0);
 __ delayed()->nop();
 // Utility encoding for loading a 64 bit Pointer into a register
 // The 64 bit pointer is stored in the generated code stream
 enc_class SetPtr( immP src, iRegP rd ) %{
 Register dest = reg_to_register_object($rd$$reg);
+MacroAssembler _masm(&cbuf);
 // [RGV] This next line should be generated from ADLC
 if ( _opnds[1]->constant_is_oop() ) {
 intptr_t val = $src$$constant;
-MacroAssembler _masm(&cbuf);
 __ set_oop_constant((jobject)val, dest);
 } else {          // non-oop pointers, e.g. card mark base, heap top
-emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false);
+__ set($src$$constant, dest);
 }
 %}
 enc_class Set13( immI13 src, iRegI rd ) %{
 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
 Register dest = reg_to_register_object($dst$$reg);
 Register temp = reg_to_register_object($tmp$$reg);
 __ set64( $src$$constant, dest, temp );
 %}
-enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{    // Load Immediate
-address float_address = MacroAssembler(&cbuf).float_constant($src$$constant);
-RelocationHolder rspec = internal_word_Relocation::spec(float_address);
-#ifdef _LP64
-Register   tmp_reg = reg_to_register_object($tmp$$reg);
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true);
-emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 );
-#else  // _LP64
-uint *code;
-int tmp_reg = $tmp$$reg;
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address );
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address );
-#endif // _LP64
-%}
-enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{    // Load Immediate
-address double_address = MacroAssembler(&cbuf).double_constant($src$$constant);
-RelocationHolder rspec = internal_word_Relocation::spec(double_address);
-#ifdef _LP64
-Register   tmp_reg = reg_to_register_object($tmp$$reg);
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
-emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
-#else // _LP64
-uint *code;
-int tmp_reg = $tmp$$reg;
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
-#endif // _LP64
-%}
 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
 // Load a constant replicated "count" times with width "width"
 int bit_width = $width$$constant * 8;
 jlong elt_val = $src$$constant;
 elt_val  &= (((jlong)1) << bit_width) - 1; // mask off sign bits
 for (int i = 0; i < $count$$constant - 1; i++) {
 val <<= bit_width;
 val |= elt_val;
 }
 jdouble dval = *(jdouble*)&val; // coerce to double type
-address double_address = MacroAssembler(&cbuf).double_constant(dval);
+MacroAssembler _masm(&cbuf);
+address double_address = __ double_constant(dval);
 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
-#ifdef _LP64
+AddressLiteral addrlit(double_address, rspec);
-Register   tmp_reg = reg_to_register_object($tmp$$reg);
-cbuf.relocate(cbuf.code_end(), rspec, 0);
+__ sethi(addrlit, $tmp$$Register);
-emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
+__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
-emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
-#else // _LP64
-uint *code;
-int tmp_reg = $tmp$$reg;
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
-cbuf.relocate(cbuf.code_end(), rspec, 0);
-emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
-#endif // _LP64
-%}
-enc_class ShouldNotEncodeThis ( ) %{
-ShouldNotCallThis();
 %}
 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
 MacroAssembler _masm(&cbuf);
 int  value_offset = java_lang_String:: value_offset_in_bytes();
 int offset_offset = java_lang_String::offset_offset_in_bytes();
 int  count_offset = java_lang_String:: count_offset_in_bytes();
 // load str1 (jchar*) base address into tmp1_reg
-__ load_heap_oop(Address(str1_reg, 0,  value_offset), tmp1_reg);
+__ load_heap_oop(str1_reg, value_offset, tmp1_reg);
-__ ld(Address(str1_reg, 0, offset_offset), result_reg);
+__ ld(str1_reg, offset_offset, result_reg);
 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
-__    ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
+__   ld(str1_reg, count_offset, str1_reg); // hoisted
 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
-__    load_heap_oop(Address(str2_reg, 0,  value_offset), tmp2_reg); // hoisted
+__   load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
 __ add(result_reg, tmp1_reg, tmp1_reg);
 // load str2 (jchar*) base address into tmp2_reg
-// __ ld_ptr(Address(str2_reg, 0,  value_offset), tmp2_reg); // hoisted
+// __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
-__ ld(Address(str2_reg, 0, offset_offset), result_reg);
+__ ld(str2_reg, offset_offset, result_reg);
 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
-__    ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
+__   ld(str2_reg, count_offset, str2_reg); // hoisted
 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
 __   subcc(str1_reg, str2_reg, O7); // hoisted
 __ add(result_reg, tmp2_reg, tmp2_reg);
 // Compute the minimum of the string lengths(str1_reg) and the
 // difference of the string lengths (stack)
 // discard string base pointers, after loading up the lengths
-// __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
+// __ ld(str1_reg, count_offset, str1_reg); // hoisted
-// __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
+// __ ld(str2_reg, count_offset, str2_reg); // hoisted
 // See if the lengths are different, and calculate min in str1_reg.
 // Stash diff in O7 in case we need it for a tie-breaker.
 Label Lskip;
 // __ subcc(str1_reg, str2_reg, O7); // hoisted
 int  value_offset = java_lang_String:: value_offset_in_bytes();
 int offset_offset = java_lang_String::offset_offset_in_bytes();
 int  count_offset = java_lang_String:: count_offset_in_bytes();
 // load str1 (jchar*) base address into tmp1_reg
-__ load_heap_oop(Address(str1_reg, 0,  value_offset), tmp1_reg);
+__ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
-__ ld(Address(str1_reg, 0, offset_offset), result_reg);
+__ ld(Address(str1_reg, offset_offset), result_reg);
 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
-__    ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
+__    ld(Address(str1_reg, count_offset), str1_reg); // hoisted
 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
-__    load_heap_oop(Address(str2_reg, 0,  value_offset), tmp2_reg); // hoisted
+__    load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
 __ add(result_reg, tmp1_reg, tmp1_reg);
 // load str2 (jchar*) base address into tmp2_reg
-// __ ld_ptr(Address(str2_reg, 0,  value_offset), tmp2_reg); // hoisted
+// __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
-__ ld(Address(str2_reg, 0, offset_offset), result_reg);
+__ ld(Address(str2_reg, offset_offset), result_reg);
 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
-__    ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
+__    ld(Address(str2_reg, count_offset), str2_reg); // hoisted
 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
 __   cmp(str1_reg, str2_reg); // hoisted
 __ add(result_reg, tmp2_reg, tmp2_reg);
 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
 __ delayed()->mov(G0, result_reg);    // not equal
 //load the lengths of arrays
-__ ld(Address(ary1_reg, 0, length_offset), tmp1_reg);
+__ ld(Address(ary1_reg, length_offset), tmp1_reg);
-__ ld(Address(ary2_reg, 0, length_offset), tmp2_reg);
+__ ld(Address(ary2_reg, length_offset), tmp2_reg);
 // return false if the two arrays are not equal length
 __ cmp(tmp1_reg, tmp2_reg);
 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
 __ delayed()->mov(G0, result_reg);     // not equal
 %}
 enc_class enc_rethrow() %{
 cbuf.set_inst_mark();
 Register temp_reg = G3;
-Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub());
+AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
 MacroAssembler _masm(&cbuf);
 #ifdef ASSERT
 __ save_frame(0);
-Address last_rethrow_addr(L1, (address)&last_rethrow);
+AddressLiteral last_rethrow_addrlit(&last_rethrow);
-__ sethi(last_rethrow_addr);
+__ sethi(last_rethrow_addrlit, L1);
+Address addr(L1, last_rethrow_addrlit.low10());
 __ get_pc(L2);
 __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
-__ st_ptr(L2, last_rethrow_addr);
+__ st_ptr(L2, addr);
 __ restore();
 #endif
-__ JUMP(rethrow_stub, 0); // sethi;jmp
+__ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
 __ delayed()->nop();
 %}
 enc_class emit_mem_nop() %{
 // Generates the instruction LDUXA [o6,g0],#0x82,g0
 match(Set dst (LoadB mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDSB   $mem,$dst\t! byte" %}
-opcode(Assembler::ldsb_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldsb($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Byte (8bit signed) into a Long Register
 instruct loadB2L(iRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadB mem)));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDSB   $mem,$dst\t! byte -> long" %}
-opcode(Assembler::ldsb_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldsb($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Unsigned Byte (8bit UNsigned) into an int reg
 instruct loadUB(iRegI dst, memory mem) %{
 match(Set dst (LoadUB mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUB   $mem,$dst\t! ubyte" %}
-opcode(Assembler::ldub_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldub($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Unsigned Byte (8bit UNsigned) into a Long Register
 instruct loadUB2L(iRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadUB mem)));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
-opcode(Assembler::ldub_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldub($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Short (16bit signed)
 instruct loadS(iRegI dst, memory mem) %{
 match(Set dst (LoadS mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDSH   $mem,$dst\t! short" %}
-opcode(Assembler::ldsh_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldsh($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Short (16bit signed) into a Long Register
 instruct loadS2L(iRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadS mem)));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDSH   $mem,$dst\t! short -> long" %}
-opcode(Assembler::ldsh_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldsh($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Unsigned Short/Char (16bit UNsigned)
 instruct loadUS(iRegI dst, memory mem) %{
 match(Set dst (LoadUS mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUH   $mem,$dst\t! ushort/char" %}
-opcode(Assembler::lduh_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ lduh($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
 instruct loadUS2L(iRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadUS mem)));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
-opcode(Assembler::lduh_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ lduh($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mask_mem);
 %}
 // Load Integer
 instruct loadI(iRegI dst, memory mem) %{
 match(Set dst (LoadI mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUW   $mem,$dst\t! int" %}
-opcode(Assembler::lduw_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ lduw($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mem);
 %}
 // Load Integer into a Long Register
 instruct loadI2L(iRegL dst, memory mem) %{
 match(Set dst (ConvI2L (LoadI mem)));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDSW   $mem,$dst\t! int -> long" %}
-opcode(Assembler::ldsw_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldsw($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mem);
 %}
 // Load Unsigned Integer into a Long Register
 instruct loadUI2L(iRegL dst, memory mem) %{
 match(Set dst (LoadUI2L mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUW   $mem,$dst\t! uint -> long" %}
-opcode(Assembler::lduw_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ lduw($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mem);
 %}
 // Load Long - aligned
 instruct loadL(iRegL dst, memory mem ) %{
 match(Set dst (LoadL mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDX    $mem,$dst\t! long" %}
-opcode(Assembler::ldx_op3);
+ins_encode %{
-ins_encode(simple_form3_mem_reg( mem, dst ) );
+__ ldx($mem$$Address, $dst$$Register);
+%}
 ins_pipe(iload_mem);
 %}
 // Load Long - UNaligned
 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
 ins_cost(MEMORY_REF_COST);
 size(4);
 #ifndef _LP64
 format %{ "LDUW   $mem,$dst\t! ptr" %}
-opcode(Assembler::lduw_op3, 0, REGP_OP);
+ins_encode %{
+__ lduw($mem$$Address, $dst$$Register);
+%}
 #else
 format %{ "LDX    $mem,$dst\t! ptr" %}
-opcode(Assembler::ldx_op3, 0, REGP_OP);
+ins_encode %{
+__ ldx($mem$$Address, $dst$$Register);
+%}
 #endif
-ins_encode( form3_mem_reg( mem, dst ) );
 ins_pipe(iload_mem);
 %}
 // Load Compressed Pointer
 instruct loadN(iRegN dst, memory mem) %{
 match(Set dst (LoadN mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
 ins_encode %{
-Register index = $mem$$index$$Register;
+__ lduw($mem$$Address, $dst$$Register);
-if (index != G0) {
+%}
-__ lduw($mem$$base$$Register, index, $dst$$Register);
+ins_pipe(iload_mem);
-} else {
-__ lduw($mem$$base$$Register, $mem$$disp, $dst$$Register);
-}
-%}
-ins_pipe(iload_mem);
 %}
 // Load Klass Pointer
 instruct loadKlass(iRegP dst, memory mem) %{
 match(Set dst (LoadKlass mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 #ifndef _LP64
 format %{ "LDUW   $mem,$dst\t! klass ptr" %}
-opcode(Assembler::lduw_op3, 0, REGP_OP);
+ins_encode %{
+__ lduw($mem$$Address, $dst$$Register);
+%}
 #else
 format %{ "LDX    $mem,$dst\t! klass ptr" %}
-opcode(Assembler::ldx_op3, 0, REGP_OP);
+ins_encode %{
+__ ldx($mem$$Address, $dst$$Register);
+%}
 #endif
-ins_encode( form3_mem_reg( mem, dst ) );
 ins_pipe(iload_mem);
 %}
 // Load narrow Klass Pointer
 instruct loadNKlass(iRegN dst, memory mem) %{
 match(Set dst (LoadNKlass mem));
 ins_cost(MEMORY_REF_COST);
 size(4);
 format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
 ins_encode %{
-Register base = as_Register($mem$$base);
+__ lduw($mem$$Address, $dst$$Register);
-Register index = as_Register($mem$$index);
-Register dst = $dst$$Register;
-if (index != G0) {
-__ lduw(base, index, dst);
-} else {
-__ lduw(base, $mem$$disp, dst);
-}
 %}
 ins_pipe(iload_mem);
 %}
 // Load Double
 instruct loadConP_poll(iRegP dst, immP_poll src) %{
 match(Set dst src);
 ins_cost(DEFAULT_COST);
 format %{ "SET    $src,$dst\t!ptr" %}
 ins_encode %{
-Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
+AddressLiteral polling_page(os::get_polling_page());
-__ sethi(polling_page, false );
+__ sethi(polling_page, reg_to_register_object($dst$$reg));
 %}
 ins_pipe(loadConP_poll);
 %}
 instruct loadConN0(iRegN dst, immN0 src) %{
 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
 match(Set dst src);
 effect(KILL tmp);
 #ifdef _LP64
-size(36);
+size(8*4);
 #else
-size(8);
+size(2*4);
 #endif
 format %{ "SETHI  hi(&$src),$tmp\t!get float $src from table\n\t"
 "LDF    [$tmp+lo(&$src)],$dst" %}
-ins_encode( LdImmF(src, dst, tmp) );
+ins_encode %{
+address float_address = __ float_constant($src$$constant);
+RelocationHolder rspec = internal_word_Relocation::spec(float_address);
+AddressLiteral addrlit(float_address, rspec);
+__ sethi(addrlit, $tmp$$Register);
+__ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
+%}
 ins_pipe(loadConFD);
 %}
 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
 match(Set dst src);
 effect(KILL tmp);
 #ifdef _LP64
-size(36);
+size(8*4);
 #else
-size(8);
+size(2*4);
 #endif
 format %{ "SETHI  hi(&$src),$tmp\t!get double $src from table\n\t"
 "LDDF   [$tmp+lo(&$src)],$dst" %}
-ins_encode( LdImmD(src, dst, tmp) );
+ins_encode %{
+address double_address = __ double_constant($src$$constant);
+RelocationHolder rspec = internal_word_Relocation::spec(double_address);
+AddressLiteral addrlit(double_address, rspec);
+__ sethi(addrlit, $tmp$$Register);
+__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
+%}
 ins_pipe(loadConFD);
 %}
 // Prefetch instructions.
 // Must be safe to execute with invalid address (cannot fault).

changeset 2571	d602ad6538bd
parent 2348	4e71ed4c2709
child 2576	a3babdbbca51