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24 */ |
24 */ |
25 |
25 |
26 #ifndef CPU_PPC_VM_VMREG_PPC_HPP |
26 #ifndef CPU_PPC_VM_VMREG_PPC_HPP |
27 #define CPU_PPC_VM_VMREG_PPC_HPP |
27 #define CPU_PPC_VM_VMREG_PPC_HPP |
28 |
28 |
29 bool is_Register(); |
29 inline bool is_Register() { |
30 Register as_Register(); |
30 return (unsigned int)value() < (unsigned int)ConcreteRegisterImpl::max_gpr; |
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31 } |
31 |
32 |
32 bool is_FloatRegister(); |
33 inline bool is_FloatRegister() { |
33 FloatRegister as_FloatRegister(); |
34 return value() >= ConcreteRegisterImpl::max_gpr && |
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35 value() < ConcreteRegisterImpl::max_fpr; |
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36 } |
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37 |
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38 inline Register as_Register() { |
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39 assert(is_Register() && is_even(value()), "even-aligned GPR name"); |
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40 return ::as_Register(value()>>1); |
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41 } |
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42 |
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43 inline FloatRegister as_FloatRegister() { |
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44 assert(is_FloatRegister() && is_even(value()), "must be"); |
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45 return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); |
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46 } |
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47 |
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48 inline bool is_concrete() { |
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49 assert(is_reg(), "must be"); |
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50 return is_even(value()); |
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51 } |
34 |
52 |
35 #endif // CPU_PPC_VM_VMREG_PPC_HPP |
53 #endif // CPU_PPC_VM_VMREG_PPC_HPP |