59 %} |
59 %} |
60 |
60 |
61 // |
61 // |
62 // Execute ZGC load barrier (strong) slow path |
62 // Execute ZGC load barrier (strong) slow path |
63 // |
63 // |
64 instruct loadBarrierSlowReg(iRegP dst, memory mem, rFlagsReg cr, |
64 instruct loadBarrierSlowReg(iRegP dst, memory src, rFlagsReg cr, |
65 vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4, |
65 vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4, |
66 vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9, |
66 vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9, |
67 vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14, |
67 vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14, |
68 vRegD_V15 v15, vRegD_V16 v16, vRegD_V17 v17, vRegD_V18 v18, vRegD_V19 v19, |
68 vRegD_V15 v15, vRegD_V16 v16, vRegD_V17 v17, vRegD_V18 v18, vRegD_V19 v19, |
69 vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24, |
69 vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24, |
70 vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29, |
70 vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29, |
71 vRegD_V30 v30, vRegD_V31 v31) %{ |
71 vRegD_V30 v30, vRegD_V31 v31) %{ |
72 match(Set dst (LoadBarrierSlowReg mem)); |
72 match(Set dst (LoadBarrierSlowReg src dst)); |
73 predicate(!n->as_LoadBarrierSlowReg()->is_weak()); |
73 predicate(!n->as_LoadBarrierSlowReg()->is_weak()); |
74 |
74 |
75 effect(DEF dst, KILL cr, |
75 effect(KILL cr, |
76 KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7, |
76 KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7, |
77 KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14, |
77 KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14, |
78 KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21, |
78 KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21, |
79 KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28, |
79 KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28, |
80 KILL v29, KILL v30, KILL v31); |
80 KILL v29, KILL v30, KILL v31); |
81 |
81 |
82 format %{"LoadBarrierSlowReg $dst, $mem" %} |
82 format %{ "lea $dst, $src\n\t" |
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83 "call #ZLoadBarrierSlowPath" %} |
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84 |
83 ins_encode %{ |
85 ins_encode %{ |
84 z_load_barrier_slow_reg(_masm, $dst$$Register, $mem$$base$$Register, |
86 z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$base$$Register, |
85 $mem$$index, $mem$$scale, $mem$$disp, false); |
87 $src$$index, $src$$scale, $src$$disp, false); |
86 %} |
88 %} |
87 ins_pipe(pipe_slow); |
89 ins_pipe(pipe_slow); |
88 %} |
90 %} |
89 |
91 |
90 // |
92 // |
91 // Execute ZGC load barrier (weak) slow path |
93 // Execute ZGC load barrier (weak) slow path |
92 // |
94 // |
93 instruct loadBarrierWeakSlowReg(iRegP dst, memory mem, rFlagsReg cr, |
95 instruct loadBarrierWeakSlowReg(iRegP dst, memory src, rFlagsReg cr, |
94 vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4, |
96 vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4, |
95 vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9, |
97 vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9, |
96 vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14, |
98 vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14, |
97 vRegD_V15 v15, vRegD_V16 v16, vRegD_V17 v17, vRegD_V18 v18, vRegD_V19 v19, |
99 vRegD_V15 v15, vRegD_V16 v16, vRegD_V17 v17, vRegD_V18 v18, vRegD_V19 v19, |
98 vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24, |
100 vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24, |
99 vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29, |
101 vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29, |
100 vRegD_V30 v30, vRegD_V31 v31) %{ |
102 vRegD_V30 v30, vRegD_V31 v31) %{ |
101 match(Set dst (LoadBarrierSlowReg mem)); |
103 match(Set dst (LoadBarrierSlowReg src dst)); |
102 predicate(n->as_LoadBarrierSlowReg()->is_weak()); |
104 predicate(n->as_LoadBarrierSlowReg()->is_weak()); |
103 |
105 |
104 effect(DEF dst, KILL cr, |
106 effect(KILL cr, |
105 KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7, |
107 KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7, |
106 KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14, |
108 KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14, |
107 KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21, |
109 KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21, |
108 KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28, |
110 KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28, |
109 KILL v29, KILL v30, KILL v31); |
111 KILL v29, KILL v30, KILL v31); |
110 |
112 |
111 format %{"LoadBarrierWeakSlowReg $dst, $mem" %} |
113 format %{ "lea $dst, $src\n\t" |
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114 "call #ZLoadBarrierSlowPath" %} |
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115 |
112 ins_encode %{ |
116 ins_encode %{ |
113 z_load_barrier_slow_reg(_masm, $dst$$Register, $mem$$base$$Register, |
117 z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$base$$Register, |
114 $mem$$index, $mem$$scale, $mem$$disp, true); |
118 $src$$index, $src$$scale, $src$$disp, true); |
115 %} |
119 %} |
116 ins_pipe(pipe_slow); |
120 ins_pipe(pipe_slow); |
117 %} |
121 %} |
118 |
122 |
119 |
123 |