equal
deleted
inserted
replaced
1707 } |
1707 } |
1708 |
1708 |
1709 return idivq_offset; |
1709 return idivq_offset; |
1710 } |
1710 } |
1711 |
1711 |
|
1712 void MacroAssembler::membar(Membar_mask_bits order_constraint) { |
|
1713 address prev = pc() - NativeMembar::instruction_size; |
|
1714 if (prev == code()->last_membar()) { |
|
1715 NativeMembar *bar = NativeMembar_at(prev); |
|
1716 // We are merging two memory barrier instructions. On AArch64 we |
|
1717 // can do this simply by ORing them together. |
|
1718 bar->set_kind(bar->get_kind() | order_constraint); |
|
1719 BLOCK_COMMENT("merged membar"); |
|
1720 } else { |
|
1721 code()->set_last_membar(pc()); |
|
1722 dmb(Assembler::barrier(order_constraint)); |
|
1723 } |
|
1724 } |
|
1725 |
1712 // MacroAssembler routines found actually to be needed |
1726 // MacroAssembler routines found actually to be needed |
1713 |
1727 |
1714 void MacroAssembler::push(Register src) |
1728 void MacroAssembler::push(Register src) |
1715 { |
1729 { |
1716 str(src, Address(pre(esp, -1 * wordSize))); |
1730 str(src, Address(pre(esp, -1 * wordSize))); |