4225 }

  4225 }

  4226 

  4226 

  4227 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {

  4227 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {

  4228   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :

  4228   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :

  4229          vector_len == AVX_256bit? VM_Version::supports_avx2() :

  4229          vector_len == AVX_256bit? VM_Version::supports_avx2() :

  4231   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);

  4231   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);

  4232   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  4232   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  4233   emit_int8(0x00);

  4233   emit_int8(0x00);

  4234   emit_int8((unsigned char)(0xC0 | encode));

  4234   emit_int8((unsigned char)(0xC0 | encode));

  4235 }

  4235 }

  7195   attributes.set_is_evex_instruction();

  7195   attributes.set_is_evex_instruction();

  7196   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  7196   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  7197   emit_int8(0x7C);

  7197   emit_int8(0x7C);

  7198   emit_int8((unsigned char)(0xC0 | encode));

  7198   emit_int8((unsigned char)(0xC0 | encode));

  7199 }

  7199 }

  7201 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {

  7200 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {

  7202   assert(VM_Version::supports_evex(), "");

  7201   assert(VM_Version::supports_evex(), "");

  7203   assert(dst != xnoreg, "sanity");

  7202   assert(dst != xnoreg, "sanity");

  7204   InstructionMark im(this);

  7203   InstructionMark im(this);

  7205   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);

  7204   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);

  7210   // swap src<->dst for encoding

  7209   // swap src<->dst for encoding

  7211   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  7210   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);

  7212   emit_int8((unsigned char)0x90);

  7211   emit_int8((unsigned char)0x90);

  7213   emit_operand(dst, src);

  7212   emit_operand(dst, src);

  7214 }

  7213 }

  7216 // Carry-Less Multiplication Quadword

  7214 // Carry-Less Multiplication Quadword

  7217 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {

  7215 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {

  7218   assert(VM_Version::supports_clmul(), "");

  7216   assert(VM_Version::supports_clmul(), "");

  7219   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);

  7217   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);

  7220   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);

  7218   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);