623 case 0x6B: // imul r, a, #8 |
640 case 0x6B: // imul r, a, #8 |
624 debug_only(has_disp32 = true); // has both kinds of operands! |
641 debug_only(has_disp32 = true); // has both kinds of operands! |
625 tail_size = 1; // the imm8 |
642 tail_size = 1; // the imm8 |
626 break; |
643 break; |
627 |
644 |
628 case 0xE8: // call rdisp32 |
645 case 0xC4: // VEX_3bytes |
629 case 0xE9: // jmp rdisp32 |
646 case 0xC5: // VEX_2bytes |
630 if (which == end_pc_operand) return ip + 4; |
647 assert((UseAVX > 0), "shouldn't have VEX prefix"); |
631 assert(which == call32_operand, "call has no disp32 or imm"); |
648 assert(ip == inst+1, "no prefixes allowed"); |
632 return ip; |
649 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions |
|
650 // but they have prefix 0x0F and processed when 0x0F processed above. |
|
651 // |
|
652 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES |
|
653 // instructions (these instructions are not supported in 64-bit mode). |
|
654 // To distinguish them bits [7:6] are set in the VEX second byte since |
|
655 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set |
|
656 // those VEX bits REX and vvvv bits are inverted. |
|
657 // |
|
658 // Fortunately C2 doesn't generate these instructions so we don't need |
|
659 // to check for them in product version. |
|
660 |
|
661 // Check second byte |
|
662 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); |
|
663 |
|
664 // First byte |
|
665 if ((0xFF & *inst) == VEX_3bytes) { |
|
666 ip++; // third byte |
|
667 is_64bit = ((VEX_W & *ip) == VEX_W); |
|
668 } |
|
669 ip++; // opcode |
|
670 // To find the end of instruction (which == end_pc_operand). |
|
671 switch (0xFF & *ip) { |
|
672 case 0x61: // pcmpestri r, r/a, #8 |
|
673 case 0x70: // pshufd r, r/a, #8 |
|
674 case 0x73: // psrldq r, #8 |
|
675 tail_size = 1; // the imm8 |
|
676 break; |
|
677 default: |
|
678 break; |
|
679 } |
|
680 ip++; // skip opcode |
|
681 debug_only(has_disp32 = true); // has both kinds of operands! |
|
682 break; |
633 |
683 |
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 |
684 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 |
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl |
685 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl |
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a |
686 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a |
637 case 0xDD: // fld_d a; fst_d a; fstp_d a |
687 case 0xDD: // fld_d a; fst_d a; fstp_d a |
916 emit_long(0); // 32-bits offset (4 bytes) |
972 emit_long(0); // 32-bits offset (4 bytes) |
917 } |
973 } |
918 |
974 |
919 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
975 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
976 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
921 emit_byte(0xF2); |
977 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
922 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
923 emit_byte(0x0F); |
|
924 emit_byte(0x58); |
978 emit_byte(0x58); |
925 emit_byte(0xC0 | encode); |
979 emit_byte(0xC0 | encode); |
926 } |
980 } |
927 |
981 |
928 void Assembler::addsd(XMMRegister dst, Address src) { |
982 void Assembler::addsd(XMMRegister dst, Address src) { |
929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
930 InstructionMark im(this); |
984 InstructionMark im(this); |
931 emit_byte(0xF2); |
985 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
932 prefix(src, dst); |
|
933 emit_byte(0x0F); |
|
934 emit_byte(0x58); |
986 emit_byte(0x58); |
935 emit_operand(dst, src); |
987 emit_operand(dst, src); |
936 } |
988 } |
937 |
989 |
938 void Assembler::addss(XMMRegister dst, XMMRegister src) { |
990 void Assembler::addss(XMMRegister dst, XMMRegister src) { |
939 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
991 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
940 emit_byte(0xF3); |
992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
941 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
942 emit_byte(0x0F); |
|
943 emit_byte(0x58); |
993 emit_byte(0x58); |
944 emit_byte(0xC0 | encode); |
994 emit_byte(0xC0 | encode); |
945 } |
995 } |
946 |
996 |
947 void Assembler::addss(XMMRegister dst, Address src) { |
997 void Assembler::addss(XMMRegister dst, Address src) { |
948 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
998 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
949 InstructionMark im(this); |
999 InstructionMark im(this); |
950 emit_byte(0xF3); |
1000 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
951 prefix(src, dst); |
|
952 emit_byte(0x0F); |
|
953 emit_byte(0x58); |
1001 emit_byte(0x58); |
954 emit_operand(dst, src); |
1002 emit_operand(dst, src); |
|
1003 } |
|
1004 |
|
1005 void Assembler::andl(Address dst, int32_t imm32) { |
|
1006 InstructionMark im(this); |
|
1007 prefix(dst); |
|
1008 emit_byte(0x81); |
|
1009 emit_operand(rsp, dst, 4); |
|
1010 emit_long(imm32); |
955 } |
1011 } |
956 |
1012 |
957 void Assembler::andl(Register dst, int32_t imm32) { |
1013 void Assembler::andl(Register dst, int32_t imm32) { |
958 prefix(dst); |
1014 prefix(dst); |
959 emit_arith(0x81, 0xE0, dst, imm32); |
1015 emit_arith(0x81, 0xE0, dst, imm32); |
1155 |
1219 |
1156 void Assembler::comisd(XMMRegister dst, Address src) { |
1220 void Assembler::comisd(XMMRegister dst, Address src) { |
1157 // NOTE: dbx seems to decode this as comiss even though the |
1221 // NOTE: dbx seems to decode this as comiss even though the |
1158 // 0x66 is there. Strangly ucomisd comes out correct |
1222 // 0x66 is there. Strangly ucomisd comes out correct |
1159 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1223 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1160 emit_byte(0x66); |
1224 InstructionMark im(this); |
1161 comiss(dst, src); |
1225 simd_prefix(dst, src, VEX_SIMD_66); |
|
1226 emit_byte(0x2F); |
|
1227 emit_operand(dst, src); |
|
1228 } |
|
1229 |
|
1230 void Assembler::comisd(XMMRegister dst, XMMRegister src) { |
|
1231 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1232 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
|
1233 emit_byte(0x2F); |
|
1234 emit_byte(0xC0 | encode); |
1162 } |
1235 } |
1163 |
1236 |
1164 void Assembler::comiss(XMMRegister dst, Address src) { |
1237 void Assembler::comiss(XMMRegister dst, Address src) { |
1165 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1238 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1166 |
1239 InstructionMark im(this); |
1167 InstructionMark im(this); |
1240 simd_prefix(dst, src, VEX_SIMD_NONE); |
1168 prefix(src, dst); |
|
1169 emit_byte(0x0F); |
|
1170 emit_byte(0x2F); |
1241 emit_byte(0x2F); |
1171 emit_operand(dst, src); |
1242 emit_operand(dst, src); |
1172 } |
1243 } |
1173 |
1244 |
|
1245 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
|
1246 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
1247 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
|
1248 emit_byte(0x2F); |
|
1249 emit_byte(0xC0 | encode); |
|
1250 } |
|
1251 |
1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1252 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1253 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1176 emit_byte(0xF3); |
1254 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1178 emit_byte(0x0F); |
|
1179 emit_byte(0xE6); |
1255 emit_byte(0xE6); |
1180 emit_byte(0xC0 | encode); |
1256 emit_byte(0xC0 | encode); |
1181 } |
1257 } |
1182 |
1258 |
1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { |
1259 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { |
1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1260 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1185 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
1186 emit_byte(0x0F); |
|
1187 emit_byte(0x5B); |
1262 emit_byte(0x5B); |
1188 emit_byte(0xC0 | encode); |
1263 emit_byte(0xC0 | encode); |
1189 } |
1264 } |
1190 |
1265 |
1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { |
1266 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { |
1192 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1193 emit_byte(0xF2); |
1268 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1194 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1195 emit_byte(0x0F); |
|
1196 emit_byte(0x5A); |
1269 emit_byte(0x5A); |
1197 emit_byte(0xC0 | encode); |
1270 emit_byte(0xC0 | encode); |
1198 } |
1271 } |
1199 |
1272 |
|
1273 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
|
1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1275 InstructionMark im(this); |
|
1276 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
|
1277 emit_byte(0x5A); |
|
1278 emit_operand(dst, src); |
|
1279 } |
|
1280 |
1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1281 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1282 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1202 emit_byte(0xF2); |
1283 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1203 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1204 emit_byte(0x0F); |
|
1205 emit_byte(0x2A); |
1284 emit_byte(0x2A); |
1206 emit_byte(0xC0 | encode); |
1285 emit_byte(0xC0 | encode); |
1207 } |
1286 } |
1208 |
1287 |
|
1288 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
|
1289 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1290 InstructionMark im(this); |
|
1291 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
|
1292 emit_byte(0x2A); |
|
1293 emit_operand(dst, src); |
|
1294 } |
|
1295 |
1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1296 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1210 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1297 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1211 emit_byte(0xF3); |
1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1212 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1213 emit_byte(0x0F); |
|
1214 emit_byte(0x2A); |
1299 emit_byte(0x2A); |
1215 emit_byte(0xC0 | encode); |
1300 emit_byte(0xC0 | encode); |
1216 } |
1301 } |
1217 |
1302 |
|
1303 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
|
1304 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
1305 InstructionMark im(this); |
|
1306 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
|
1307 emit_byte(0x2A); |
|
1308 emit_operand(dst, src); |
|
1309 } |
|
1310 |
1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1311 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1219 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1220 emit_byte(0xF3); |
1313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1221 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1222 emit_byte(0x0F); |
|
1223 emit_byte(0x5A); |
1314 emit_byte(0x5A); |
1224 emit_byte(0xC0 | encode); |
1315 emit_byte(0xC0 | encode); |
1225 } |
1316 } |
1226 |
1317 |
|
1318 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
|
1319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1320 InstructionMark im(this); |
|
1321 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
|
1322 emit_byte(0x5A); |
|
1323 emit_operand(dst, src); |
|
1324 } |
|
1325 |
|
1326 |
1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1327 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1229 emit_byte(0xF2); |
1329 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
1230 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1231 emit_byte(0x0F); |
|
1232 emit_byte(0x2C); |
1330 emit_byte(0x2C); |
1233 emit_byte(0xC0 | encode); |
1331 emit_byte(0xC0 | encode); |
1234 } |
1332 } |
1235 |
1333 |
1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) { |
1334 void Assembler::cvttss2sil(Register dst, XMMRegister src) { |
1237 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1335 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1238 emit_byte(0xF3); |
1336 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1239 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1240 emit_byte(0x0F); |
|
1241 emit_byte(0x2C); |
1337 emit_byte(0x2C); |
1242 emit_byte(0xC0 | encode); |
1338 emit_byte(0xC0 | encode); |
1243 } |
1339 } |
1244 |
1340 |
1245 void Assembler::decl(Address dst) { |
1341 void Assembler::decl(Address dst) { |
1251 } |
1347 } |
1252 |
1348 |
1253 void Assembler::divsd(XMMRegister dst, Address src) { |
1349 void Assembler::divsd(XMMRegister dst, Address src) { |
1254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1350 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1255 InstructionMark im(this); |
1351 InstructionMark im(this); |
1256 emit_byte(0xF2); |
1352 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
1257 prefix(src, dst); |
|
1258 emit_byte(0x0F); |
|
1259 emit_byte(0x5E); |
1353 emit_byte(0x5E); |
1260 emit_operand(dst, src); |
1354 emit_operand(dst, src); |
1261 } |
1355 } |
1262 |
1356 |
1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) { |
1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) { |
1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1265 emit_byte(0xF2); |
1359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1267 emit_byte(0x0F); |
|
1268 emit_byte(0x5E); |
1360 emit_byte(0x5E); |
1269 emit_byte(0xC0 | encode); |
1361 emit_byte(0xC0 | encode); |
1270 } |
1362 } |
1271 |
1363 |
1272 void Assembler::divss(XMMRegister dst, Address src) { |
1364 void Assembler::divss(XMMRegister dst, Address src) { |
1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1365 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1274 InstructionMark im(this); |
1366 InstructionMark im(this); |
1275 emit_byte(0xF3); |
1367 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
1276 prefix(src, dst); |
|
1277 emit_byte(0x0F); |
|
1278 emit_byte(0x5E); |
1368 emit_byte(0x5E); |
1279 emit_operand(dst, src); |
1369 emit_operand(dst, src); |
1280 } |
1370 } |
1281 |
1371 |
1282 void Assembler::divss(XMMRegister dst, XMMRegister src) { |
1372 void Assembler::divss(XMMRegister dst, XMMRegister src) { |
1283 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1373 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1284 emit_byte(0xF3); |
1374 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1286 emit_byte(0x0F); |
|
1287 emit_byte(0x5E); |
1375 emit_byte(0x5E); |
1288 emit_byte(0xC0 | encode); |
1376 emit_byte(0xC0 | encode); |
1289 } |
1377 } |
1290 |
1378 |
1291 void Assembler::emms() { |
1379 void Assembler::emms() { |
1580 emit_operand(src, dst); |
1635 emit_operand(src, dst); |
1581 } |
1636 } |
1582 |
1637 |
1583 void Assembler::movdl(XMMRegister dst, Register src) { |
1638 void Assembler::movdl(XMMRegister dst, Register src) { |
1584 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1639 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1585 emit_byte(0x66); |
1640 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1587 emit_byte(0x0F); |
|
1588 emit_byte(0x6E); |
1641 emit_byte(0x6E); |
1589 emit_byte(0xC0 | encode); |
1642 emit_byte(0xC0 | encode); |
1590 } |
1643 } |
1591 |
1644 |
1592 void Assembler::movdl(Register dst, XMMRegister src) { |
1645 void Assembler::movdl(Register dst, XMMRegister src) { |
1593 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1646 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1594 emit_byte(0x66); |
|
1595 // swap src/dst to get correct prefix |
1647 // swap src/dst to get correct prefix |
1596 int encode = prefix_and_encode(src->encoding(), dst->encoding()); |
1648 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
1597 emit_byte(0x0F); |
|
1598 emit_byte(0x7E); |
1649 emit_byte(0x7E); |
1599 emit_byte(0xC0 | encode); |
1650 emit_byte(0xC0 | encode); |
1600 } |
1651 } |
1601 |
1652 |
1602 void Assembler::movdl(XMMRegister dst, Address src) { |
1653 void Assembler::movdl(XMMRegister dst, Address src) { |
1603 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1654 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1604 InstructionMark im(this); |
1655 InstructionMark im(this); |
1605 emit_byte(0x66); |
1656 simd_prefix(dst, src, VEX_SIMD_66); |
1606 prefix(src, dst); |
|
1607 emit_byte(0x0F); |
|
1608 emit_byte(0x6E); |
1657 emit_byte(0x6E); |
1609 emit_operand(dst, src); |
1658 emit_operand(dst, src); |
1610 } |
1659 } |
1611 |
1660 |
1612 |
1661 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1613 void Assembler::movdqa(XMMRegister dst, Address src) { |
|
1614 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1615 InstructionMark im(this); |
1663 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1616 emit_byte(0x66); |
1664 emit_byte(0x6F); |
1617 prefix(src, dst); |
1665 emit_byte(0xC0 | encode); |
1618 emit_byte(0x0F); |
1666 } |
|
1667 |
|
1668 void Assembler::movdqu(XMMRegister dst, Address src) { |
|
1669 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1670 InstructionMark im(this); |
|
1671 simd_prefix(dst, src, VEX_SIMD_F3); |
1619 emit_byte(0x6F); |
1672 emit_byte(0x6F); |
1620 emit_operand(dst, src); |
1673 emit_operand(dst, src); |
1621 } |
1674 } |
1622 |
1675 |
1623 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1676 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { |
1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1677 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1625 emit_byte(0x66); |
1678 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
1626 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
1627 emit_byte(0x0F); |
|
1628 emit_byte(0x6F); |
1679 emit_byte(0x6F); |
1629 emit_byte(0xC0 | encode); |
1680 emit_byte(0xC0 | encode); |
1630 } |
1681 } |
1631 |
1682 |
1632 void Assembler::movdqa(Address dst, XMMRegister src) { |
|
1633 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1634 InstructionMark im(this); |
|
1635 emit_byte(0x66); |
|
1636 prefix(dst, src); |
|
1637 emit_byte(0x0F); |
|
1638 emit_byte(0x7F); |
|
1639 emit_operand(src, dst); |
|
1640 } |
|
1641 |
|
1642 void Assembler::movdqu(XMMRegister dst, Address src) { |
|
1643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1644 InstructionMark im(this); |
|
1645 emit_byte(0xF3); |
|
1646 prefix(src, dst); |
|
1647 emit_byte(0x0F); |
|
1648 emit_byte(0x6F); |
|
1649 emit_operand(dst, src); |
|
1650 } |
|
1651 |
|
1652 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { |
|
1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
1654 emit_byte(0xF3); |
|
1655 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
1656 emit_byte(0x0F); |
|
1657 emit_byte(0x6F); |
|
1658 emit_byte(0xC0 | encode); |
|
1659 } |
|
1660 |
|
1661 void Assembler::movdqu(Address dst, XMMRegister src) { |
1683 void Assembler::movdqu(Address dst, XMMRegister src) { |
1662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1684 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1663 InstructionMark im(this); |
1685 InstructionMark im(this); |
1664 emit_byte(0xF3); |
1686 simd_prefix(dst, src, VEX_SIMD_F3); |
1665 prefix(dst, src); |
|
1666 emit_byte(0x0F); |
|
1667 emit_byte(0x7F); |
1687 emit_byte(0x7F); |
1668 emit_operand(src, dst); |
1688 emit_operand(src, dst); |
1669 } |
1689 } |
1670 |
1690 |
1671 // Uses zero extension on 64bit |
1691 // Uses zero extension on 64bit |
1773 emit_byte(0xC0 | encode); |
1787 emit_byte(0xC0 | encode); |
1774 } |
1788 } |
1775 |
1789 |
1776 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
1790 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1791 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1778 emit_byte(0xF2); |
1792 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1780 emit_byte(0x0F); |
|
1781 emit_byte(0x10); |
1793 emit_byte(0x10); |
1782 emit_byte(0xC0 | encode); |
1794 emit_byte(0xC0 | encode); |
1783 } |
1795 } |
1784 |
1796 |
1785 void Assembler::movsd(XMMRegister dst, Address src) { |
1797 void Assembler::movsd(XMMRegister dst, Address src) { |
1786 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1798 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1787 InstructionMark im(this); |
1799 InstructionMark im(this); |
1788 emit_byte(0xF2); |
1800 simd_prefix(dst, src, VEX_SIMD_F2); |
1789 prefix(src, dst); |
|
1790 emit_byte(0x0F); |
|
1791 emit_byte(0x10); |
1801 emit_byte(0x10); |
1792 emit_operand(dst, src); |
1802 emit_operand(dst, src); |
1793 } |
1803 } |
1794 |
1804 |
1795 void Assembler::movsd(Address dst, XMMRegister src) { |
1805 void Assembler::movsd(Address dst, XMMRegister src) { |
1796 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1806 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1797 InstructionMark im(this); |
1807 InstructionMark im(this); |
1798 emit_byte(0xF2); |
1808 simd_prefix(dst, src, VEX_SIMD_F2); |
1799 prefix(dst, src); |
|
1800 emit_byte(0x0F); |
|
1801 emit_byte(0x11); |
1809 emit_byte(0x11); |
1802 emit_operand(src, dst); |
1810 emit_operand(src, dst); |
1803 } |
1811 } |
1804 |
1812 |
1805 void Assembler::movss(XMMRegister dst, XMMRegister src) { |
1813 void Assembler::movss(XMMRegister dst, XMMRegister src) { |
1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1814 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1807 emit_byte(0xF3); |
1815 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1808 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1809 emit_byte(0x0F); |
|
1810 emit_byte(0x10); |
1816 emit_byte(0x10); |
1811 emit_byte(0xC0 | encode); |
1817 emit_byte(0xC0 | encode); |
1812 } |
1818 } |
1813 |
1819 |
1814 void Assembler::movss(XMMRegister dst, Address src) { |
1820 void Assembler::movss(XMMRegister dst, Address src) { |
1815 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1821 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1816 InstructionMark im(this); |
1822 InstructionMark im(this); |
1817 emit_byte(0xF3); |
1823 simd_prefix(dst, src, VEX_SIMD_F3); |
1818 prefix(src, dst); |
|
1819 emit_byte(0x0F); |
|
1820 emit_byte(0x10); |
1824 emit_byte(0x10); |
1821 emit_operand(dst, src); |
1825 emit_operand(dst, src); |
1822 } |
1826 } |
1823 |
1827 |
1824 void Assembler::movss(Address dst, XMMRegister src) { |
1828 void Assembler::movss(Address dst, XMMRegister src) { |
1825 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1829 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1826 InstructionMark im(this); |
1830 InstructionMark im(this); |
1827 emit_byte(0xF3); |
1831 simd_prefix(dst, src, VEX_SIMD_F3); |
1828 prefix(dst, src); |
|
1829 emit_byte(0x0F); |
|
1830 emit_byte(0x11); |
1832 emit_byte(0x11); |
1831 emit_operand(src, dst); |
1833 emit_operand(src, dst); |
1832 } |
1834 } |
1833 |
1835 |
1834 void Assembler::movswl(Register dst, Address src) { // movsxw |
1836 void Assembler::movswl(Register dst, Address src) { // movsxw |
1917 } |
1919 } |
1918 |
1920 |
1919 void Assembler::mulsd(XMMRegister dst, Address src) { |
1921 void Assembler::mulsd(XMMRegister dst, Address src) { |
1920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1922 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1921 InstructionMark im(this); |
1923 InstructionMark im(this); |
1922 emit_byte(0xF2); |
1924 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
1923 prefix(src, dst); |
|
1924 emit_byte(0x0F); |
|
1925 emit_byte(0x59); |
1925 emit_byte(0x59); |
1926 emit_operand(dst, src); |
1926 emit_operand(dst, src); |
1927 } |
1927 } |
1928 |
1928 |
1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { |
1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { |
1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1931 emit_byte(0xF2); |
1931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1932 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1933 emit_byte(0x0F); |
|
1934 emit_byte(0x59); |
1932 emit_byte(0x59); |
1935 emit_byte(0xC0 | encode); |
1933 emit_byte(0xC0 | encode); |
1936 } |
1934 } |
1937 |
1935 |
1938 void Assembler::mulss(XMMRegister dst, Address src) { |
1936 void Assembler::mulss(XMMRegister dst, Address src) { |
1939 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1937 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1940 InstructionMark im(this); |
1938 InstructionMark im(this); |
1941 emit_byte(0xF3); |
1939 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
1942 prefix(src, dst); |
|
1943 emit_byte(0x0F); |
|
1944 emit_byte(0x59); |
1940 emit_byte(0x59); |
1945 emit_operand(dst, src); |
1941 emit_operand(dst, src); |
1946 } |
1942 } |
1947 |
1943 |
1948 void Assembler::mulss(XMMRegister dst, XMMRegister src) { |
1944 void Assembler::mulss(XMMRegister dst, XMMRegister src) { |
1949 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1945 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1950 emit_byte(0xF3); |
1946 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1951 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
1952 emit_byte(0x0F); |
|
1953 emit_byte(0x59); |
1947 emit_byte(0x59); |
1954 emit_byte(0xC0 | encode); |
1948 emit_byte(0xC0 | encode); |
1955 } |
1949 } |
1956 |
1950 |
1957 void Assembler::negl(Register dst) { |
1951 void Assembler::negl(Register dst) { |
2235 void Assembler::orl(Register dst, Register src) { |
2229 void Assembler::orl(Register dst, Register src) { |
2236 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2230 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2237 emit_arith(0x0B, 0xC0, dst, src); |
2231 emit_arith(0x0B, 0xC0, dst, src); |
2238 } |
2232 } |
2239 |
2233 |
|
2234 void Assembler::packuswb(XMMRegister dst, Address src) { |
|
2235 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2236 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
|
2237 InstructionMark im(this); |
|
2238 simd_prefix(dst, dst, src, VEX_SIMD_66); |
|
2239 emit_byte(0x67); |
|
2240 emit_operand(dst, src); |
|
2241 } |
|
2242 |
|
2243 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { |
|
2244 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2245 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
|
2246 emit_byte(0x67); |
|
2247 emit_byte(0xC0 | encode); |
|
2248 } |
|
2249 |
2240 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2250 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2241 assert(VM_Version::supports_sse4_2(), ""); |
2251 assert(VM_Version::supports_sse4_2(), ""); |
2242 |
2252 InstructionMark im(this); |
2243 InstructionMark im(this); |
2253 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2244 emit_byte(0x66); |
|
2245 prefix(src, dst); |
|
2246 emit_byte(0x0F); |
|
2247 emit_byte(0x3A); |
|
2248 emit_byte(0x61); |
2254 emit_byte(0x61); |
2249 emit_operand(dst, src); |
2255 emit_operand(dst, src); |
2250 emit_byte(imm8); |
2256 emit_byte(imm8); |
2251 } |
2257 } |
2252 |
2258 |
2253 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { |
2259 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { |
2254 assert(VM_Version::supports_sse4_2(), ""); |
2260 assert(VM_Version::supports_sse4_2(), ""); |
2255 |
2261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2256 emit_byte(0x66); |
|
2257 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
2258 emit_byte(0x0F); |
|
2259 emit_byte(0x3A); |
|
2260 emit_byte(0x61); |
2262 emit_byte(0x61); |
2261 emit_byte(0xC0 | encode); |
2263 emit_byte(0xC0 | encode); |
2262 emit_byte(imm8); |
2264 emit_byte(imm8); |
|
2265 } |
|
2266 |
|
2267 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
|
2268 assert(VM_Version::supports_sse4_1(), ""); |
|
2269 InstructionMark im(this); |
|
2270 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
2271 emit_byte(0x30); |
|
2272 emit_operand(dst, src); |
|
2273 } |
|
2274 |
|
2275 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { |
|
2276 assert(VM_Version::supports_sse4_1(), ""); |
|
2277 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
|
2278 emit_byte(0x30); |
|
2279 emit_byte(0xC0 | encode); |
2263 } |
2280 } |
2264 |
2281 |
2265 // generic |
2282 // generic |
2266 void Assembler::pop(Register dst) { |
2283 void Assembler::pop(Register dst) { |
2267 int encode = prefix_and_encode(dst->encoding()); |
2284 int encode = prefix_and_encode(dst->encoding()); |
2358 a_byte(p); |
2375 a_byte(p); |
2359 } |
2376 } |
2360 |
2377 |
2361 void Assembler::por(XMMRegister dst, XMMRegister src) { |
2378 void Assembler::por(XMMRegister dst, XMMRegister src) { |
2362 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2379 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2363 |
2380 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2364 emit_byte(0x66); |
|
2365 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2366 emit_byte(0x0F); |
|
2367 |
|
2368 emit_byte(0xEB); |
2381 emit_byte(0xEB); |
2369 emit_byte(0xC0 | encode); |
2382 emit_byte(0xC0 | encode); |
|
2383 } |
|
2384 |
|
2385 void Assembler::por(XMMRegister dst, Address src) { |
|
2386 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2387 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
|
2388 InstructionMark im(this); |
|
2389 simd_prefix(dst, dst, src, VEX_SIMD_66); |
|
2390 emit_byte(0xEB); |
|
2391 emit_operand(dst, src); |
2370 } |
2392 } |
2371 |
2393 |
2372 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2394 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2373 assert(isByte(mode), "invalid value"); |
2395 assert(isByte(mode), "invalid value"); |
2374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2396 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2375 |
2397 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
2376 emit_byte(0x66); |
|
2377 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2378 emit_byte(0x0F); |
|
2379 emit_byte(0x70); |
2398 emit_byte(0x70); |
2380 emit_byte(0xC0 | encode); |
2399 emit_byte(0xC0 | encode); |
2381 emit_byte(mode & 0xFF); |
2400 emit_byte(mode & 0xFF); |
2382 |
2401 |
2383 } |
2402 } |
2384 |
2403 |
2385 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
2404 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
2386 assert(isByte(mode), "invalid value"); |
2405 assert(isByte(mode), "invalid value"); |
2387 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2406 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2388 |
2407 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2389 InstructionMark im(this); |
2408 InstructionMark im(this); |
2390 emit_byte(0x66); |
2409 simd_prefix(dst, src, VEX_SIMD_66); |
2391 prefix(src, dst); |
|
2392 emit_byte(0x0F); |
|
2393 emit_byte(0x70); |
2410 emit_byte(0x70); |
2394 emit_operand(dst, src); |
2411 emit_operand(dst, src); |
2395 emit_byte(mode & 0xFF); |
2412 emit_byte(mode & 0xFF); |
2396 } |
2413 } |
2397 |
2414 |
2398 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
2415 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
2399 assert(isByte(mode), "invalid value"); |
2416 assert(isByte(mode), "invalid value"); |
2400 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2417 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2401 |
2418 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
2402 emit_byte(0xF2); |
|
2403 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2404 emit_byte(0x0F); |
|
2405 emit_byte(0x70); |
2419 emit_byte(0x70); |
2406 emit_byte(0xC0 | encode); |
2420 emit_byte(0xC0 | encode); |
2407 emit_byte(mode & 0xFF); |
2421 emit_byte(mode & 0xFF); |
2408 } |
2422 } |
2409 |
2423 |
2410 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
2424 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
2411 assert(isByte(mode), "invalid value"); |
2425 assert(isByte(mode), "invalid value"); |
2412 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2426 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2413 |
2427 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2414 InstructionMark im(this); |
2428 InstructionMark im(this); |
2415 emit_byte(0xF2); |
2429 simd_prefix(dst, src, VEX_SIMD_F2); |
2416 prefix(src, dst); // QQ new |
|
2417 emit_byte(0x0F); |
|
2418 emit_byte(0x70); |
2430 emit_byte(0x70); |
2419 emit_operand(dst, src); |
2431 emit_operand(dst, src); |
2420 emit_byte(mode & 0xFF); |
2432 emit_byte(mode & 0xFF); |
2421 } |
2433 } |
2422 |
2434 |
2423 void Assembler::psrlq(XMMRegister dst, int shift) { |
2435 void Assembler::psrlq(XMMRegister dst, int shift) { |
2424 // Shift 64 bit value logically right by specified number of bits. |
2436 // Shift 64 bit value logically right by specified number of bits. |
2425 // HMM Table D-1 says sse2 or mmx. |
2437 // HMM Table D-1 says sse2 or mmx. |
2426 // Do not confuse it with psrldq SSE2 instruction which |
2438 // Do not confuse it with psrldq SSE2 instruction which |
2427 // shifts 128 bit value in xmm register by number of bytes. |
2439 // shifts 128 bit value in xmm register by number of bytes. |
2428 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2429 |
2441 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
2430 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); |
|
2431 emit_byte(0x66); |
|
2432 emit_byte(0x0F); |
|
2433 emit_byte(0x73); |
2442 emit_byte(0x73); |
2434 emit_byte(0xC0 | encode); |
2443 emit_byte(0xC0 | encode); |
2435 emit_byte(shift); |
2444 emit_byte(shift); |
2436 } |
2445 } |
2437 |
2446 |
2438 void Assembler::psrldq(XMMRegister dst, int shift) { |
2447 void Assembler::psrldq(XMMRegister dst, int shift) { |
2439 // Shift 128 bit value in xmm register by number of bytes. |
2448 // Shift 128 bit value in xmm register by number of bytes. |
2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2449 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2441 |
2450 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
2442 int encode = prefixq_and_encode(xmm3->encoding(), dst->encoding()); |
|
2443 emit_byte(0x66); |
|
2444 emit_byte(0x0F); |
|
2445 emit_byte(0x73); |
2451 emit_byte(0x73); |
2446 emit_byte(0xC0 | encode); |
2452 emit_byte(0xC0 | encode); |
2447 emit_byte(shift); |
2453 emit_byte(shift); |
2448 } |
2454 } |
2449 |
2455 |
2450 void Assembler::ptest(XMMRegister dst, Address src) { |
2456 void Assembler::ptest(XMMRegister dst, Address src) { |
2451 assert(VM_Version::supports_sse4_1(), ""); |
2457 assert(VM_Version::supports_sse4_1(), ""); |
2452 |
2458 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2453 InstructionMark im(this); |
2459 InstructionMark im(this); |
2454 emit_byte(0x66); |
2460 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2455 prefix(src, dst); |
|
2456 emit_byte(0x0F); |
|
2457 emit_byte(0x38); |
|
2458 emit_byte(0x17); |
2461 emit_byte(0x17); |
2459 emit_operand(dst, src); |
2462 emit_operand(dst, src); |
2460 } |
2463 } |
2461 |
2464 |
2462 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2465 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2463 assert(VM_Version::supports_sse4_1(), ""); |
2466 assert(VM_Version::supports_sse4_1(), ""); |
2464 |
2467 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2465 emit_byte(0x66); |
|
2466 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
2467 emit_byte(0x0F); |
|
2468 emit_byte(0x38); |
|
2469 emit_byte(0x17); |
2468 emit_byte(0x17); |
2470 emit_byte(0xC0 | encode); |
2469 emit_byte(0xC0 | encode); |
2471 } |
2470 } |
2472 |
2471 |
|
2472 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
|
2473 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2474 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
|
2475 InstructionMark im(this); |
|
2476 simd_prefix(dst, dst, src, VEX_SIMD_66); |
|
2477 emit_byte(0x60); |
|
2478 emit_operand(dst, src); |
|
2479 } |
|
2480 |
2473 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2481 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2474 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2482 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2475 emit_byte(0x66); |
2483 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2476 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2477 emit_byte(0x0F); |
|
2478 emit_byte(0x60); |
2484 emit_byte(0x60); |
|
2485 emit_byte(0xC0 | encode); |
|
2486 } |
|
2487 |
|
2488 void Assembler::punpckldq(XMMRegister dst, Address src) { |
|
2489 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2490 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
|
2491 InstructionMark im(this); |
|
2492 simd_prefix(dst, dst, src, VEX_SIMD_66); |
|
2493 emit_byte(0x62); |
|
2494 emit_operand(dst, src); |
|
2495 } |
|
2496 |
|
2497 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { |
|
2498 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2499 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
|
2500 emit_byte(0x62); |
2479 emit_byte(0xC0 | encode); |
2501 emit_byte(0xC0 | encode); |
2480 } |
2502 } |
2481 |
2503 |
2482 void Assembler::push(int32_t imm32) { |
2504 void Assembler::push(int32_t imm32) { |
2483 // in 64bits we push 64bits onto the stack but only |
2505 // in 64bits we push 64bits onto the stack but only |
2681 void Assembler::smovl() { |
2699 void Assembler::smovl() { |
2682 emit_byte(0xA5); |
2700 emit_byte(0xA5); |
2683 } |
2701 } |
2684 |
2702 |
2685 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2703 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2686 // HMM Table D-1 says sse2 |
|
2687 // NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
2688 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2704 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2689 emit_byte(0xF2); |
2705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
2690 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2691 emit_byte(0x0F); |
|
2692 emit_byte(0x51); |
2706 emit_byte(0x51); |
2693 emit_byte(0xC0 | encode); |
2707 emit_byte(0xC0 | encode); |
2694 } |
2708 } |
2695 |
2709 |
2696 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2710 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2711 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2698 InstructionMark im(this); |
2712 InstructionMark im(this); |
2699 emit_byte(0xF2); |
2713 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
2700 prefix(src, dst); |
|
2701 emit_byte(0x0F); |
|
2702 emit_byte(0x51); |
2714 emit_byte(0x51); |
2703 emit_operand(dst, src); |
2715 emit_operand(dst, src); |
2704 } |
2716 } |
2705 |
2717 |
2706 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { |
2718 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { |
2707 // HMM Table D-1 says sse2 |
2719 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2708 // NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2720 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
2709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
2710 emit_byte(0xF3); |
|
2711 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2712 emit_byte(0x0F); |
|
2713 emit_byte(0x51); |
2721 emit_byte(0x51); |
2714 emit_byte(0xC0 | encode); |
2722 emit_byte(0xC0 | encode); |
2715 } |
2723 } |
2716 |
2724 |
2717 void Assembler::sqrtss(XMMRegister dst, Address src) { |
2725 void Assembler::sqrtss(XMMRegister dst, Address src) { |
2718 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2726 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2719 InstructionMark im(this); |
2727 InstructionMark im(this); |
2720 emit_byte(0xF3); |
2728 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
2721 prefix(src, dst); |
|
2722 emit_byte(0x0F); |
|
2723 emit_byte(0x51); |
2729 emit_byte(0x51); |
2724 emit_operand(dst, src); |
2730 emit_operand(dst, src); |
2725 } |
2731 } |
2726 |
2732 |
2727 void Assembler::stmxcsr( Address dst) { |
2733 void Assembler::stmxcsr( Address dst) { |
2763 emit_arith(0x2B, 0xC0, dst, src); |
2769 emit_arith(0x2B, 0xC0, dst, src); |
2764 } |
2770 } |
2765 |
2771 |
2766 void Assembler::subsd(XMMRegister dst, XMMRegister src) { |
2772 void Assembler::subsd(XMMRegister dst, XMMRegister src) { |
2767 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2773 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2768 emit_byte(0xF2); |
2774 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
2769 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2770 emit_byte(0x0F); |
|
2771 emit_byte(0x5C); |
2775 emit_byte(0x5C); |
2772 emit_byte(0xC0 | encode); |
2776 emit_byte(0xC0 | encode); |
2773 } |
2777 } |
2774 |
2778 |
2775 void Assembler::subsd(XMMRegister dst, Address src) { |
2779 void Assembler::subsd(XMMRegister dst, Address src) { |
2776 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2780 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2777 InstructionMark im(this); |
2781 InstructionMark im(this); |
2778 emit_byte(0xF2); |
2782 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
2779 prefix(src, dst); |
|
2780 emit_byte(0x0F); |
|
2781 emit_byte(0x5C); |
2783 emit_byte(0x5C); |
2782 emit_operand(dst, src); |
2784 emit_operand(dst, src); |
2783 } |
2785 } |
2784 |
2786 |
2785 void Assembler::subss(XMMRegister dst, XMMRegister src) { |
2787 void Assembler::subss(XMMRegister dst, XMMRegister src) { |
2786 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2788 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2787 emit_byte(0xF3); |
2789 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
2788 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
2789 emit_byte(0x0F); |
|
2790 emit_byte(0x5C); |
2790 emit_byte(0x5C); |
2791 emit_byte(0xC0 | encode); |
2791 emit_byte(0xC0 | encode); |
2792 } |
2792 } |
2793 |
2793 |
2794 void Assembler::subss(XMMRegister dst, Address src) { |
2794 void Assembler::subss(XMMRegister dst, Address src) { |
2795 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2795 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2796 InstructionMark im(this); |
2796 InstructionMark im(this); |
2797 emit_byte(0xF3); |
2797 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
2798 prefix(src, dst); |
|
2799 emit_byte(0x0F); |
|
2800 emit_byte(0x5C); |
2798 emit_byte(0x5C); |
2801 emit_operand(dst, src); |
2799 emit_operand(dst, src); |
2802 } |
2800 } |
2803 |
2801 |
2804 void Assembler::testb(Register dst, int imm8) { |
2802 void Assembler::testb(Register dst, int imm8) { |
2834 emit_operand(dst, src); |
2832 emit_operand(dst, src); |
2835 } |
2833 } |
2836 |
2834 |
2837 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2835 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2836 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2839 emit_byte(0x66); |
2837 InstructionMark im(this); |
2840 ucomiss(dst, src); |
2838 simd_prefix(dst, src, VEX_SIMD_66); |
|
2839 emit_byte(0x2E); |
|
2840 emit_operand(dst, src); |
2841 } |
2841 } |
2842 |
2842 |
2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { |
2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { |
2844 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2844 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2845 emit_byte(0x66); |
2845 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
2846 ucomiss(dst, src); |
2846 emit_byte(0x2E); |
|
2847 emit_byte(0xC0 | encode); |
2847 } |
2848 } |
2848 |
2849 |
2849 void Assembler::ucomiss(XMMRegister dst, Address src) { |
2850 void Assembler::ucomiss(XMMRegister dst, Address src) { |
2850 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2851 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2851 |
2852 InstructionMark im(this); |
2852 InstructionMark im(this); |
2853 simd_prefix(dst, src, VEX_SIMD_NONE); |
2853 prefix(src, dst); |
|
2854 emit_byte(0x0F); |
|
2855 emit_byte(0x2E); |
2854 emit_byte(0x2E); |
2856 emit_operand(dst, src); |
2855 emit_operand(dst, src); |
2857 } |
2856 } |
2858 |
2857 |
2859 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { |
2858 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { |
2860 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2859 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2861 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2860 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
2862 emit_byte(0x0F); |
|
2863 emit_byte(0x2E); |
2861 emit_byte(0x2E); |
2864 emit_byte(0xC0 | encode); |
2862 emit_byte(0xC0 | encode); |
2865 } |
2863 } |
2866 |
2864 |
2867 |
2865 |
2903 emit_arith(0x33, 0xC0, dst, src); |
2901 emit_arith(0x33, 0xC0, dst, src); |
2904 } |
2902 } |
2905 |
2903 |
2906 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
2904 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
2907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2905 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2908 emit_byte(0x66); |
2906 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
2909 xorps(dst, src); |
2907 emit_byte(0x57); |
|
2908 emit_byte(0xC0 | encode); |
2910 } |
2909 } |
2911 |
2910 |
2912 void Assembler::xorpd(XMMRegister dst, Address src) { |
2911 void Assembler::xorpd(XMMRegister dst, Address src) { |
2913 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2912 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2914 InstructionMark im(this); |
2913 InstructionMark im(this); |
2915 emit_byte(0x66); |
2914 simd_prefix(dst, dst, src, VEX_SIMD_66); |
2916 prefix(src, dst); |
|
2917 emit_byte(0x0F); |
|
2918 emit_byte(0x57); |
2915 emit_byte(0x57); |
2919 emit_operand(dst, src); |
2916 emit_operand(dst, src); |
2920 } |
2917 } |
2921 |
2918 |
2922 |
2919 |
2923 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
2920 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
2924 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2921 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2925 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2922 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); |
2926 emit_byte(0x0F); |
|
2927 emit_byte(0x57); |
2923 emit_byte(0x57); |
2928 emit_byte(0xC0 | encode); |
2924 emit_byte(0xC0 | encode); |
2929 } |
2925 } |
2930 |
2926 |
2931 void Assembler::xorps(XMMRegister dst, Address src) { |
2927 void Assembler::xorps(XMMRegister dst, Address src) { |
2932 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2928 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2933 InstructionMark im(this); |
2929 InstructionMark im(this); |
2934 prefix(src, dst); |
2930 simd_prefix(dst, dst, src, VEX_SIMD_NONE); |
2935 emit_byte(0x0F); |
|
2936 emit_byte(0x57); |
2931 emit_byte(0x57); |
2937 emit_operand(dst, src); |
2932 emit_operand(dst, src); |
2938 } |
2933 } |
2939 |
2934 |
2940 #ifndef _LP64 |
2935 #ifndef _LP64 |
3392 void Assembler::fyl2x() { |
3387 void Assembler::fyl2x() { |
3393 emit_byte(0xD9); |
3388 emit_byte(0xD9); |
3394 emit_byte(0xF1); |
3389 emit_byte(0xF1); |
3395 } |
3390 } |
3396 |
3391 |
|
3392 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
|
3393 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; |
|
3394 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. |
|
3395 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; |
|
3396 |
|
3397 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. |
|
3398 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { |
|
3399 if (pre > 0) { |
|
3400 emit_byte(simd_pre[pre]); |
|
3401 } |
|
3402 if (rex_w) { |
|
3403 prefixq(adr, xreg); |
|
3404 } else { |
|
3405 prefix(adr, xreg); |
|
3406 } |
|
3407 if (opc > 0) { |
|
3408 emit_byte(0x0F); |
|
3409 int opc2 = simd_opc[opc]; |
|
3410 if (opc2 > 0) { |
|
3411 emit_byte(opc2); |
|
3412 } |
|
3413 } |
|
3414 } |
|
3415 |
|
3416 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { |
|
3417 if (pre > 0) { |
|
3418 emit_byte(simd_pre[pre]); |
|
3419 } |
|
3420 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : |
|
3421 prefix_and_encode(dst_enc, src_enc); |
|
3422 if (opc > 0) { |
|
3423 emit_byte(0x0F); |
|
3424 int opc2 = simd_opc[opc]; |
|
3425 if (opc2 > 0) { |
|
3426 emit_byte(opc2); |
|
3427 } |
|
3428 } |
|
3429 return encode; |
|
3430 } |
|
3431 |
|
3432 |
|
3433 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { |
|
3434 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { |
|
3435 prefix(VEX_3bytes); |
|
3436 |
|
3437 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); |
|
3438 byte1 = (~byte1) & 0xE0; |
|
3439 byte1 |= opc; |
|
3440 a_byte(byte1); |
|
3441 |
|
3442 int byte2 = ((~nds_enc) & 0xf) << 3; |
|
3443 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; |
|
3444 emit_byte(byte2); |
|
3445 } else { |
|
3446 prefix(VEX_2bytes); |
|
3447 |
|
3448 int byte1 = vex_r ? VEX_R : 0; |
|
3449 byte1 = (~byte1) & 0x80; |
|
3450 byte1 |= ((~nds_enc) & 0xf) << 3; |
|
3451 byte1 |= (vector256 ? 4 : 0) | pre; |
|
3452 emit_byte(byte1); |
|
3453 } |
|
3454 } |
|
3455 |
|
3456 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ |
|
3457 bool vex_r = (xreg_enc >= 8); |
|
3458 bool vex_b = adr.base_needs_rex(); |
|
3459 bool vex_x = adr.index_needs_rex(); |
|
3460 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); |
|
3461 } |
|
3462 |
|
3463 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { |
|
3464 bool vex_r = (dst_enc >= 8); |
|
3465 bool vex_b = (src_enc >= 8); |
|
3466 bool vex_x = false; |
|
3467 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); |
|
3468 return (((dst_enc & 7) << 3) | (src_enc & 7)); |
|
3469 } |
|
3470 |
|
3471 |
|
3472 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { |
|
3473 if (UseAVX > 0) { |
|
3474 int xreg_enc = xreg->encoding(); |
|
3475 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
|
3476 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); |
|
3477 } else { |
|
3478 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); |
|
3479 rex_prefix(adr, xreg, pre, opc, rex_w); |
|
3480 } |
|
3481 } |
|
3482 |
|
3483 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { |
|
3484 int dst_enc = dst->encoding(); |
|
3485 int src_enc = src->encoding(); |
|
3486 if (UseAVX > 0) { |
|
3487 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
|
3488 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); |
|
3489 } else { |
|
3490 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); |
|
3491 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); |
|
3492 } |
|
3493 } |
3397 |
3494 |
3398 #ifndef _LP64 |
3495 #ifndef _LP64 |
3399 |
3496 |
3400 void Assembler::incl(Register dst) { |
3497 void Assembler::incl(Register dst) { |
3401 // Don't use it directly. Use MacroAssembler::incrementl() instead. |
3498 // Don't use it directly. Use MacroAssembler::incrementl() instead. |
3402 emit_byte(0x40 | dst->encoding()); |
3499 emit_byte(0x40 | dst->encoding()); |
3403 } |
3500 } |
3404 |
3501 |
3405 void Assembler::lea(Register dst, Address src) { |
3502 void Assembler::lea(Register dst, Address src) { |
3406 leal(dst, src); |
3503 leal(dst, src); |
3407 } |
3504 } |
3916 emit_operand(reg, adr); |
4045 emit_operand(reg, adr); |
3917 } |
4046 } |
3918 |
4047 |
3919 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { |
4048 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { |
3920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4049 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3921 emit_byte(0xF2); |
4050 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
3922 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
3923 emit_byte(0x0F); |
|
3924 emit_byte(0x2A); |
4051 emit_byte(0x2A); |
3925 emit_byte(0xC0 | encode); |
4052 emit_byte(0xC0 | encode); |
3926 } |
4053 } |
3927 |
4054 |
|
4055 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
|
4056 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
|
4057 InstructionMark im(this); |
|
4058 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); |
|
4059 emit_byte(0x2A); |
|
4060 emit_operand(dst, src); |
|
4061 } |
|
4062 |
3928 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
4063 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
3929 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
4064 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3930 emit_byte(0xF3); |
4065 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
3931 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
3932 emit_byte(0x0F); |
|
3933 emit_byte(0x2A); |
4066 emit_byte(0x2A); |
3934 emit_byte(0xC0 | encode); |
4067 emit_byte(0xC0 | encode); |
3935 } |
4068 } |
3936 |
4069 |
|
4070 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
|
4071 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
|
4072 InstructionMark im(this); |
|
4073 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); |
|
4074 emit_byte(0x2A); |
|
4075 emit_operand(dst, src); |
|
4076 } |
|
4077 |
3937 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
4078 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
3938 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4079 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3939 emit_byte(0xF2); |
4080 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
3940 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
3941 emit_byte(0x0F); |
|
3942 emit_byte(0x2C); |
4081 emit_byte(0x2C); |
3943 emit_byte(0xC0 | encode); |
4082 emit_byte(0xC0 | encode); |
3944 } |
4083 } |
3945 |
4084 |
3946 void Assembler::cvttss2siq(Register dst, XMMRegister src) { |
4085 void Assembler::cvttss2siq(Register dst, XMMRegister src) { |
3947 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
4086 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3948 emit_byte(0xF3); |
4087 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
3949 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
3950 emit_byte(0x0F); |
|
3951 emit_byte(0x2C); |
4088 emit_byte(0x2C); |
3952 emit_byte(0xC0 | encode); |
4089 emit_byte(0xC0 | encode); |
3953 } |
4090 } |
3954 |
4091 |
3955 void Assembler::decl(Register dst) { |
4092 void Assembler::decl(Register dst) { |
5678 |
5811 |
5679 void MacroAssembler::addptr(Address dst, Register src) { |
5812 void MacroAssembler::addptr(Address dst, Register src) { |
5680 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); |
5813 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); |
5681 } |
5814 } |
5682 |
5815 |
|
5816 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { |
|
5817 if (reachable(src)) { |
|
5818 Assembler::addsd(dst, as_Address(src)); |
|
5819 } else { |
|
5820 lea(rscratch1, src); |
|
5821 Assembler::addsd(dst, Address(rscratch1, 0)); |
|
5822 } |
|
5823 } |
|
5824 |
|
5825 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { |
|
5826 if (reachable(src)) { |
|
5827 addss(dst, as_Address(src)); |
|
5828 } else { |
|
5829 lea(rscratch1, src); |
|
5830 addss(dst, Address(rscratch1, 0)); |
|
5831 } |
|
5832 } |
|
5833 |
5683 void MacroAssembler::align(int modulus) { |
5834 void MacroAssembler::align(int modulus) { |
5684 if (offset() % modulus != 0) { |
5835 if (offset() % modulus != 0) { |
5685 nop(modulus - (offset() % modulus)); |
5836 nop(modulus - (offset() % modulus)); |
5686 } |
5837 } |
5687 } |
5838 } |
5688 |
5839 |
5689 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { |
5840 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { |
|
5841 // Used in sign-masking with aligned address. |
|
5842 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
5690 if (reachable(src)) { |
5843 if (reachable(src)) { |
5691 andpd(dst, as_Address(src)); |
5844 Assembler::andpd(dst, as_Address(src)); |
5692 } else { |
5845 } else { |
5693 lea(rscratch1, src); |
5846 lea(rscratch1, src); |
5694 andpd(dst, Address(rscratch1, 0)); |
5847 Assembler::andpd(dst, Address(rscratch1, 0)); |
|
5848 } |
|
5849 } |
|
5850 |
|
5851 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { |
|
5852 // Used in sign-masking with aligned address. |
|
5853 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
|
5854 if (reachable(src)) { |
|
5855 Assembler::andps(dst, as_Address(src)); |
|
5856 } else { |
|
5857 lea(rscratch1, src); |
|
5858 Assembler::andps(dst, Address(rscratch1, 0)); |
5695 } |
5859 } |
5696 } |
5860 } |
5697 |
5861 |
5698 void MacroAssembler::andptr(Register dst, int32_t imm32) { |
5862 void MacroAssembler::andptr(Register dst, int32_t imm32) { |
5699 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); |
5863 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); |
6801 |
6983 |
6802 void MacroAssembler::movptr(Address dst, Register src) { |
6984 void MacroAssembler::movptr(Address dst, Register src) { |
6803 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
6985 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
6804 } |
6986 } |
6805 |
6987 |
|
6988 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { |
|
6989 if (reachable(src)) { |
|
6990 Assembler::movsd(dst, as_Address(src)); |
|
6991 } else { |
|
6992 lea(rscratch1, src); |
|
6993 Assembler::movsd(dst, Address(rscratch1, 0)); |
|
6994 } |
|
6995 } |
|
6996 |
6806 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
6997 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
6807 if (reachable(src)) { |
6998 if (reachable(src)) { |
6808 movss(dst, as_Address(src)); |
6999 Assembler::movss(dst, as_Address(src)); |
6809 } else { |
7000 } else { |
6810 lea(rscratch1, src); |
7001 lea(rscratch1, src); |
6811 movss(dst, Address(rscratch1, 0)); |
7002 Assembler::movss(dst, Address(rscratch1, 0)); |
|
7003 } |
|
7004 } |
|
7005 |
|
7006 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { |
|
7007 if (reachable(src)) { |
|
7008 Assembler::mulsd(dst, as_Address(src)); |
|
7009 } else { |
|
7010 lea(rscratch1, src); |
|
7011 Assembler::mulsd(dst, Address(rscratch1, 0)); |
|
7012 } |
|
7013 } |
|
7014 |
|
7015 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { |
|
7016 if (reachable(src)) { |
|
7017 Assembler::mulss(dst, as_Address(src)); |
|
7018 } else { |
|
7019 lea(rscratch1, src); |
|
7020 Assembler::mulss(dst, Address(rscratch1, 0)); |
6812 } |
7021 } |
6813 } |
7022 } |
6814 |
7023 |
6815 void MacroAssembler::null_check(Register reg, int offset) { |
7024 void MacroAssembler::null_check(Register reg, int offset) { |
6816 if (needs_explicit_null_check(offset)) { |
7025 if (needs_explicit_null_check(offset)) { |
7873 bind(L_fallthrough); |
8118 bind(L_fallthrough); |
7874 } |
8119 } |
7875 |
8120 |
7876 |
8121 |
7877 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
8122 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
7878 ucomisd(dst, as_Address(src)); |
8123 if (reachable(src)) { |
|
8124 Assembler::ucomisd(dst, as_Address(src)); |
|
8125 } else { |
|
8126 lea(rscratch1, src); |
|
8127 Assembler::ucomisd(dst, Address(rscratch1, 0)); |
|
8128 } |
7879 } |
8129 } |
7880 |
8130 |
7881 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { |
8131 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { |
7882 ucomiss(dst, as_Address(src)); |
8132 if (reachable(src)) { |
|
8133 Assembler::ucomiss(dst, as_Address(src)); |
|
8134 } else { |
|
8135 lea(rscratch1, src); |
|
8136 Assembler::ucomiss(dst, Address(rscratch1, 0)); |
|
8137 } |
7883 } |
8138 } |
7884 |
8139 |
7885 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { |
8140 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { |
|
8141 // Used in sign-bit flipping with aligned address. |
|
8142 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
7886 if (reachable(src)) { |
8143 if (reachable(src)) { |
7887 xorpd(dst, as_Address(src)); |
8144 Assembler::xorpd(dst, as_Address(src)); |
7888 } else { |
8145 } else { |
7889 lea(rscratch1, src); |
8146 lea(rscratch1, src); |
7890 xorpd(dst, Address(rscratch1, 0)); |
8147 Assembler::xorpd(dst, Address(rscratch1, 0)); |
7891 } |
8148 } |
7892 } |
8149 } |
7893 |
8150 |
7894 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { |
8151 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { |
|
8152 // Used in sign-bit flipping with aligned address. |
|
8153 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
7895 if (reachable(src)) { |
8154 if (reachable(src)) { |
7896 xorps(dst, as_Address(src)); |
8155 Assembler::xorps(dst, as_Address(src)); |
7897 } else { |
8156 } else { |
7898 lea(rscratch1, src); |
8157 lea(rscratch1, src); |
7899 xorps(dst, Address(rscratch1, 0)); |
8158 Assembler::xorps(dst, Address(rscratch1, 0)); |
7900 } |
8159 } |
7901 } |
8160 } |
7902 |
8161 |
7903 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
8162 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
7904 if (VM_Version::supports_cmov()) { |
8163 if (VM_Version::supports_cmov()) { |