479 // To assure the IRIW property on processors that are not multiple copy |
479 // To assure the IRIW property on processors that are not multiple copy |
480 // atomic, sync instructions must be issued between volatile reads to |
480 // atomic, sync instructions must be issued between volatile reads to |
481 // assure their ordering, instead of after volatile stores. |
481 // assure their ordering, instead of after volatile stores. |
482 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" |
482 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" |
483 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) |
483 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) |
484 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC |
484 #ifdef CPU_MULTI_COPY_ATOMIC |
485 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; |
485 // Not needed. |
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486 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; |
486 #else |
487 #else |
487 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; |
488 // From all non-multi-copy-atomic architectures, only PPC64 supports IRIW at the moment. |
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489 // Final decision is subject to JEP 188: Java Memory Model Update. |
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490 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = PPC64_ONLY(true) NOT_PPC64(false); |
488 #endif |
491 #endif |
489 |
492 |
490 // The expected size in bytes of a cache line, used to pad data structures. |
493 // The expected size in bytes of a cache line, used to pad data structures. |
491 #ifndef DEFAULT_CACHE_LINE_SIZE |
494 #ifndef DEFAULT_CACHE_LINE_SIZE |
492 #define DEFAULT_CACHE_LINE_SIZE 64 |
495 #define DEFAULT_CACHE_LINE_SIZE 64 |