1278       break;

  1278       break;

  1279     case Op_AbsVB:

  1279     case Op_AbsVB:

  1280     case Op_AbsVS:

  1280     case Op_AbsVS:

  1281     case Op_AbsVI:

  1281     case Op_AbsVI:

  1282     case Op_AddReductionVI:

  1282     case Op_AddReductionVI:

  1284         ret_value = false;

  1284         ret_value = false;

  1285       break;

  1285       break;

  1286     case Op_MulReductionVI:

  1286     case Op_MulReductionVI:

  1287       if (UseSSE < 4) // requires at least SSE4

  1287       if (UseSSE < 4) // requires at least SSE4

  1288         ret_value = false;

  1288         ret_value = false;