equal
deleted
inserted
replaced
1195 } |
1195 } |
1196 } |
1196 } |
1197 if (in_regs[i].first()->is_Register() && |
1197 if (in_regs[i].first()->is_Register() && |
1198 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { |
1198 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { |
1199 int offset = slot * VMRegImpl::stack_slot_size; |
1199 int offset = slot * VMRegImpl::stack_slot_size; |
1200 slot += VMRegImpl::slots_per_word; |
|
1201 if (map != NULL) { |
1200 if (map != NULL) { |
1202 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); |
1201 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); |
1203 if (in_sig_bt[i] == T_ARRAY) { |
1202 if (in_sig_bt[i] == T_ARRAY) { |
1204 map->set_oop(VMRegImpl::stack2reg(slot));; |
1203 map->set_oop(VMRegImpl::stack2reg(slot));; |
1205 } |
1204 } |
1206 } else { |
1205 } else { |
1207 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); |
1206 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); |
1208 } |
1207 } |
|
1208 slot += VMRegImpl::slots_per_word; |
1209 } |
1209 } |
1210 } |
1210 } |
1211 // Save or restore single word registers |
1211 // Save or restore single word registers |
1212 for ( int i = 0; i < total_in_args; i++) { |
1212 for ( int i = 0; i < total_in_args; i++) { |
1213 if (in_regs[i].first()->is_Register()) { |
1213 if (in_regs[i].first()->is_Register()) { |