1 /* |
1 /* |
2 * Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved. |
2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * |
4 * |
5 * This code is free software; you can redistribute it and/or modify it |
5 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as |
6 * under the terms of the GNU General Public License version 2 only, as |
7 * published by the Free Software Foundation. |
7 * published by the Free Software Foundation. |
58 } |
58 } |
59 compiler_barrier(); |
59 compiler_barrier(); |
60 } |
60 } |
61 |
61 |
62 template<> |
62 template<> |
63 inline void OrderAccess::specialized_release_store_fence<jbyte> (volatile jbyte* p, jbyte v) { |
63 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE> |
64 __asm__ volatile ( "xchgb (%2),%0" |
64 VALUE_OBJ_CLASS_SPEC |
65 : "=q" (v) |
65 { |
66 : "0" (v), "r" (p) |
66 template <typename T> |
67 : "memory"); |
67 void operator()(T v, volatile T* p) const { |
68 } |
68 __asm__ volatile ( "xchgb (%2),%0" |
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69 : "=q" (v) |
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70 : "0" (v), "r" (p) |
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71 : "memory"); |
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72 } |
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73 }; |
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74 |
69 template<> |
75 template<> |
70 inline void OrderAccess::specialized_release_store_fence<jshort>(volatile jshort* p, jshort v) { |
76 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE> |
71 __asm__ volatile ( "xchgw (%2),%0" |
77 VALUE_OBJ_CLASS_SPEC |
72 : "=r" (v) |
78 { |
73 : "0" (v), "r" (p) |
79 template <typename T> |
74 : "memory"); |
80 void operator()(T v, volatile T* p) const { |
75 } |
81 __asm__ volatile ( "xchgw (%2),%0" |
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82 : "=r" (v) |
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83 : "0" (v), "r" (p) |
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84 : "memory"); |
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85 } |
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86 }; |
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87 |
76 template<> |
88 template<> |
77 inline void OrderAccess::specialized_release_store_fence<jint> (volatile jint* p, jint v) { |
89 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE> |
78 __asm__ volatile ( "xchgl (%2),%0" |
90 VALUE_OBJ_CLASS_SPEC |
79 : "=r" (v) |
91 { |
80 : "0" (v), "r" (p) |
92 template <typename T> |
81 : "memory"); |
93 void operator()(T v, volatile T* p) const { |
82 } |
94 __asm__ volatile ( "xchgl (%2),%0" |
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95 : "=r" (v) |
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96 : "0" (v), "r" (p) |
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97 : "memory"); |
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98 } |
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99 }; |
83 |
100 |
84 #ifdef AMD64 |
101 #ifdef AMD64 |
85 template<> |
102 template<> |
86 inline void OrderAccess::specialized_release_store_fence<jlong> (volatile jlong* p, jlong v) { |
103 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE> |
87 __asm__ volatile ( "xchgq (%2), %0" |
104 VALUE_OBJ_CLASS_SPEC |
88 : "=r" (v) |
105 { |
89 : "0" (v), "r" (p) |
106 template <typename T> |
90 : "memory"); |
107 void operator()(T v, volatile T* p) const { |
91 } |
108 __asm__ volatile ( "xchgq (%2), %0" |
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109 : "=r" (v) |
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110 : "0" (v), "r" (p) |
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111 : "memory"); |
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112 } |
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113 }; |
92 #endif // AMD64 |
114 #endif // AMD64 |
93 |
115 |
94 template<> |
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95 inline void OrderAccess::specialized_release_store_fence<jfloat> (volatile jfloat* p, jfloat v) { |
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96 release_store_fence((volatile jint*)p, jint_cast(v)); |
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97 } |
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98 template<> |
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99 inline void OrderAccess::specialized_release_store_fence<jdouble>(volatile jdouble* p, jdouble v) { |
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100 release_store_fence((volatile jlong*)p, jlong_cast(v)); |
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101 } |
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102 |
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103 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1 |
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104 |
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105 #endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP |
116 #endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_INLINE_HPP |