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1 /* |
1 /* |
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. |
3 * Copyright (c) 2012, 2013 SAP SE. All rights reserved. |
3 * Copyright (c) 2012, 2018 SAP SE. All rights reserved. |
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
5 * |
5 * |
6 * This code is free software; you can redistribute it and/or modify it |
6 * This code is free software; you can redistribute it and/or modify it |
7 * under the terms of the GNU General Public License version 2 only, as |
7 * under the terms of the GNU General Public License version 2 only, as |
8 * published by the Free Software Foundation. |
8 * published by the Free Software Foundation. |
22 * questions. |
22 * questions. |
23 * |
23 * |
24 */ |
24 */ |
25 |
25 |
26 #include "precompiled.hpp" |
26 #include "precompiled.hpp" |
27 #include "assembler_ppc.inline.hpp" |
|
28 #include "runtime/icache.hpp" |
27 #include "runtime/icache.hpp" |
29 |
28 |
30 // Use inline assembler to implement icache flush. |
29 // Use inline assembler to implement icache flush. |
31 int ICache::ppc64_flush_icache(address start, int lines, int magic) { |
30 int ICache::ppc64_flush_icache(address start, int lines, int magic) { |
32 address end = start + (unsigned int)lines*ICache::line_size; |
31 address end = start + (unsigned int)lines*ICache::line_size; |
33 assert(start <= end, "flush_icache parms"); |
32 assert(start <= end, "flush_icache parms"); |
34 |
33 |
35 // store modified cache lines from data cache |
34 // Store modified cache lines from data cache. |
36 for (address a = start; a < end; a += ICache::line_size) { |
35 for (address a = start; a < end; a += ICache::line_size) { |
37 __asm__ __volatile__( |
36 __asm__ __volatile__( |
38 "dcbst 0, %0 \n" |
37 "dcbst 0, %0 \n" |
39 : |
38 : |
40 : "r" (a) |
39 : "r" (a) |
46 "sync \n" |
45 "sync \n" |
47 : |
46 : |
48 : |
47 : |
49 : "memory"); |
48 : "memory"); |
50 |
49 |
51 // invalidate respective cache lines in instruction cache |
50 // Invalidate respective cache lines in instruction cache. |
52 for (address a = start; a < end; a += ICache::line_size) { |
51 for (address a = start; a < end; a += ICache::line_size) { |
53 __asm__ __volatile__( |
52 __asm__ __volatile__( |
54 "icbi 0, %0 \n" |
53 "icbi 0, %0 \n" |
55 : |
54 : |
56 : "r" (a) |
55 : "r" (a) |
57 : "memory"); |
56 : "memory"); |
58 } |
57 } |
59 |
58 |
60 // discard fetched instructions |
59 // Discard fetched instructions. |
61 __asm__ __volatile__( |
60 __asm__ __volatile__( |
62 "isync \n" |
61 "isync \n" |
63 : |
62 : |
64 : |
63 : |
65 : "memory"); |
64 : "memory"); |
69 |
68 |
70 void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) { |
69 void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) { |
71 |
70 |
72 *flush_icache_stub = (ICache::flush_icache_stub_t)ICache::ppc64_flush_icache; |
71 *flush_icache_stub = (ICache::flush_icache_stub_t)ICache::ppc64_flush_icache; |
73 |
72 |
74 // First call to flush itself |
73 // First call to flush itself. |
|
74 // Pointless since we call C, but it is expected to get |
|
75 // executed during VM_Version::determine_features(). |
75 ICache::invalidate_range((address)(*flush_icache_stub), 0); |
76 ICache::invalidate_range((address)(*flush_icache_stub), 0); |
76 } |
77 } |