hotspot/src/cpu/x86/vm/x86_32.ad
changeset 35146 9ebfec283f56
parent 35135 dd2ce9021031
child 35540 e001ad24dcdb
equal deleted inserted replaced
35145:a4ffa2fa7f4d 35146:9ebfec283f56
  9883   ins_encode( Push_Reg_DPR(src),
  9883   ins_encode( Push_Reg_DPR(src),
  9884               OpcS, OpcP, Pop_Reg_DPR(dst) );
  9884               OpcS, OpcP, Pop_Reg_DPR(dst) );
  9885   ins_pipe( pipe_slow );
  9885   ins_pipe( pipe_slow );
  9886 %}
  9886 %}
  9887 
  9887 
  9888 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
       
  9889   predicate (UseSSE<=1);
       
  9890   match(Set Y (PowD X Y));  // Raise X to the Yth power
       
  9891   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
       
  9892   format %{ "fast_pow $X $Y -> $Y  // KILL $rax, $rcx, $rdx" %}
       
  9893   ins_encode %{
       
  9894     __ subptr(rsp, 8);
       
  9895     __ fld_s($X$$reg - 1);
       
  9896     __ fast_pow();
       
  9897     __ addptr(rsp, 8);
       
  9898   %}
       
  9899   ins_pipe( pipe_slow );
       
  9900 %}
       
  9901 
       
  9902 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
       
  9903   predicate (UseSSE>=2);
       
  9904   match(Set dst (PowD src0 src1));  // Raise src0 to the src1'th power
       
  9905   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
       
  9906   format %{ "fast_pow $src0 $src1 -> $dst  // KILL $rax, $rcx, $rdx" %}
       
  9907   ins_encode %{
       
  9908     __ subptr(rsp, 8);
       
  9909     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
       
  9910     __ fld_d(Address(rsp, 0));
       
  9911     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
       
  9912     __ fld_d(Address(rsp, 0));
       
  9913     __ fast_pow();
       
  9914     __ fstp_d(Address(rsp, 0));
       
  9915     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
       
  9916     __ addptr(rsp, 8);
       
  9917   %}
       
  9918   ins_pipe( pipe_slow );
       
  9919 %}
       
  9920 
       
  9921 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
  9888 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
  9922   predicate (UseSSE<=1);
  9889   predicate (UseSSE<=1);
  9923   // The source Double operand on FPU stack
  9890   // The source Double operand on FPU stack
  9924   match(Set dst (Log10D src));
  9891   match(Set dst (Log10D src));
  9925   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
  9892   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number