9883 ins_encode( Push_Reg_DPR(src), |
9883 ins_encode( Push_Reg_DPR(src), |
9884 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
9884 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
9885 ins_pipe( pipe_slow ); |
9885 ins_pipe( pipe_slow ); |
9886 %} |
9886 %} |
9887 |
9887 |
9888 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
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9889 predicate (UseSSE<=1); |
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9890 match(Set Y (PowD X Y)); // Raise X to the Yth power |
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9891 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
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9892 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
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9893 ins_encode %{ |
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9894 __ subptr(rsp, 8); |
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9895 __ fld_s($X$$reg - 1); |
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9896 __ fast_pow(); |
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9897 __ addptr(rsp, 8); |
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9898 %} |
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9899 ins_pipe( pipe_slow ); |
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9900 %} |
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9901 |
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9902 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
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9903 predicate (UseSSE>=2); |
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9904 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
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9905 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
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9906 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
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9907 ins_encode %{ |
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9908 __ subptr(rsp, 8); |
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9909 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
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9910 __ fld_d(Address(rsp, 0)); |
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9911 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
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9912 __ fld_d(Address(rsp, 0)); |
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9913 __ fast_pow(); |
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9914 __ fstp_d(Address(rsp, 0)); |
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9915 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
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9916 __ addptr(rsp, 8); |
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9917 %} |
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9918 ins_pipe( pipe_slow ); |
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9919 %} |
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9920 |
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9921 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
9888 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
9922 predicate (UseSSE<=1); |
9889 predicate (UseSSE<=1); |
9923 // The source Double operand on FPU stack |
9890 // The source Double operand on FPU stack |
9924 match(Set dst (Log10D src)); |
9891 match(Set dst (Log10D src)); |
9925 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number |
9892 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number |