544 // emit 32 bit value and construct relocation entry from RelocationHolder |
544 // emit 32 bit value and construct relocation entry from RelocationHolder |
545 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
545 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
546 #ifdef ASSERT |
546 #ifdef ASSERT |
547 if (rspec.reloc()->type() == relocInfo::oop_type && |
547 if (rspec.reloc()->type() == relocInfo::oop_type && |
548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { |
548 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { |
549 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
549 assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop"); |
550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code"); |
550 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code"); |
551 } |
551 } |
552 #endif |
552 #endif |
553 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
553 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
554 cbuf.insts()->emit_int32(d32); |
554 cbuf.insts()->emit_int32(d32); |
571 // emit 64 bit value and construct relocation entry from RelocationHolder |
571 // emit 64 bit value and construct relocation entry from RelocationHolder |
572 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
572 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
573 #ifdef ASSERT |
573 #ifdef ASSERT |
574 if (rspec.reloc()->type() == relocInfo::oop_type && |
574 if (rspec.reloc()->type() == relocInfo::oop_type && |
575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { |
575 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { |
576 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
576 assert(Universe::heap()->is_in((address)d64), "should be real oop"); |
577 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code"); |
577 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code"); |
578 } |
578 } |
579 #endif |
579 #endif |
580 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
580 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
581 cbuf.insts()->emit_int64(d64); |
581 cbuf.insts()->emit_int64(d64); |
872 MacroAssembler _masm(&cbuf); |
872 MacroAssembler _masm(&cbuf); |
873 |
873 |
874 int framesize = C->frame_size_in_bytes(); |
874 int framesize = C->frame_size_in_bytes(); |
875 int bangsize = C->bang_size_in_bytes(); |
875 int bangsize = C->bang_size_in_bytes(); |
876 |
876 |
|
877 if (C->clinit_barrier_on_entry()) { |
|
878 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); |
|
879 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); |
|
880 |
|
881 Label L_skip_barrier; |
|
882 Register klass = rscratch1; |
|
883 |
|
884 __ mov_metadata(klass, C->method()->holder()->constant_encoding()); |
|
885 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/); |
|
886 |
|
887 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path |
|
888 |
|
889 __ bind(L_skip_barrier); |
|
890 } |
|
891 |
877 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL); |
892 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL); |
878 |
893 |
879 C->set_frame_complete(cbuf.insts_size()); |
894 C->set_frame_complete(cbuf.insts_size()); |
880 |
895 |
881 if (C->has_mach_constant_base_node()) { |
896 if (C->has_mach_constant_base_node()) { |
1041 |
1056 |
1042 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
1057 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
1043 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
1058 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
1044 int src_hi, int dst_hi, uint ireg, outputStream* st); |
1059 int src_hi, int dst_hi, uint ireg, outputStream* st); |
1045 |
1060 |
1046 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
1061 int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
1047 int stack_offset, int reg, uint ireg, outputStream* st); |
1062 int stack_offset, int reg, uint ireg, outputStream* st); |
1048 |
1063 |
1049 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
1064 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
1050 int dst_offset, uint ireg, outputStream* st) { |
1065 int dst_offset, uint ireg, outputStream* st) { |
1051 if (cbuf) { |
1066 if (cbuf) { |
1052 MacroAssembler _masm(cbuf); |
1067 MacroAssembler _masm(cbuf); |
4243 overflow(0x0, "o"); |
4258 overflow(0x0, "o"); |
4244 no_overflow(0x1, "no"); |
4259 no_overflow(0x1, "no"); |
4245 %} |
4260 %} |
4246 %} |
4261 %} |
4247 |
4262 |
4248 // Operands for bound floating pointer register arguments |
|
4249 operand rxmm0() %{ |
|
4250 constraint(ALLOC_IN_RC(xmm0_reg)); |
|
4251 match(VecX); |
|
4252 format%{%} |
|
4253 interface(REG_INTER); |
|
4254 %} |
|
4255 operand rxmm1() %{ |
|
4256 constraint(ALLOC_IN_RC(xmm1_reg)); |
|
4257 match(VecX); |
|
4258 format%{%} |
|
4259 interface(REG_INTER); |
|
4260 %} |
|
4261 operand rxmm2() %{ |
|
4262 constraint(ALLOC_IN_RC(xmm2_reg)); |
|
4263 match(VecX); |
|
4264 format%{%} |
|
4265 interface(REG_INTER); |
|
4266 %} |
|
4267 operand rxmm3() %{ |
|
4268 constraint(ALLOC_IN_RC(xmm3_reg)); |
|
4269 match(VecX); |
|
4270 format%{%} |
|
4271 interface(REG_INTER); |
|
4272 %} |
|
4273 operand rxmm4() %{ |
|
4274 constraint(ALLOC_IN_RC(xmm4_reg)); |
|
4275 match(VecX); |
|
4276 format%{%} |
|
4277 interface(REG_INTER); |
|
4278 %} |
|
4279 operand rxmm5() %{ |
|
4280 constraint(ALLOC_IN_RC(xmm5_reg)); |
|
4281 match(VecX); |
|
4282 format%{%} |
|
4283 interface(REG_INTER); |
|
4284 %} |
|
4285 operand rxmm6() %{ |
|
4286 constraint(ALLOC_IN_RC(xmm6_reg)); |
|
4287 match(VecX); |
|
4288 format%{%} |
|
4289 interface(REG_INTER); |
|
4290 %} |
|
4291 operand rxmm7() %{ |
|
4292 constraint(ALLOC_IN_RC(xmm7_reg)); |
|
4293 match(VecX); |
|
4294 format%{%} |
|
4295 interface(REG_INTER); |
|
4296 %} |
|
4297 operand rxmm8() %{ |
|
4298 constraint(ALLOC_IN_RC(xmm8_reg)); |
|
4299 match(VecX); |
|
4300 format%{%} |
|
4301 interface(REG_INTER); |
|
4302 %} |
|
4303 operand rxmm9() %{ |
|
4304 constraint(ALLOC_IN_RC(xmm9_reg)); |
|
4305 match(VecX); |
|
4306 format%{%} |
|
4307 interface(REG_INTER); |
|
4308 %} |
|
4309 operand rxmm10() %{ |
|
4310 constraint(ALLOC_IN_RC(xmm10_reg)); |
|
4311 match(VecX); |
|
4312 format%{%} |
|
4313 interface(REG_INTER); |
|
4314 %} |
|
4315 operand rxmm11() %{ |
|
4316 constraint(ALLOC_IN_RC(xmm11_reg)); |
|
4317 match(VecX); |
|
4318 format%{%} |
|
4319 interface(REG_INTER); |
|
4320 %} |
|
4321 operand rxmm12() %{ |
|
4322 constraint(ALLOC_IN_RC(xmm12_reg)); |
|
4323 match(VecX); |
|
4324 format%{%} |
|
4325 interface(REG_INTER); |
|
4326 %} |
|
4327 operand rxmm13() %{ |
|
4328 constraint(ALLOC_IN_RC(xmm13_reg)); |
|
4329 match(VecX); |
|
4330 format%{%} |
|
4331 interface(REG_INTER); |
|
4332 %} |
|
4333 operand rxmm14() %{ |
|
4334 constraint(ALLOC_IN_RC(xmm14_reg)); |
|
4335 match(VecX); |
|
4336 format%{%} |
|
4337 interface(REG_INTER); |
|
4338 %} |
|
4339 operand rxmm15() %{ |
|
4340 constraint(ALLOC_IN_RC(xmm15_reg)); |
|
4341 match(VecX); |
|
4342 format%{%} |
|
4343 interface(REG_INTER); |
|
4344 %} |
|
4345 operand rxmm16() %{ |
|
4346 constraint(ALLOC_IN_RC(xmm16_reg)); |
|
4347 match(VecX); |
|
4348 format%{%} |
|
4349 interface(REG_INTER); |
|
4350 %} |
|
4351 operand rxmm17() %{ |
|
4352 constraint(ALLOC_IN_RC(xmm17_reg)); |
|
4353 match(VecX); |
|
4354 format%{%} |
|
4355 interface(REG_INTER); |
|
4356 %} |
|
4357 operand rxmm18() %{ |
|
4358 constraint(ALLOC_IN_RC(xmm18_reg)); |
|
4359 match(VecX); |
|
4360 format%{%} |
|
4361 interface(REG_INTER); |
|
4362 %} |
|
4363 operand rxmm19() %{ |
|
4364 constraint(ALLOC_IN_RC(xmm19_reg)); |
|
4365 match(VecX); |
|
4366 format%{%} |
|
4367 interface(REG_INTER); |
|
4368 %} |
|
4369 operand rxmm20() %{ |
|
4370 constraint(ALLOC_IN_RC(xmm20_reg)); |
|
4371 match(VecX); |
|
4372 format%{%} |
|
4373 interface(REG_INTER); |
|
4374 %} |
|
4375 operand rxmm21() %{ |
|
4376 constraint(ALLOC_IN_RC(xmm21_reg)); |
|
4377 match(VecX); |
|
4378 format%{%} |
|
4379 interface(REG_INTER); |
|
4380 %} |
|
4381 operand rxmm22() %{ |
|
4382 constraint(ALLOC_IN_RC(xmm22_reg)); |
|
4383 match(VecX); |
|
4384 format%{%} |
|
4385 interface(REG_INTER); |
|
4386 %} |
|
4387 operand rxmm23() %{ |
|
4388 constraint(ALLOC_IN_RC(xmm23_reg)); |
|
4389 match(VecX); |
|
4390 format%{%} |
|
4391 interface(REG_INTER); |
|
4392 %} |
|
4393 operand rxmm24() %{ |
|
4394 constraint(ALLOC_IN_RC(xmm24_reg)); |
|
4395 match(VecX); |
|
4396 format%{%} |
|
4397 interface(REG_INTER); |
|
4398 %} |
|
4399 operand rxmm25() %{ |
|
4400 constraint(ALLOC_IN_RC(xmm25_reg)); |
|
4401 match(VecX); |
|
4402 format%{%} |
|
4403 interface(REG_INTER); |
|
4404 %} |
|
4405 operand rxmm26() %{ |
|
4406 constraint(ALLOC_IN_RC(xmm26_reg)); |
|
4407 match(VecX); |
|
4408 format%{%} |
|
4409 interface(REG_INTER); |
|
4410 %} |
|
4411 operand rxmm27() %{ |
|
4412 constraint(ALLOC_IN_RC(xmm27_reg)); |
|
4413 match(VecX); |
|
4414 format%{%} |
|
4415 interface(REG_INTER); |
|
4416 %} |
|
4417 operand rxmm28() %{ |
|
4418 constraint(ALLOC_IN_RC(xmm28_reg)); |
|
4419 match(VecX); |
|
4420 format%{%} |
|
4421 interface(REG_INTER); |
|
4422 %} |
|
4423 operand rxmm29() %{ |
|
4424 constraint(ALLOC_IN_RC(xmm29_reg)); |
|
4425 match(VecX); |
|
4426 format%{%} |
|
4427 interface(REG_INTER); |
|
4428 %} |
|
4429 operand rxmm30() %{ |
|
4430 constraint(ALLOC_IN_RC(xmm30_reg)); |
|
4431 match(VecX); |
|
4432 format%{%} |
|
4433 interface(REG_INTER); |
|
4434 %} |
|
4435 operand rxmm31() %{ |
|
4436 constraint(ALLOC_IN_RC(xmm31_reg)); |
|
4437 match(VecX); |
|
4438 format%{%} |
|
4439 interface(REG_INTER); |
|
4440 %} |
|
4441 |
|
4442 //----------OPERAND CLASSES---------------------------------------------------- |
4263 //----------OPERAND CLASSES---------------------------------------------------- |
4443 // Operand Classes are groups of operands that are used as to simplify |
4264 // Operand Classes are groups of operands that are used as to simplify |
4444 // instruction definitions by not requiring the AD writer to specify separate |
4265 // instruction definitions by not requiring the AD writer to specify separate |
4445 // instructions for every form of operand when the instruction accepts |
4266 // instructions for every form of operand when the instruction accepts |
4446 // multiple operand types with the same basic encoding and format. The classic |
4267 // multiple operand types with the same basic encoding and format. The classic |
5329 |
5150 |
5330 // Load Pointer |
5151 // Load Pointer |
5331 instruct loadP(rRegP dst, memory mem) |
5152 instruct loadP(rRegP dst, memory mem) |
5332 %{ |
5153 %{ |
5333 match(Set dst (LoadP mem)); |
5154 match(Set dst (LoadP mem)); |
|
5155 predicate(n->as_Load()->barrier_data() == 0); |
5334 |
5156 |
5335 ins_cost(125); // XXX |
5157 ins_cost(125); // XXX |
5336 format %{ "movq $dst, $mem\t# ptr" %} |
5158 format %{ "movq $dst, $mem\t# ptr" %} |
5337 opcode(0x8B); |
5159 opcode(0x8B); |
5338 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5160 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
5526 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5348 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5527 %} |
5349 %} |
5528 ins_pipe( pipe_slow ); |
5350 ins_pipe( pipe_slow ); |
5529 %} |
5351 %} |
5530 |
5352 |
5531 instruct maxF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{ |
5353 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{ |
5532 predicate(UseAVX > 0 && n->is_reduction()); |
5354 predicate(UseAVX > 0 && n->is_reduction()); |
5533 match(Set dst (MaxF a b)); |
5355 match(Set dst (MaxF a b)); |
5534 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5356 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5535 |
5357 |
5536 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %} |
5358 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %} |
5562 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5384 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5563 %} |
5385 %} |
5564 ins_pipe( pipe_slow ); |
5386 ins_pipe( pipe_slow ); |
5565 %} |
5387 %} |
5566 |
5388 |
5567 instruct maxD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{ |
5389 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{ |
5568 predicate(UseAVX > 0 && n->is_reduction()); |
5390 predicate(UseAVX > 0 && n->is_reduction()); |
5569 match(Set dst (MaxD a b)); |
5391 match(Set dst (MaxD a b)); |
5570 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5392 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5571 |
5393 |
5572 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %} |
5394 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %} |
5598 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5420 __ blendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5599 %} |
5421 %} |
5600 ins_pipe( pipe_slow ); |
5422 ins_pipe( pipe_slow ); |
5601 %} |
5423 %} |
5602 |
5424 |
5603 instruct minF_reduction_reg(regF dst, regF a, regF b, regF xmmt, rRegI tmp, rFlagsReg cr) %{ |
5425 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{ |
5604 predicate(UseAVX > 0 && n->is_reduction()); |
5426 predicate(UseAVX > 0 && n->is_reduction()); |
5605 match(Set dst (MinF a b)); |
5427 match(Set dst (MinF a b)); |
5606 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5428 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5607 |
5429 |
5608 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %} |
5430 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %} |
5634 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5456 __ blendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len); |
5635 %} |
5457 %} |
5636 ins_pipe( pipe_slow ); |
5458 ins_pipe( pipe_slow ); |
5637 %} |
5459 %} |
5638 |
5460 |
5639 instruct minD_reduction_reg(regD dst, regD a, regD b, regD xmmt, rRegL tmp, rFlagsReg cr) %{ |
5461 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{ |
5640 predicate(UseAVX > 0 && n->is_reduction()); |
5462 predicate(UseAVX > 0 && n->is_reduction()); |
5641 match(Set dst (MinD a b)); |
5463 match(Set dst (MinD a b)); |
5642 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5464 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr); |
5643 |
5465 |
5644 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %} |
5466 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %} |
6544 |
6366 |
6545 ins_cost(95); // XXX |
6367 ins_cost(95); // XXX |
6546 format %{ "movsd $dst, $src\t# double stk" %} |
6368 format %{ "movsd $dst, $src\t# double stk" %} |
6547 ins_encode %{ |
6369 ins_encode %{ |
6548 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); |
6370 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); |
|
6371 %} |
|
6372 ins_pipe(pipe_slow); // XXX |
|
6373 %} |
|
6374 |
|
6375 instruct cacheWB(indirect addr) |
|
6376 %{ |
|
6377 predicate(VM_Version::supports_data_cache_line_flush()); |
|
6378 match(CacheWB addr); |
|
6379 |
|
6380 ins_cost(100); |
|
6381 format %{"cache wb $addr" %} |
|
6382 ins_encode %{ |
|
6383 assert($addr->index_position() < 0, "should be"); |
|
6384 assert($addr$$disp == 0, "should be"); |
|
6385 __ cache_wb(Address($addr$$base$$Register, 0)); |
|
6386 %} |
|
6387 ins_pipe(pipe_slow); // XXX |
|
6388 %} |
|
6389 |
|
6390 instruct cacheWBPreSync() |
|
6391 %{ |
|
6392 predicate(VM_Version::supports_data_cache_line_flush()); |
|
6393 match(CacheWBPreSync); |
|
6394 |
|
6395 ins_cost(100); |
|
6396 format %{"cache wb presync" %} |
|
6397 ins_encode %{ |
|
6398 __ cache_wbsync(true); |
|
6399 %} |
|
6400 ins_pipe(pipe_slow); // XXX |
|
6401 %} |
|
6402 |
|
6403 instruct cacheWBPostSync() |
|
6404 %{ |
|
6405 predicate(VM_Version::supports_data_cache_line_flush()); |
|
6406 match(CacheWBPostSync); |
|
6407 |
|
6408 ins_cost(100); |
|
6409 format %{"cache wb postsync" %} |
|
6410 ins_encode %{ |
|
6411 __ cache_wbsync(false); |
6549 %} |
6412 %} |
6550 ins_pipe(pipe_slow); // XXX |
6413 ins_pipe(pipe_slow); // XXX |
6551 %} |
6414 %} |
6552 |
6415 |
6553 //----------BSWAP Instructions------------------------------------------------- |
6416 //----------BSWAP Instructions------------------------------------------------- |
7725 |
7599 |
7726 instruct storePConditional(memory heap_top_ptr, |
7600 instruct storePConditional(memory heap_top_ptr, |
7727 rax_RegP oldval, rRegP newval, |
7601 rax_RegP oldval, rRegP newval, |
7728 rFlagsReg cr) |
7602 rFlagsReg cr) |
7729 %{ |
7603 %{ |
|
7604 predicate(n->as_LoadStore()->barrier_data() == 0); |
7730 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); |
7605 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); |
7731 |
7606 |
7732 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
7607 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
7733 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} |
7608 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} |
7734 opcode(0x0F, 0xB1); |
7609 opcode(0x0F, 0xB1); |
7776 instruct compareAndSwapP(rRegI res, |
7651 instruct compareAndSwapP(rRegI res, |
7777 memory mem_ptr, |
7652 memory mem_ptr, |
7778 rax_RegP oldval, rRegP newval, |
7653 rax_RegP oldval, rRegP newval, |
7779 rFlagsReg cr) |
7654 rFlagsReg cr) |
7780 %{ |
7655 %{ |
7781 predicate(VM_Version::supports_cx8()); |
7656 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0); |
7782 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7657 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
7783 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); |
7658 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); |
7784 effect(KILL cr, KILL oldval); |
7659 effect(KILL cr, KILL oldval); |
7785 |
7660 |
7786 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
7661 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
8018 instruct compareAndExchangeP( |
7893 instruct compareAndExchangeP( |
8019 memory mem_ptr, |
7894 memory mem_ptr, |
8020 rax_RegP oldval, rRegP newval, |
7895 rax_RegP oldval, rRegP newval, |
8021 rFlagsReg cr) |
7896 rFlagsReg cr) |
8022 %{ |
7897 %{ |
8023 predicate(VM_Version::supports_cx8()); |
7898 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0); |
8024 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval))); |
7899 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval))); |
8025 effect(KILL cr); |
7900 effect(KILL cr); |
8026 |
7901 |
8027 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
7902 format %{ "cmpxchgq $mem_ptr,$newval\t# " |
8028 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} |
7903 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} |
8163 ins_pipe( pipe_cmpxchg ); |
8038 ins_pipe( pipe_cmpxchg ); |
8164 %} |
8039 %} |
8165 |
8040 |
8166 instruct xchgP( memory mem, rRegP newval) %{ |
8041 instruct xchgP( memory mem, rRegP newval) %{ |
8167 match(Set newval (GetAndSetP mem newval)); |
8042 match(Set newval (GetAndSetP mem newval)); |
|
8043 predicate(n->as_LoadStore()->barrier_data() == 0); |
8168 format %{ "XCHGQ $newval,[$mem]" %} |
8044 format %{ "XCHGQ $newval,[$mem]" %} |
8169 ins_encode %{ |
8045 ins_encode %{ |
8170 __ xchgq($newval$$Register, $mem$$Address); |
8046 __ xchgq($newval$$Register, $mem$$Address); |
8171 %} |
8047 %} |
8172 ins_pipe( pipe_cmpxchg ); |
8048 ins_pipe( pipe_cmpxchg ); |
11905 %} |
11781 %} |
11906 |
11782 |
11907 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) |
11783 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) |
11908 %{ |
11784 %{ |
11909 match(Set cr (CmpP op1 (LoadP op2))); |
11785 match(Set cr (CmpP op1 (LoadP op2))); |
|
11786 predicate(n->in(2)->as_Load()->barrier_data() == 0); |
11910 |
11787 |
11911 ins_cost(500); // XXX |
11788 ins_cost(500); // XXX |
11912 format %{ "cmpq $op1, $op2\t# ptr" %} |
11789 format %{ "cmpq $op1, $op2\t# ptr" %} |
11913 opcode(0x3B); /* Opcode 3B /r */ |
11790 opcode(0x3B); /* Opcode 3B /r */ |
11914 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11791 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11930 // Compare raw pointer (used in out-of-heap check). |
11807 // Compare raw pointer (used in out-of-heap check). |
11931 // Only works because non-oop pointers must be raw pointers |
11808 // Only works because non-oop pointers must be raw pointers |
11932 // and raw pointers have no anti-dependencies. |
11809 // and raw pointers have no anti-dependencies. |
11933 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) |
11810 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) |
11934 %{ |
11811 %{ |
11935 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
11812 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none && |
|
11813 n->in(2)->as_Load()->barrier_data() == 0); |
11936 match(Set cr (CmpP op1 (LoadP op2))); |
11814 match(Set cr (CmpP op1 (LoadP op2))); |
11937 |
11815 |
11938 format %{ "cmpq $op1, $op2\t# raw ptr" %} |
11816 format %{ "cmpq $op1, $op2\t# raw ptr" %} |
11939 opcode(0x3B); /* Opcode 3B /r */ |
11817 opcode(0x3B); /* Opcode 3B /r */ |
11940 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11818 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); |
11955 |
11833 |
11956 // This will generate a signed flags result. This should be OK since |
11834 // This will generate a signed flags result. This should be OK since |
11957 // any compare to a zero should be eq/neq. |
11835 // any compare to a zero should be eq/neq. |
11958 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
11836 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
11959 %{ |
11837 %{ |
11960 predicate(!UseCompressedOops || (CompressedOops::base() != NULL)); |
11838 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) && |
|
11839 n->in(1)->as_Load()->barrier_data() == 0); |
11961 match(Set cr (CmpP (LoadP op) zero)); |
11840 match(Set cr (CmpP (LoadP op) zero)); |
11962 |
11841 |
11963 ins_cost(500); // XXX |
11842 ins_cost(500); // XXX |
11964 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} |
11843 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} |
11965 opcode(0xF7); /* Opcode F7 /0 */ |
11844 opcode(0xF7); /* Opcode F7 /0 */ |
11968 ins_pipe(ialu_cr_reg_imm); |
11847 ins_pipe(ialu_cr_reg_imm); |
11969 %} |
11848 %} |
11970 |
11849 |
11971 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
11850 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
11972 %{ |
11851 %{ |
11973 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && (CompressedKlassPointers::base() == NULL)); |
11852 predicate(UseCompressedOops && (CompressedOops::base() == NULL) && |
|
11853 (CompressedKlassPointers::base() == NULL) && |
|
11854 n->in(1)->as_Load()->barrier_data() == 0); |
11974 match(Set cr (CmpP (LoadP mem) zero)); |
11855 match(Set cr (CmpP (LoadP mem) zero)); |
11975 |
11856 |
11976 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
11857 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
11977 ins_encode %{ |
11858 ins_encode %{ |
11978 __ cmpq(r12, $mem$$Address); |
11859 __ cmpq(r12, $mem$$Address); |