jdk-sandbox: comparison src/hotspot/cpu/x86/x86.ad

equal deleted inserted replaced

-:13588c901957
+:9cf78a70fa4f
 );
 reg_class_dynamic vectorz_reg(vectorz_reg_evex, vectorz_reg_legacy, %{ VM_Version::supports_evex() %} );
 reg_class_dynamic vectorz_reg_vl(vectorz_reg_evex, vectorz_reg_legacy, %{ VM_Version::supports_evex() && VM_Version::supports_avx512vl() %} );
-reg_class xmm0_reg(XMM0, XMM0b, XMM0c, XMM0d);
-reg_class ymm0_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h);
-reg_class zmm0_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, XMM0i, XMM0j, XMM0k, XMM0l, XMM0m, XMM0n, XMM0o, XMM0p);
-reg_class xmm1_reg(XMM1, XMM1b, XMM1c, XMM1d);
-reg_class ymm1_reg(XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h);
-reg_class zmm1_reg(XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, XMM1i, XMM1j, XMM1k, XMM1l, XMM1m, XMM1n, XMM1o, XMM1p);
-reg_class xmm2_reg(XMM2, XMM2b, XMM2c, XMM2d);
-reg_class ymm2_reg(XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h);
-reg_class zmm2_reg(XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, XMM2i, XMM2j, XMM2k, XMM2l, XMM2m, XMM2n, XMM2o, XMM2p);
-reg_class xmm3_reg(XMM3, XMM3b, XMM3c, XMM3d);
-reg_class ymm3_reg(XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h);
-reg_class zmm3_reg(XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, XMM3i, XMM3j, XMM3k, XMM3l, XMM3m, XMM3n, XMM3o, XMM3p);
-reg_class xmm4_reg(XMM4, XMM4b, XMM4c, XMM4d);
-reg_class ymm4_reg(XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h);
-reg_class zmm4_reg(XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, XMM4i, XMM4j, XMM4k, XMM4l, XMM4m, XMM4n, XMM4o, XMM4p);
-reg_class xmm5_reg(XMM5, XMM5b, XMM5c, XMM5d);
-reg_class ymm5_reg(XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h);
-reg_class zmm5_reg(XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, XMM5i, XMM5j, XMM5k, XMM5l, XMM5m, XMM5n, XMM5o, XMM5p);
-reg_class xmm6_reg(XMM6, XMM6b, XMM6c, XMM6d);
-reg_class ymm6_reg(XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h);
-reg_class zmm6_reg(XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, XMM6i, XMM6j, XMM6k, XMM6l, XMM6m, XMM6n, XMM6o, XMM6p);
-reg_class xmm7_reg(XMM7, XMM7b, XMM7c, XMM7d);
-reg_class ymm7_reg(XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h);
-reg_class zmm7_reg(XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h, XMM7i, XMM7j, XMM7k, XMM7l, XMM7m, XMM7n, XMM7o, XMM7p);
-#ifdef _LP64
-reg_class xmm8_reg(XMM8, XMM8b, XMM8c, XMM8d);
-reg_class ymm8_reg(XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h);
-reg_class zmm8_reg(XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, XMM8i, XMM8j, XMM8k, XMM8l, XMM8m, XMM8n, XMM8o, XMM8p);
-reg_class xmm9_reg(XMM9, XMM9b, XMM9c, XMM9d);
-reg_class ymm9_reg(XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h);
-reg_class zmm9_reg(XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, XMM9i, XMM9j, XMM9k, XMM9l, XMM9m, XMM9n, XMM9o, XMM9p);
-reg_class xmm10_reg(XMM10, XMM10b, XMM10c, XMM10d);
-reg_class ymm10_reg(XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h);
-reg_class zmm10_reg(XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, XMM10i, XMM10j, XMM10k, XMM10l, XMM10m, XMM10n, XMM10o, XMM10p);
-reg_class xmm11_reg(XMM11, XMM11b, XMM11c, XMM11d);
-reg_class ymm11_reg(XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h);
-reg_class zmm11_reg(XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, XMM11i, XMM11j, XMM11k, XMM11l, XMM11m, XMM11n, XMM11o, XMM11p);
-reg_class xmm12_reg(XMM12, XMM12b, XMM12c, XMM12d);
-reg_class ymm12_reg(XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h);
-reg_class zmm12_reg(XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, XMM12i, XMM12j, XMM12k, XMM12l, XMM12m, XMM12n, XMM12o, XMM12p);
-reg_class xmm13_reg(XMM13, XMM13b, XMM13c, XMM13d);
-reg_class ymm13_reg(XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h);
-reg_class zmm13_reg(XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, XMM13i, XMM13j, XMM13k, XMM13l, XMM13m, XMM13n, XMM13o, XMM13p);
-reg_class xmm14_reg(XMM14, XMM14b, XMM14c, XMM14d);
-reg_class ymm14_reg(XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h);
-reg_class zmm14_reg(XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, XMM14i, XMM14j, XMM14k, XMM14l, XMM14m, XMM14n, XMM14o, XMM14p);
-reg_class xmm15_reg(XMM15, XMM15b, XMM15c, XMM15d);
-reg_class ymm15_reg(XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h);
-reg_class zmm15_reg(XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h, XMM15i, XMM15j, XMM15k, XMM15l, XMM15m, XMM15n, XMM15o, XMM15p);
-reg_class xmm16_reg(XMM16, XMM16b, XMM16c, XMM16d);
-reg_class ymm16_reg(XMM16, XMM16b, XMM16c, XMM16d, XMM16e, XMM16f, XMM16g, XMM16h);
-reg_class zmm16_reg(XMM16, XMM16b, XMM16c, XMM16d, XMM16e, XMM16f, XMM16g, XMM16h, XMM16i, XMM16j, XMM16k, XMM16l, XMM16m, XMM16n, XMM16o, XMM16p);
-reg_class xmm17_reg(XMM17, XMM17b, XMM17c, XMM17d);
-reg_class ymm17_reg(XMM17, XMM17b, XMM17c, XMM17d, XMM17e, XMM17f, XMM17g, XMM17h);
-reg_class zmm17_reg(XMM17, XMM17b, XMM17c, XMM17d, XMM17e, XMM17f, XMM17g, XMM17h, XMM17i, XMM17j, XMM17k, XMM17l, XMM17m, XMM17n, XMM17o, XMM17p);
-reg_class xmm18_reg(XMM18, XMM18b, XMM18c, XMM18d);
-reg_class ymm18_reg(XMM18, XMM18b, XMM18c, XMM18d, XMM18e, XMM18f, XMM18g, XMM18h);
-reg_class zmm18_reg(XMM18, XMM18b, XMM18c, XMM18d, XMM18e, XMM18f, XMM18g, XMM18h, XMM18i, XMM18j, XMM18k, XMM18l, XMM18m, XMM18n, XMM18o, XMM18p);
-reg_class xmm19_reg(XMM19, XMM19b, XMM19c, XMM19d);
-reg_class ymm19_reg(XMM19, XMM19b, XMM19c, XMM19d, XMM19e, XMM19f, XMM19g, XMM19h);
-reg_class zmm19_reg(XMM19, XMM19b, XMM19c, XMM19d, XMM19e, XMM19f, XMM19g, XMM19h, XMM19i, XMM19j, XMM19k, XMM19l, XMM19m, XMM19n, XMM19o, XMM19p);
-reg_class xmm20_reg(XMM20, XMM20b, XMM20c, XMM20d);
-reg_class ymm20_reg(XMM20, XMM20b, XMM20c, XMM20d, XMM20e, XMM20f, XMM20g, XMM20h);
-reg_class zmm20_reg(XMM20, XMM20b, XMM20c, XMM20d, XMM20e, XMM20f, XMM20g, XMM20h, XMM20i, XMM20j, XMM20k, XMM20l, XMM20m, XMM20n, XMM20o, XMM20p);
-reg_class xmm21_reg(XMM21, XMM21b, XMM21c, XMM21d);
-reg_class ymm21_reg(XMM21, XMM21b, XMM21c, XMM21d, XMM21e, XMM21f, XMM21g, XMM21h);
-reg_class zmm21_reg(XMM21, XMM21b, XMM21c, XMM21d, XMM21e, XMM21f, XMM21g, XMM21h, XMM21i, XMM21j, XMM21k, XMM21l, XMM21m, XMM21n, XMM21o, XMM21p);
-reg_class xmm22_reg(XMM22, XMM22b, XMM22c, XMM22d);
-reg_class ymm22_reg(XMM22, XMM22b, XMM22c, XMM22d, XMM22e, XMM22f, XMM22g, XMM22h);
-reg_class zmm22_reg(XMM22, XMM22b, XMM22c, XMM22d, XMM22e, XMM22f, XMM22g, XMM22h, XMM22i, XMM22j, XMM22k, XMM22l, XMM22m, XMM22n, XMM22o, XMM22p);
-reg_class xmm23_reg(XMM23, XMM23b, XMM23c, XMM23d);
-reg_class ymm23_reg(XMM23, XMM23b, XMM23c, XMM23d, XMM23e, XMM23f, XMM23g, XMM23h);
-reg_class zmm23_reg(XMM23, XMM23b, XMM23c, XMM23d, XMM23e, XMM23f, XMM23g, XMM23h, XMM23i, XMM23j, XMM23k, XMM23l, XMM23m, XMM23n, XMM23o, XMM23p);
-reg_class xmm24_reg(XMM24, XMM24b, XMM24c, XMM24d);
-reg_class ymm24_reg(XMM24, XMM24b, XMM24c, XMM24d, XMM24e, XMM24f, XMM24g, XMM24h);
-reg_class zmm24_reg(XMM24, XMM24b, XMM24c, XMM24d, XMM24e, XMM24f, XMM24g, XMM24h, XMM24i, XMM24j, XMM24k, XMM24l, XMM24m, XMM24n, XMM24o, XMM24p);
-reg_class xmm25_reg(XMM25, XMM25b, XMM25c, XMM25d);
-reg_class ymm25_reg(XMM25, XMM25b, XMM25c, XMM25d, XMM25e, XMM25f, XMM25g, XMM25h);
-reg_class zmm25_reg(XMM25, XMM25b, XMM25c, XMM25d, XMM25e, XMM25f, XMM25g, XMM25h, XMM25i, XMM25j, XMM25k, XMM25l, XMM25m, XMM25n, XMM25o, XMM25p);
-reg_class xmm26_reg(XMM26, XMM26b, XMM26c, XMM26d);
-reg_class ymm26_reg(XMM26, XMM26b, XMM26c, XMM26d, XMM26e, XMM26f, XMM26g, XMM26h);
-reg_class zmm26_reg(XMM26, XMM26b, XMM26c, XMM26d, XMM26e, XMM26f, XMM26g, XMM26h, XMM26i, XMM26j, XMM26k, XMM26l, XMM26m, XMM26n, XMM26o, XMM26p);
-reg_class xmm27_reg(XMM27, XMM27b, XMM27c, XMM27d);
-reg_class ymm27_reg(XMM27, XMM27b, XMM27c, XMM27d, XMM27e, XMM27f, XMM27g, XMM27h);
-reg_class zmm27_reg(XMM27, XMM27b, XMM27c, XMM27d, XMM27e, XMM27f, XMM27g, XMM27h, XMM27i, XMM27j, XMM27k, XMM27l, XMM27m, XMM27n, XMM27o, XMM27p);
-reg_class xmm28_reg(XMM28, XMM28b, XMM28c, XMM28d);
-reg_class ymm28_reg(XMM28, XMM28b, XMM28c, XMM28d, XMM28e, XMM28f, XMM28g, XMM28h);
-reg_class zmm28_reg(XMM28, XMM28b, XMM28c, XMM28d, XMM28e, XMM28f, XMM28g, XMM28h, XMM28i, XMM28j, XMM28k, XMM28l, XMM28m, XMM28n, XMM28o, XMM28p);
-reg_class xmm29_reg(XMM29, XMM29b, XMM29c, XMM29d);
-reg_class ymm29_reg(XMM29, XMM29b, XMM29c, XMM29d, XMM29e, XMM29f, XMM29g, XMM29h);
-reg_class zmm29_reg(XMM29, XMM29b, XMM29c, XMM29d, XMM29e, XMM29f, XMM29g, XMM29h, XMM29i, XMM29j, XMM29k, XMM29l, XMM29m, XMM29n, XMM29o, XMM29p);
-reg_class xmm30_reg(XMM30, XMM30b, XMM30c, XMM30d);
-reg_class ymm30_reg(XMM30, XMM30b, XMM30c, XMM30d, XMM30e, XMM30f, XMM30g, XMM30h);
-reg_class zmm30_reg(XMM30, XMM30b, XMM30c, XMM30d, XMM30e, XMM30f, XMM30g, XMM30h, XMM30i, XMM30j, XMM30k, XMM30l, XMM30m, XMM30n, XMM30o, XMM30p);
-reg_class xmm31_reg(XMM31, XMM31b, XMM31c, XMM31d);
-reg_class ymm31_reg(XMM31, XMM31b, XMM31c, XMM31d, XMM31e, XMM31f, XMM31g, XMM31h);
-reg_class zmm31_reg(XMM31, XMM31b, XMM31c, XMM31d, XMM31e, XMM31f, XMM31g, XMM31h, XMM31i, XMM31j, XMM31k, XMM31l, XMM31m, XMM31n, XMM31o, XMM31p);
-#endif
 %}
 //----------SOURCE BLOCK-------------------------------------------------------
 // This is a block of C++ code which provides values, functions, and
 break;
 case Op_AbsVB:
 case Op_AbsVS:
 case Op_AbsVI:
 case Op_AddReductionVI:
-if (UseSSE < 3) // requires at least SSE3
+if (UseSSE < 3 || !VM_Version::supports_ssse3()) // requires at least SSSE3
 ret_value = false;
 break;
 case Op_MulReductionVI:
 if (UseSSE < 4) // requires at least SSE4
 ret_value = false;
 case Op_MinF:
 if (UseAVX < 1) // enabled for AVX only
 ret_value = false;
 break;
 #endif
+case Op_CacheWB:
+case Op_CacheWBPreSync:
+case Op_CacheWBPostSync:
+if (!VM_Version::supports_data_cache_line_flush()) {
+ret_value = false;
+}
+break;
+case Op_RoundDoubleMode:
+if (UseSSE < 4)
+ret_value = false;
+break;
 }
 return ret_value;  // Per default match rules are supported.
 }
 ret_value = false;
 break;
 case Op_CMoveVD:
 if (vlen != 4)
 ret_value  = false;
+break;
+case Op_RoundDoubleModeV:
+if (VM_Version::supports_avx() == false)
+ret_value = false;
 break;
 }
 }
 return ret_value;  // Per default match rules are supported.
 }
 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
 return (UseAVX > 2) ? 6 : 4;
 }
-static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
+int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
 int stack_offset, int reg, uint ireg, outputStream* st) {
 // In 64-bit VM size calculation is very complex. Emitting instructions
 // into scratch buffer is used to get size in 64-bit VM.
 LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); )
 if (cbuf) {
 MacroAssembler _masm(cbuf);
 instruct ShouldNotReachHere() %{
 match(Halt);
 format %{ "ud2\t# ShouldNotReachHere" %}
 ins_encode %{
-__ ud2();
+__ stop(_halt_reason);
 %}
 ins_pipe(pipe_slow);
 %}
 // =================================EVEX special===============================
 ins_encode %{
 __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
 %}
 ins_pipe(pipe_slow);
 %}
+#ifdef _LP64
+instruct roundD_reg(legRegD dst, legRegD src, immU8 rmode) %{
+predicate(UseSSE>=4);
+match(Set dst (RoundDoubleMode src rmode));
+format %{ "roundsd  $dst, $src" %}
+ins_cost(150);
+ins_encode %{
+__ roundsd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant);
+%}
+ins_pipe(pipe_slow);
+%}
+instruct roundD_mem(legRegD dst, memory src, immU8 rmode) %{
+predicate(UseSSE>=4);
+match(Set dst (RoundDoubleMode (LoadD src) rmode));
+format %{ "roundsd  $dst, $src" %}
+ins_cost(150);
+ins_encode %{
+__ roundsd($dst$$XMMRegister, $src$$Address, $rmode$$constant);
+%}
+ins_pipe(pipe_slow);
+%}
+instruct roundD_imm(legRegD dst, immD con, immU8 rmode, rRegI scratch_reg) %{
+predicate(UseSSE>=4);
+match(Set dst (RoundDoubleMode con rmode));
+effect(TEMP scratch_reg);
+format %{ "roundsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
+ins_cost(150);
+ins_encode %{
+__ roundsd($dst$$XMMRegister, $constantaddress($con), $rmode$$constant, $scratch_reg$$Register);
+%}
+ins_pipe(pipe_slow);
+%}
+instruct vround2D_reg(legVecX dst, legVecX src, immU8 rmode) %{
+predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+match(Set dst (RoundDoubleModeV src rmode));
+format %{ "vroundpd  $dst, $src, $rmode\t! round packed2D" %}
+ins_encode %{
+int vector_len = 0;
+__ vroundpd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len);
+%}
+ins_pipe( pipe_slow );
+%}
+instruct vround2D_mem(legVecX dst, memory mem, immU8 rmode) %{
+predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+match(Set dst (RoundDoubleModeV (LoadVector mem) rmode));
+format %{ "vroundpd $dst, $mem, $rmode\t! round packed2D" %}
+ins_encode %{
+int vector_len = 0;
+__ vroundpd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len);
+%}
+ins_pipe( pipe_slow );
+%}
+instruct vround4D_reg(legVecY dst, legVecY src, legVecY rmode) %{
+predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+match(Set dst (RoundDoubleModeV src rmode));
+format %{ "vroundpd  $dst, $src, $rmode\t! round packed4D" %}
+ins_encode %{
+int vector_len = 1;
+__ vroundpd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len);
+%}
+ins_pipe( pipe_slow );
+%}
+instruct vround4D_mem(legVecY dst, memory mem, immU8 rmode) %{
+predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+match(Set dst (RoundDoubleModeV (LoadVector mem) rmode));
+format %{ "vroundpd $dst, $mem, $rmode\t! round packed4D" %}
+ins_encode %{
+int vector_len = 1;
+__ vroundpd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len);
+%}
+ins_pipe( pipe_slow );
+%}
+instruct vround8D_reg(vecZ dst, vecZ src, immU8 rmode) %{
+predicate(UseAVX > 2 && n->as_Vector()->length() == 8);
+match(Set dst (RoundDoubleModeV src rmode));
+format %{ "vrndscalepd $dst, $src, $rmode\t! round packed8D" %}
+ins_encode %{
+int vector_len = 2;
+__ vrndscalepd($dst$$XMMRegister, $src$$XMMRegister, $rmode$$constant, vector_len);
+%}
+ins_pipe( pipe_slow );
+%}
+instruct vround8D_mem(vecZ dst, memory mem, immU8 rmode) %{
+predicate(UseAVX > 2 && n->as_Vector()->length() == 8);
+match(Set dst (RoundDoubleModeV (LoadVector mem) rmode));
+format %{ "vrndscalepd $dst, $mem, $rmode\t! round packed8D" %}
+ins_encode %{
+int vector_len = 2;
+__ vrndscalepd($dst$$XMMRegister, $mem$$Address, $rmode$$constant, vector_len);
+%}
+ins_pipe( pipe_slow );
+%}
+#endif // _LP64
 instruct onspinwait() %{
 match(OnSpinWait);
 ins_cost(200);
 %}
 ins_pipe( pipe_slow );
 %}
 instruct Repl2F_zero(vecD dst, immF0 zero) %{
-predicate(n->as_Vector()->length() == 2 && UseAVX < 3);
+predicate(n->as_Vector()->length() == 2);
 match(Set dst (ReplicateF zero));
 format %{ "xorps   $dst,$dst\t! replicate2F zero" %}
 ins_encode %{
 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
 %}
 ins_pipe( fpu_reg_reg );
 %}
 instruct Repl4F_zero(vecX dst, immF0 zero) %{
-predicate(n->as_Vector()->length() == 4 && UseAVX < 3);
+predicate(n->as_Vector()->length() == 4);
 match(Set dst (ReplicateF zero));
 format %{ "xorps   $dst,$dst\t! replicate4F zero" %}
 ins_encode %{
 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
 %}
 ins_pipe( fpu_reg_reg );
 %}
 instruct Repl8F_zero(vecY dst, immF0 zero) %{
-predicate(n->as_Vector()->length() == 8 && UseAVX < 3);
+predicate(n->as_Vector()->length() == 8 && UseAVX > 0);
 match(Set dst (ReplicateF zero));
 format %{ "vxorps  $dst,$dst,$dst\t! replicate8F zero" %}
 ins_encode %{
 int vector_len = 1;
 __ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len);
 ins_pipe( pipe_slow );
 %}
 // Replicate double (8 byte) scalar zero to be vector
 instruct Repl2D_zero(vecX dst, immD0 zero) %{
-predicate(n->as_Vector()->length() == 2 && UseAVX < 3);
+predicate(n->as_Vector()->length() == 2);
 match(Set dst (ReplicateD zero));
 format %{ "xorpd   $dst,$dst\t! replicate2D zero" %}
 ins_encode %{
 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
 %}
 ins_pipe( fpu_reg_reg );
 %}
 instruct Repl4D_zero(vecY dst, immD0 zero) %{
-predicate(n->as_Vector()->length() == 4 && UseAVX < 3);
+predicate(n->as_Vector()->length() == 4 && UseAVX > 0);
 match(Set dst (ReplicateD zero));
 format %{ "vxorpd  $dst,$dst,$dst,vect256\t! replicate4D zero" %}
 ins_encode %{
 int vector_len = 1;
 __ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len);
 __ vpbroadcastss($dst$$XMMRegister, $mem$$Address, vector_len);
 %}
 ins_pipe( pipe_slow );
 %}
-instruct Repl2F_zero_evex(vecD dst, immF0 zero) %{
-predicate(n->as_Vector()->length() == 2 && UseAVX > 2);
-match(Set dst (ReplicateF zero));
-format %{ "vpxor  $dst k0,$dst,$dst\t! replicate2F zero" %}
-ins_encode %{
-// Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
-int vector_len = 2;
-__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len);
-%}
-ins_pipe( fpu_reg_reg );
-%}
-instruct Repl4F_zero_evex(vecX dst, immF0 zero) %{
-predicate(n->as_Vector()->length() == 4 && UseAVX > 2);
-match(Set dst (ReplicateF zero));
-format %{ "vpxor  $dst k0,$dst,$dst\t! replicate4F zero" %}
-ins_encode %{
-// Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
-int vector_len = 2;
-__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len);
-%}
-ins_pipe( fpu_reg_reg );
-%}
-instruct Repl8F_zero_evex(vecY dst, immF0 zero) %{
-predicate(n->as_Vector()->length() == 8 && UseAVX > 2);
-match(Set dst (ReplicateF zero));
-format %{ "vpxor  $dst k0,$dst,$dst\t! replicate8F zero" %}
-ins_encode %{
-// Use vpxor in place of vxorps since EVEX has a constriant on dq for vxorps: this is a 512-bit operation
-int vector_len = 2;
-__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len);
-%}
-ins_pipe( fpu_reg_reg );
-%}
 instruct Repl16F_zero_evex(vecZ dst, immF0 zero) %{
 predicate(n->as_Vector()->length() == 16 && UseAVX > 2);
 match(Set dst (ReplicateF zero));
 format %{ "vpxor  $dst k0,$dst,$dst\t! replicate16F zero" %}
 ins_encode %{
 ins_encode %{
 int vector_len = 2;
 __ vpbroadcastsd($dst$$XMMRegister, $mem$$Address, vector_len);
 %}
 ins_pipe( pipe_slow );
-%}
-instruct Repl2D_zero_evex(vecX dst, immD0 zero) %{
-predicate(n->as_Vector()->length() == 2 && UseAVX > 2);
-match(Set dst (ReplicateD zero));
-format %{ "vpxor  $dst k0,$dst,$dst\t! replicate2D zero" %}
-ins_encode %{
-// Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation
-int vector_len = 2;
-__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len);
-%}
-ins_pipe( fpu_reg_reg );
-%}
-instruct Repl4D_zero_evex(vecY dst, immD0 zero) %{
-predicate(n->as_Vector()->length() == 4 && UseAVX > 2);
-match(Set dst (ReplicateD zero));
-format %{ "vpxor  $dst k0,$dst,$dst\t! replicate4D zero" %}
-ins_encode %{
-// Use vpxor in place of vxorpd since EVEX has a constriant on dq for vxorpd: this is a 512-bit operation
-int vector_len = 2;
-__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len);
-%}
-ins_pipe( fpu_reg_reg );
 %}
 instruct Repl8D_zero_evex(vecZ dst, immD0 zero) %{
 predicate(n->as_Vector()->length() == 8 && UseAVX > 2);
 match(Set dst (ReplicateD zero));
 instruct vshift4B(vecS dst, vecS src, vecS shift, vecS tmp, rRegI scratch) %{
 predicate(UseSSE > 3 && n->as_Vector()->length() == 4);
 match(Set dst (LShiftVB src shift));
 match(Set dst (RShiftVB src shift));
 match(Set dst (URShiftVB src shift));
-effect(TEMP dst, TEMP tmp, TEMP scratch);
+effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch);
 format %{"vextendbw $tmp,$src\n\t"
 "vshiftw   $tmp,$shift\n\t"
 "movdqu    $dst,[0x00ff00ff0x00ff00ff]\n\t"
 "pand      $dst,$tmp\n\t"
 "packuswb  $dst,$dst\n\t ! packed4B shift" %}
 instruct vshift8B(vecD dst, vecD src, vecS shift, vecD tmp, rRegI scratch) %{
 predicate(UseSSE > 3 && n->as_Vector()->length() == 8);
 match(Set dst (LShiftVB src shift));
 match(Set dst (RShiftVB src shift));
 match(Set dst (URShiftVB src shift));
-effect(TEMP dst, TEMP tmp, TEMP scratch);
+effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch);
 format %{"vextendbw $tmp,$src\n\t"
 "vshiftw   $tmp,$shift\n\t"
 "movdqu    $dst,[0x00ff00ff0x00ff00ff]\n\t"
 "pand      $dst,$tmp\n\t"
 "packuswb  $dst,$dst\n\t ! packed8B shift" %}
 instruct vshift16B(vecX dst, vecX src, vecS shift, vecX tmp1, vecX tmp2, rRegI scratch) %{
 predicate(UseSSE > 3  && UseAVX <= 1 && n->as_Vector()->length() == 16);
 match(Set dst (LShiftVB src shift));
 match(Set dst (RShiftVB src shift));
 match(Set dst (URShiftVB src shift));
-effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch);
+effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch);
 format %{"vextendbw $tmp1,$src\n\t"
 "vshiftw   $tmp1,$shift\n\t"
 "pshufd    $tmp2,$src\n\t"
 "vextendbw $tmp2,$tmp2\n\t"
 "vshiftw   $tmp2,$shift\n\t"
 instruct vshift16B_avx(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{
 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
 match(Set dst (LShiftVB src shift));
 match(Set dst (RShiftVB src shift));
 match(Set dst (URShiftVB src shift));
-effect(TEMP dst, TEMP tmp, TEMP scratch);
+effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch);
 format %{"vextendbw  $tmp,$src\n\t"
 "vshiftw    $tmp,$tmp,$shift\n\t"
 "vpand      $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t"
 "vextracti128_high  $dst,$tmp\n\t"
 "vpackuswb  $dst,$tmp,$dst\n\t! packed16B shift" %}
 instruct vshift32B_avx(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{
 predicate(UseAVX > 1 && n->as_Vector()->length() == 32);
 match(Set dst (LShiftVB src shift));
 match(Set dst (RShiftVB src shift));
 match(Set dst (URShiftVB src shift));
-effect(TEMP dst, TEMP tmp, TEMP scratch);
+effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch);
 format %{"vextracti128_high  $tmp,$src\n\t"
 "vextendbw  $tmp,$tmp\n\t"
 "vextendbw  $dst,$src\n\t"
 "vshiftw    $tmp,$tmp,$shift\n\t"
 "vshiftw    $dst,$dst,$shift\n\t"
 instruct vshift64B_avx(vecZ dst, vecZ src, vecS shift, vecZ tmp1, vecZ tmp2, rRegI scratch) %{
 predicate(UseAVX > 2 && n->as_Vector()->length() == 64);
 match(Set dst (LShiftVB src shift));
 match(Set dst (RShiftVB src shift));
 match(Set dst (URShiftVB src shift));
-effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch);
+effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch);
 format %{"vextracti64x4  $tmp1,$src\n\t"
 "vextendbw      $tmp1,$tmp1\n\t"
 "vextendbw      $tmp2,$src\n\t"
 "vshiftw        $tmp1,$tmp1,$shift\n\t"
 "vshiftw        $tmp2,$tmp2,$shift\n\t"
 instruct vshist2S(vecS dst, vecS src, vecS shift) %{
 predicate(n->as_Vector()->length() == 2);
 match(Set dst (LShiftVS src shift));
 match(Set dst (RShiftVS src shift));
 match(Set dst (URShiftVS src shift));
+effect(TEMP dst, USE src, USE shift);
 format %{ "vshiftw  $dst,$src,$shift\t! shift packed2S" %}
 ins_encode %{
 int opcode = this->as_Mach()->ideal_Opcode();
 if (UseAVX == 0) {
 if ($dst$$XMMRegister != $src$$XMMRegister)
 instruct vshift4S(vecD dst, vecD src, vecS shift) %{
 predicate(n->as_Vector()->length() == 4);
 match(Set dst (LShiftVS src shift));
 match(Set dst (RShiftVS src shift));
 match(Set dst (URShiftVS src shift));
+effect(TEMP dst, USE src, USE shift);
 format %{ "vshiftw  $dst,$src,$shift\t! shift packed4S" %}
 ins_encode %{
 int opcode = this->as_Mach()->ideal_Opcode();
 if (UseAVX == 0) {
 if ($dst$$XMMRegister != $src$$XMMRegister)
 instruct vshift8S(vecX dst, vecX src, vecS shift) %{
 predicate(n->as_Vector()->length() == 8);
 match(Set dst (LShiftVS src shift));
 match(Set dst (RShiftVS src shift));
 match(Set dst (URShiftVS src shift));
+effect(TEMP dst, USE src, USE shift);
 format %{ "vshiftw  $dst,$src,$shift\t! shift packed8S" %}
 ins_encode %{
 int opcode = this->as_Mach()->ideal_Opcode();
 if (UseAVX == 0) {
 if ($dst$$XMMRegister != $src$$XMMRegister)
 instruct vshift16S(vecY dst, vecY src, vecS shift) %{
 predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
 match(Set dst (LShiftVS src shift));
 match(Set dst (RShiftVS src shift));
 match(Set dst (URShiftVS src shift));
+effect(DEF dst, USE src, USE shift);
 format %{ "vshiftw  $dst,$src,$shift\t! shift packed16S" %}
 ins_encode %{
 int vector_len = 1;
 int opcode = this->as_Mach()->ideal_Opcode();
 __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
 instruct vshift32S(vecZ dst, vecZ src, vecS shift) %{
 predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32);
 match(Set dst (LShiftVS src shift));
 match(Set dst (RShiftVS src shift));
 match(Set dst (URShiftVS src shift));
+effect(DEF dst, USE src, USE shift);
 format %{ "vshiftw  $dst,$src,$shift\t! shift packed32S" %}
 ins_encode %{
 int vector_len = 2;
 int opcode = this->as_Mach()->ideal_Opcode();
 __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
 instruct vshift2I(vecD dst, vecD src, vecS shift) %{
 predicate(n->as_Vector()->length() == 2);
 match(Set dst (LShiftVI src shift));
 match(Set dst (RShiftVI src shift));
 match(Set dst (URShiftVI src shift));
+effect(TEMP dst, USE src, USE shift);
 format %{ "vshiftd  $dst,$src,$shift\t! shift packed2I" %}
 ins_encode %{
 int opcode = this->as_Mach()->ideal_Opcode();
 if (UseAVX == 0) {
 if ($dst$$XMMRegister != $src$$XMMRegister)
 instruct vshift4I(vecX dst, vecX src, vecS shift) %{
 predicate(n->as_Vector()->length() == 4);
 match(Set dst (LShiftVI src shift));
 match(Set dst (RShiftVI src shift));
 match(Set dst (URShiftVI src shift));
+effect(TEMP dst, USE src, USE shift);
 format %{ "vshiftd  $dst,$src,$shift\t! shift packed4I" %}
 ins_encode %{
 int opcode = this->as_Mach()->ideal_Opcode();
 if (UseAVX == 0) {
 if ($dst$$XMMRegister != $src$$XMMRegister)
 instruct vshift8I(vecY dst, vecY src, vecS shift) %{
 predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
 match(Set dst (LShiftVI src shift));
 match(Set dst (RShiftVI src shift));
 match(Set dst (URShiftVI src shift));
+effect(DEF dst, USE src, USE shift);
 format %{ "vshiftd  $dst,$src,$shift\t! shift packed8I" %}
 ins_encode %{
 int vector_len = 1;
 int opcode = this->as_Mach()->ideal_Opcode();
 __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
 instruct vshift16I(vecZ dst, vecZ src, vecS shift) %{
 predicate(UseAVX > 2 && n->as_Vector()->length() == 16);
 match(Set dst (LShiftVI src shift));
 match(Set dst (RShiftVI src shift));
 match(Set dst (URShiftVI src shift));
+effect(DEF dst, USE src, USE shift);
 format %{ "vshiftd  $dst,$src,$shift\t! shift packed16I" %}
 ins_encode %{
 int vector_len = 2;
 int opcode = this->as_Mach()->ideal_Opcode();
 __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
 // Longs vector shift
 instruct vshift2L(vecX dst, vecX src, vecS shift) %{
 predicate(n->as_Vector()->length() == 2);
 match(Set dst (LShiftVL src shift));
 match(Set dst (URShiftVL src shift));
+effect(TEMP dst, USE src, USE shift);
 format %{ "vshiftq  $dst,$src,$shift\t! shift packed2L" %}
 ins_encode %{
 int opcode = this->as_Mach()->ideal_Opcode();
 if (UseAVX == 0) {
 if ($dst$$XMMRegister != $src$$XMMRegister)
 instruct vshift4L(vecY dst, vecY src, vecS shift) %{
 predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
 match(Set dst (LShiftVL src shift));
 match(Set dst (URShiftVL src shift));
+effect(DEF dst, USE src, USE shift);
 format %{ "vshiftq  $dst,$src,$shift\t! left shift packed4L" %}
 ins_encode %{
 int vector_len = 1;
 int opcode = this->as_Mach()->ideal_Opcode();
 __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
 instruct vshift8L(vecZ dst, vecZ src, vecS shift) %{
 predicate(UseAVX > 2 && n->as_Vector()->length() == 8);
 match(Set dst (LShiftVL src shift));
 match(Set dst (RShiftVL src shift));
 match(Set dst (URShiftVL src shift));
+effect(DEF dst, USE src, USE shift);
 format %{ "vshiftq  $dst,$src,$shift\t! shift packed8L" %}
 ins_encode %{
 int vector_len = 2;
 int opcode = this->as_Mach()->ideal_Opcode();
 __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);

branch	datagramsocketimpl-branch
changeset 58678	9cf78a70fa4f
parent 55061	d1fa0f8d8c9a
child 58679	9c3209ff7550