1376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1378 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1377 emit_int8((unsigned char)0xDC); |
1379 emit_int8((unsigned char)0xDC); |
1378 emit_int8(0xC0 | encode); |
1380 emit_int8(0xC0 | encode); |
1379 } |
1381 } |
1380 |
1382 |
|
1383 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { |
|
1384 assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); |
|
1385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
|
1386 attributes.set_is_evex_instruction(); |
|
1387 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
|
1388 emit_int8((unsigned char)0xDC); |
|
1389 emit_int8((unsigned char)(0xC0 | encode)); |
|
1390 } |
|
1391 |
1381 void Assembler::aesenclast(XMMRegister dst, Address src) { |
1392 void Assembler::aesenclast(XMMRegister dst, Address src) { |
1382 assert(VM_Version::supports_aes(), ""); |
1393 assert(VM_Version::supports_aes(), ""); |
1383 InstructionMark im(this); |
1394 InstructionMark im(this); |
1384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1385 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1396 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1389 |
1400 |
1390 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { |
1401 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { |
1391 assert(VM_Version::supports_aes(), ""); |
1402 assert(VM_Version::supports_aes(), ""); |
1392 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
1393 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1404 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
|
1405 emit_int8((unsigned char)0xDD); |
|
1406 emit_int8((unsigned char)(0xC0 | encode)); |
|
1407 } |
|
1408 |
|
1409 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { |
|
1410 assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); |
|
1411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
|
1412 attributes.set_is_evex_instruction(); |
|
1413 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); |
1394 emit_int8((unsigned char)0xDD); |
1414 emit_int8((unsigned char)0xDD); |
1395 emit_int8((unsigned char)(0xC0 | encode)); |
1415 emit_int8((unsigned char)(0xC0 | encode)); |
1396 } |
1416 } |
1397 |
1417 |
1398 void Assembler::andl(Address dst, int32_t imm32) { |
1418 void Assembler::andl(Address dst, int32_t imm32) { |
2250 void Assembler::mfence() { |
2270 void Assembler::mfence() { |
2251 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
2271 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
2252 emit_int8(0x0F); |
2272 emit_int8(0x0F); |
2253 emit_int8((unsigned char)0xAE); |
2273 emit_int8((unsigned char)0xAE); |
2254 emit_int8((unsigned char)0xF0); |
2274 emit_int8((unsigned char)0xF0); |
|
2275 } |
|
2276 |
|
2277 // Emit sfence instruction |
|
2278 void Assembler::sfence() { |
|
2279 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
|
2280 emit_int8(0x0F); |
|
2281 emit_int8((unsigned char)0xAE); |
|
2282 emit_int8((unsigned char)0xF8); |
2255 } |
2283 } |
2256 |
2284 |
2257 void Assembler::mov(Register dst, Register src) { |
2285 void Assembler::mov(Register dst, Register src) { |
2258 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
2286 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
2259 } |
2287 } |
4272 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); |
4300 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); |
4273 emit_int8(0x70); |
4301 emit_int8(0x70); |
4274 emit_operand(dst, src); |
4302 emit_operand(dst, src); |
4275 emit_int8(mode & 0xFF); |
4303 emit_int8(mode & 0xFF); |
4276 } |
4304 } |
|
4305 |
4277 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { |
4306 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { |
4278 assert(VM_Version::supports_evex(), "requires EVEX support"); |
4307 assert(VM_Version::supports_evex(), "requires EVEX support"); |
4279 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, ""); |
4308 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, ""); |
4280 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
4309 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
4281 attributes.set_is_evex_instruction(); |
4310 attributes.set_is_evex_instruction(); |
4709 } |
4738 } |
4710 |
4739 |
4711 // copies a single word from [esi] to [edi] |
4740 // copies a single word from [esi] to [edi] |
4712 void Assembler::smovl() { |
4741 void Assembler::smovl() { |
4713 emit_int8((unsigned char)0xA5); |
4742 emit_int8((unsigned char)0xA5); |
|
4743 } |
|
4744 |
|
4745 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { |
|
4746 assert(VM_Version::supports_sse4_1(), ""); |
|
4747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
|
4748 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); |
|
4749 emit_int8(0x0B); |
|
4750 emit_int8((unsigned char)(0xC0 | encode)); |
|
4751 emit_int8((unsigned char)rmode); |
|
4752 } |
|
4753 |
|
4754 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) { |
|
4755 assert(VM_Version::supports_sse4_1(), ""); |
|
4756 InstructionMark im(this); |
|
4757 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
|
4758 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); |
|
4759 emit_int8(0x0B); |
|
4760 emit_operand(dst, src); |
|
4761 emit_int8((unsigned char)rmode); |
4714 } |
4762 } |
4715 |
4763 |
4716 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
4764 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
4717 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4765 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4718 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); |
4766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); |
5507 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); |
5555 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); |
5508 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); |
5556 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); |
5509 emit_int8(0x5E); |
5557 emit_int8(0x5E); |
5510 emit_operand(dst, src); |
5558 emit_operand(dst, src); |
5511 } |
5559 } |
|
5560 |
|
5561 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { |
|
5562 assert(VM_Version::supports_avx(), ""); |
|
5563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
|
5564 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); |
|
5565 emit_int8(0x09); |
|
5566 emit_int8((unsigned char)(0xC0 | encode)); |
|
5567 emit_int8((unsigned char)(rmode)); |
|
5568 } |
|
5569 |
|
5570 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { |
|
5571 assert(VM_Version::supports_avx(), ""); |
|
5572 InstructionMark im(this); |
|
5573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); |
|
5574 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); |
|
5575 emit_int8(0x09); |
|
5576 emit_operand(dst, src); |
|
5577 emit_int8((unsigned char)(rmode)); |
|
5578 } |
|
5579 |
|
5580 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { |
|
5581 assert(VM_Version::supports_evex(), "requires EVEX support"); |
|
5582 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
|
5583 attributes.set_is_evex_instruction(); |
|
5584 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); |
|
5585 emit_int8((unsigned char)0x09); |
|
5586 emit_int8((unsigned char)(0xC0 | encode)); |
|
5587 emit_int8((unsigned char)(rmode)); |
|
5588 } |
|
5589 |
|
5590 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { |
|
5591 assert(VM_Version::supports_evex(), "requires EVEX support"); |
|
5592 assert(dst != xnoreg, "sanity"); |
|
5593 InstructionMark im(this); |
|
5594 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
|
5595 attributes.set_is_evex_instruction(); |
|
5596 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); |
|
5597 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); |
|
5598 emit_int8((unsigned char)0x09); |
|
5599 emit_operand(dst, src); |
|
5600 emit_int8((unsigned char)(rmode)); |
|
5601 } |
|
5602 |
5512 |
5603 |
5513 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { |
5604 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { |
5514 assert(VM_Version::supports_avx(), ""); |
5605 assert(VM_Version::supports_avx(), ""); |
5515 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
5606 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); |
5516 attributes.set_rex_vex_w_reverted(); |
5607 attributes.set_rex_vex_w_reverted(); |
8594 prefix(REX_W); |
8685 prefix(REX_W); |
8595 emit_int8((unsigned char)0x99); |
8686 emit_int8((unsigned char)0x99); |
8596 } |
8687 } |
8597 |
8688 |
8598 void Assembler::clflush(Address adr) { |
8689 void Assembler::clflush(Address adr) { |
|
8690 assert(VM_Version::supports_clflush(), "should do"); |
8599 prefix(adr); |
8691 prefix(adr); |
8600 emit_int8(0x0F); |
8692 emit_int8(0x0F); |
8601 emit_int8((unsigned char)0xAE); |
8693 emit_int8((unsigned char)0xAE); |
8602 emit_operand(rdi, adr); |
8694 emit_operand(rdi, adr); |
|
8695 } |
|
8696 |
|
8697 void Assembler::clflushopt(Address adr) { |
|
8698 assert(VM_Version::supports_clflushopt(), "should do!"); |
|
8699 // adr should be base reg only with no index or offset |
|
8700 assert(adr.index() == noreg, "index should be noreg"); |
|
8701 assert(adr.scale() == Address::no_scale, "scale should be no_scale"); |
|
8702 assert(adr.disp() == 0, "displacement should be 0"); |
|
8703 // instruction prefix is 0x66 |
|
8704 emit_int8(0x66); |
|
8705 prefix(adr); |
|
8706 // opcode family is 0x0f 0xAE |
|
8707 emit_int8(0x0F); |
|
8708 emit_int8((unsigned char)0xAE); |
|
8709 // extended opcode byte is 7 == rdi |
|
8710 emit_operand(rdi, adr); |
|
8711 } |
|
8712 |
|
8713 void Assembler::clwb(Address adr) { |
|
8714 assert(VM_Version::supports_clwb(), "should do!"); |
|
8715 // adr should be base reg only with no index or offset |
|
8716 assert(adr.index() == noreg, "index should be noreg"); |
|
8717 assert(adr.scale() == Address::no_scale, "scale should be no_scale"); |
|
8718 assert(adr.disp() == 0, "displacement should be 0"); |
|
8719 // instruction prefix is 0x66 |
|
8720 emit_int8(0x66); |
|
8721 prefix(adr); |
|
8722 // opcode family is 0x0f 0xAE |
|
8723 emit_int8(0x0F); |
|
8724 emit_int8((unsigned char)0xAE); |
|
8725 // extended opcode byte is 6 == rsi |
|
8726 emit_operand(rsi, adr); |
8603 } |
8727 } |
8604 |
8728 |
8605 void Assembler::cmovq(Condition cc, Register dst, Register src) { |
8729 void Assembler::cmovq(Condition cc, Register dst, Register src) { |
8606 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
8730 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
8607 emit_int8(0x0F); |
8731 emit_int8(0x0F); |