1 /* |
1 /* |
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. |
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved. |
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved. |
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved. |
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
5 * |
5 * |
6 * This code is free software; you can redistribute it and/or modify it |
6 * This code is free software; you can redistribute it and/or modify it |
7 * under the terms of the GNU General Public License version 2 only, as |
7 * under the terms of the GNU General Public License version 2 only, as |
314 |
314 |
315 __ bind(dont); |
315 __ bind(dont); |
316 return start_offset; |
316 return start_offset; |
317 } |
317 } |
318 |
318 |
|
319 void LIR_Assembler::clinit_barrier(ciMethod* method) { |
|
320 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); |
|
321 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); |
|
322 |
|
323 Label L_skip_barrier; |
|
324 |
|
325 __ mov_metadata(rscratch2, method->holder()->constant_encoding()); |
|
326 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/); |
|
327 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); |
|
328 __ bind(L_skip_barrier); |
|
329 } |
319 |
330 |
320 void LIR_Assembler::jobject2reg(jobject o, Register reg) { |
331 void LIR_Assembler::jobject2reg(jobject o, Register reg) { |
321 if (o == NULL) { |
332 if (o == NULL) { |
322 __ mov(reg, zr); |
333 __ mov(reg, zr); |
323 } else { |
334 } else { |
715 __ verify_oop(src->as_register()); |
726 __ verify_oop(src->as_register()); |
716 } |
727 } |
717 move_regs(src->as_register(), dest->as_register()); |
728 move_regs(src->as_register(), dest->as_register()); |
718 |
729 |
719 } else if (dest->is_double_cpu()) { |
730 } else if (dest->is_double_cpu()) { |
720 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { |
731 if (is_reference_type(src->type())) { |
721 // Surprising to me but we can see move of a long to t_object |
732 // Surprising to me but we can see move of a long to t_object |
722 __ verify_oop(src->as_register()); |
733 __ verify_oop(src->as_register()); |
723 move_regs(src->as_register(), dest->as_register_lo()); |
734 move_regs(src->as_register(), dest->as_register_lo()); |
724 return; |
735 return; |
725 } |
736 } |
743 } |
754 } |
744 } |
755 } |
745 |
756 |
746 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
757 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { |
747 if (src->is_single_cpu()) { |
758 if (src->is_single_cpu()) { |
748 if (type == T_ARRAY || type == T_OBJECT) { |
759 if (is_reference_type(type)) { |
749 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); |
760 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); |
750 __ verify_oop(src->as_register()); |
761 __ verify_oop(src->as_register()); |
751 } else if (type == T_METADATA || type == T_DOUBLE) { |
762 } else if (type == T_METADATA || type == T_DOUBLE) { |
752 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); |
763 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix())); |
753 } else { |
764 } else { |
781 if (patch_code != lir_patch_none) { |
792 if (patch_code != lir_patch_none) { |
782 deoptimize_trap(info); |
793 deoptimize_trap(info); |
783 return; |
794 return; |
784 } |
795 } |
785 |
796 |
786 if (type == T_ARRAY || type == T_OBJECT) { |
797 if (is_reference_type(type)) { |
787 __ verify_oop(src->as_register()); |
798 __ verify_oop(src->as_register()); |
788 |
799 |
789 if (UseCompressedOops && !wide) { |
800 if (UseCompressedOops && !wide) { |
790 __ encode_heap_oop(compressed_src, src->as_register()); |
801 __ encode_heap_oop(compressed_src, src->as_register()); |
791 } else { |
802 } else { |
856 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
867 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { |
857 assert(src->is_stack(), "should not call otherwise"); |
868 assert(src->is_stack(), "should not call otherwise"); |
858 assert(dest->is_register(), "should not call otherwise"); |
869 assert(dest->is_register(), "should not call otherwise"); |
859 |
870 |
860 if (dest->is_single_cpu()) { |
871 if (dest->is_single_cpu()) { |
861 if (type == T_ARRAY || type == T_OBJECT) { |
872 if (is_reference_type(type)) { |
862 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
873 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
863 __ verify_oop(dest->as_register()); |
874 __ verify_oop(dest->as_register()); |
864 } else if (type == T_METADATA) { |
875 } else if (type == T_METADATA) { |
865 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
876 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
866 } else { |
877 } else { |
1006 |
1017 |
1007 default: |
1018 default: |
1008 ShouldNotReachHere(); |
1019 ShouldNotReachHere(); |
1009 } |
1020 } |
1010 |
1021 |
1011 if (type == T_ARRAY || type == T_OBJECT) { |
1022 if (is_reference_type(type)) { |
1012 if (UseCompressedOops && !wide) { |
1023 if (UseCompressedOops && !wide) { |
1013 __ decode_heap_oop(dest->as_register()); |
1024 __ decode_heap_oop(dest->as_register()); |
1014 } |
1025 } |
1015 __ verify_oop(dest->as_register()); |
1026 |
|
1027 if (!UseZGC) { |
|
1028 // Load barrier has not yet been applied, so ZGC can't verify the oop here |
|
1029 __ verify_oop(dest->as_register()); |
|
1030 } |
1016 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { |
1031 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { |
1017 if (UseCompressedClassPointers) { |
1032 if (UseCompressedClassPointers) { |
1018 __ decode_klass_not_null(dest->as_register()); |
1033 __ decode_klass_not_null(dest->as_register()); |
1019 } |
1034 } |
1020 } |
1035 } |
1069 if (op->code() == lir_cond_float_branch) { |
1084 if (op->code() == lir_cond_float_branch) { |
1070 bool is_unordered = (op->ublock() == op->block()); |
1085 bool is_unordered = (op->ublock() == op->block()); |
1071 // Assembler::EQ does not permit unordered branches, so we add |
1086 // Assembler::EQ does not permit unordered branches, so we add |
1072 // another branch here. Likewise, Assembler::NE does not permit |
1087 // another branch here. Likewise, Assembler::NE does not permit |
1073 // ordered branches. |
1088 // ordered branches. |
1074 if (is_unordered && op->cond() == lir_cond_equal |
1089 if ((is_unordered && op->cond() == lir_cond_equal) |
1075 || !is_unordered && op->cond() == lir_cond_notEqual) |
1090 || (!is_unordered && op->cond() == lir_cond_notEqual)) |
1076 __ br(Assembler::VS, *(op->ublock()->label())); |
1091 __ br(Assembler::VS, *(op->ublock()->label())); |
1077 switch(op->cond()) { |
1092 switch(op->cond()) { |
1078 case lir_cond_equal: acond = Assembler::EQ; break; |
1093 case lir_cond_equal: acond = Assembler::EQ; break; |
1079 case lir_cond_notEqual: acond = Assembler::NE; break; |
1094 case lir_cond_notEqual: acond = Assembler::NE; break; |
1080 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break; |
1095 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break; |
1210 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
1225 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { |
1211 Register len = op->len()->as_register(); |
1226 Register len = op->len()->as_register(); |
1212 __ uxtw(len, len); |
1227 __ uxtw(len, len); |
1213 |
1228 |
1214 if (UseSlowPath || |
1229 if (UseSlowPath || |
1215 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || |
1230 (!UseFastNewObjectArray && is_reference_type(op->type())) || |
1216 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { |
1231 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { |
1217 __ b(*op->stub()->entry()); |
1232 __ b(*op->stub()->entry()); |
1218 } else { |
1233 } else { |
1219 Register tmp1 = op->tmp1()->as_register(); |
1234 Register tmp1 = op->tmp1()->as_register(); |
1220 Register tmp2 = op->tmp2()->as_register(); |
1235 Register tmp2 = op->tmp2()->as_register(); |
1221 Register tmp3 = op->tmp3()->as_register(); |
1236 Register tmp3 = op->tmp3()->as_register(); |
1780 } else if (left->is_single_fpu()) { |
1795 } else if (left->is_single_fpu()) { |
1781 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register"); |
1796 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register"); |
1782 switch (code) { |
1797 switch (code) { |
1783 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
1798 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
1784 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
1799 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
|
1800 case lir_mul_strictfp: // fall through |
1785 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
1801 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
|
1802 case lir_div_strictfp: // fall through |
1786 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
1803 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; |
1787 default: |
1804 default: |
1788 ShouldNotReachHere(); |
1805 ShouldNotReachHere(); |
1789 } |
1806 } |
1790 } else if (left->is_double_fpu()) { |
1807 } else if (left->is_double_fpu()) { |
1791 if (right->is_double_fpu()) { |
1808 if (right->is_double_fpu()) { |
1792 // cpu register - cpu register |
1809 // fpu register - fpu register |
1793 switch (code) { |
1810 switch (code) { |
1794 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
1811 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
1795 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
1812 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
|
1813 case lir_mul_strictfp: // fall through |
1796 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
1814 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
|
1815 case lir_div_strictfp: // fall through |
1797 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
1816 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; |
1798 default: |
1817 default: |
1799 ShouldNotReachHere(); |
1818 ShouldNotReachHere(); |
1800 } |
1819 } |
1801 } else { |
1820 } else { |
1927 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) { |
1946 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) { |
1928 Register reg1 = as_reg(opr1); |
1947 Register reg1 = as_reg(opr1); |
1929 if (opr2->is_single_cpu()) { |
1948 if (opr2->is_single_cpu()) { |
1930 // cpu register - cpu register |
1949 // cpu register - cpu register |
1931 Register reg2 = opr2->as_register(); |
1950 Register reg2 = opr2->as_register(); |
1932 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
1951 if (is_reference_type(opr1->type())) { |
1933 __ cmpoop(reg1, reg2); |
1952 __ cmpoop(reg1, reg2); |
1934 } else { |
1953 } else { |
1935 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); |
1954 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); |
1936 __ cmpw(reg1, reg2); |
1955 __ cmpw(reg1, reg2); |
1937 } |
1956 } |
1938 return; |
1957 return; |
1939 } |
1958 } |
1940 if (opr2->is_double_cpu()) { |
1959 if (opr2->is_double_cpu()) { |
2222 __ resolve(ACCESS_WRITE, dst); |
2241 __ resolve(ACCESS_WRITE, dst); |
2223 |
2242 |
2224 CodeStub* stub = op->stub(); |
2243 CodeStub* stub = op->stub(); |
2225 int flags = op->flags(); |
2244 int flags = op->flags(); |
2226 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
2245 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; |
2227 if (basic_type == T_ARRAY) basic_type = T_OBJECT; |
2246 if (is_reference_type(basic_type)) basic_type = T_OBJECT; |
2228 |
2247 |
2229 // if we don't know anything, just go through the generic arraycopy |
2248 // if we don't know anything, just go through the generic arraycopy |
2230 if (default_type == NULL // || basic_type == T_OBJECT |
2249 if (default_type == NULL // || basic_type == T_OBJECT |
2231 ) { |
2250 ) { |
2232 Label done; |
2251 Label done; |
2864 } |
2883 } |
2865 } |
2884 } |
2866 |
2885 |
2867 |
2886 |
2868 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
2887 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { |
2869 assert(patch_code == lir_patch_none, "Patch code not supported"); |
2888 if (patch_code != lir_patch_none) { |
|
2889 deoptimize_trap(info); |
|
2890 return; |
|
2891 } |
|
2892 |
2870 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); |
2893 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); |
2871 } |
2894 } |
2872 |
2895 |
2873 |
2896 |
2874 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
2897 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { |
2877 CodeBlob *cb = CodeCache::find_blob(dest); |
2900 CodeBlob *cb = CodeCache::find_blob(dest); |
2878 if (cb) { |
2901 if (cb) { |
2879 __ far_call(RuntimeAddress(dest)); |
2902 __ far_call(RuntimeAddress(dest)); |
2880 } else { |
2903 } else { |
2881 __ mov(rscratch1, RuntimeAddress(dest)); |
2904 __ mov(rscratch1, RuntimeAddress(dest)); |
2882 int len = args->length(); |
2905 __ blr(rscratch1); |
2883 int type = 0; |
|
2884 if (! result->is_illegal()) { |
|
2885 switch (result->type()) { |
|
2886 case T_VOID: |
|
2887 type = 0; |
|
2888 break; |
|
2889 case T_INT: |
|
2890 case T_LONG: |
|
2891 case T_OBJECT: |
|
2892 type = 1; |
|
2893 break; |
|
2894 case T_FLOAT: |
|
2895 type = 2; |
|
2896 break; |
|
2897 case T_DOUBLE: |
|
2898 type = 3; |
|
2899 break; |
|
2900 default: |
|
2901 ShouldNotReachHere(); |
|
2902 break; |
|
2903 } |
|
2904 } |
|
2905 int num_gpargs = 0; |
|
2906 int num_fpargs = 0; |
|
2907 for (int i = 0; i < args->length(); i++) { |
|
2908 LIR_Opr arg = args->at(i); |
|
2909 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) { |
|
2910 num_fpargs++; |
|
2911 } else { |
|
2912 num_gpargs++; |
|
2913 } |
|
2914 } |
|
2915 __ blrt(rscratch1, num_gpargs, num_fpargs, type); |
|
2916 } |
2906 } |
2917 |
2907 |
2918 if (info != NULL) { |
2908 if (info != NULL) { |
2919 add_call_info_here(info); |
2909 add_call_info_here(info); |
2920 } |
2910 } |
3139 } |
3129 } |
3140 |
3130 |
3141 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) { |
3131 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) { |
3142 Address addr = as_Address(src->as_address_ptr()); |
3132 Address addr = as_Address(src->as_address_ptr()); |
3143 BasicType type = src->type(); |
3133 BasicType type = src->type(); |
3144 bool is_oop = type == T_OBJECT || type == T_ARRAY; |
3134 bool is_oop = is_reference_type(type); |
3145 |
3135 |
3146 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr); |
3136 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr); |
3147 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr); |
3137 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr); |
3148 |
3138 |
3149 switch(type) { |
3139 switch(type) { |