13680 %} |
13680 %} |
13681 |
13681 |
13682 instruct mtvsrwz(vecX temp1, iRegIsrc src) %{ |
13682 instruct mtvsrwz(vecX temp1, iRegIsrc src) %{ |
13683 effect(DEF temp1, USE src); |
13683 effect(DEF temp1, USE src); |
13684 |
13684 |
|
13685 format %{ "MTVSRWZ $temp1, $src \t// Move to 16-byte register" %} |
13685 size(4); |
13686 size(4); |
13686 ins_encode %{ |
13687 ins_encode %{ |
13687 __ mtvsrwz($temp1$$VectorSRegister, $src$$Register); |
13688 __ mtvsrwz($temp1$$VectorSRegister, $src$$Register); |
13688 %} |
13689 %} |
13689 ins_pipe(pipe_class_default); |
13690 ins_pipe(pipe_class_default); |
13690 %} |
13691 %} |
13691 |
13692 |
13692 instruct xxspltw(vecX dst, vecX src, immI8 imm1) %{ |
13693 instruct xxspltw(vecX dst, vecX src, immI8 imm1) %{ |
13693 effect(DEF dst, USE src, USE imm1); |
13694 effect(DEF dst, USE src, USE imm1); |
13694 |
13695 |
|
13696 format %{ "XXSPLTW $dst, $src, $imm1 \t// Splat word" %} |
13695 size(4); |
13697 size(4); |
13696 ins_encode %{ |
13698 ins_encode %{ |
13697 __ xxspltw($dst$$VectorSRegister, $src$$VectorSRegister, $imm1$$constant); |
13699 __ xxspltw($dst$$VectorSRegister, $src$$VectorSRegister, $imm1$$constant); |
|
13700 %} |
|
13701 ins_pipe(pipe_class_default); |
|
13702 %} |
|
13703 |
|
13704 instruct xscvdpspn_regF(vecX dst, regF src) %{ |
|
13705 effect(DEF dst, USE src); |
|
13706 |
|
13707 format %{ "XSCVDPSPN $dst, $src \t// Convert scalar single precision to vector single precision" %} |
|
13708 size(4); |
|
13709 ins_encode %{ |
|
13710 __ xscvdpspn($dst$$VectorSRegister, $src$$FloatRegister->to_vsr()); |
13698 %} |
13711 %} |
13699 ins_pipe(pipe_class_default); |
13712 ins_pipe(pipe_class_default); |
13700 %} |
13713 %} |
13701 |
13714 |
13702 //---------- Replicate Vector Instructions ------------------------------------ |
13715 //---------- Replicate Vector Instructions ------------------------------------ |
14358 __ mulldo_(R0, $op1$$Register, $op2$$Register); |
14371 __ mulldo_(R0, $op1$$Register, $op2$$Register); |
14359 %} |
14372 %} |
14360 ins_pipe(pipe_class_default); |
14373 ins_pipe(pipe_class_default); |
14361 %} |
14374 %} |
14362 |
14375 |
14363 |
|
14364 instruct repl4F_reg_Ex(vecX dst, regF src) %{ |
14376 instruct repl4F_reg_Ex(vecX dst, regF src) %{ |
14365 match(Set dst (ReplicateF src)); |
14377 match(Set dst (ReplicateF src)); |
14366 predicate(n->as_Vector()->length() == 4); |
14378 predicate(n->as_Vector()->length() == 4); |
14367 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); |
14379 ins_cost(DEFAULT_COST); |
14368 expand %{ |
14380 expand %{ |
14369 stackSlotL tmpS; |
|
14370 iRegIdst tmpI; |
|
14371 iRegLdst tmpL; |
|
14372 vecX tmpV; |
14381 vecX tmpV; |
14373 immI8 zero %{ (int) 0 %} |
14382 immI8 zero %{ (int) 0 %} |
14374 |
14383 |
14375 moveF2I_reg_stack(tmpS, src); // Move float to stack. |
14384 xscvdpspn_regF(tmpV, src); |
14376 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. |
14385 xxspltw(dst, tmpV, zero); |
14377 moveReg(tmpL, tmpI); // Move int to long reg. |
|
14378 repl32(tmpL); // Replicate bitpattern. |
|
14379 mtvsrd(tmpV, tmpL); |
|
14380 xxpermdi(dst, tmpV, tmpV, zero); |
|
14381 %} |
14386 %} |
14382 %} |
14387 %} |
14383 |
14388 |
14384 instruct repl4F_immF_Ex(vecX dst, immF src, iRegLdst tmp) %{ |
14389 instruct repl4F_immF_Ex(vecX dst, immF src, iRegLdst tmp) %{ |
14385 match(Set dst (ReplicateF src)); |
14390 match(Set dst (ReplicateF src)); |
14402 %} |
14407 %} |
14403 |
14408 |
14404 instruct repl2D_reg_Ex(vecX dst, regD src) %{ |
14409 instruct repl2D_reg_Ex(vecX dst, regD src) %{ |
14405 match(Set dst (ReplicateD src)); |
14410 match(Set dst (ReplicateD src)); |
14406 predicate(n->as_Vector()->length() == 2); |
14411 predicate(n->as_Vector()->length() == 2); |
14407 expand %{ |
14412 |
14408 stackSlotL tmpS; |
14413 format %{ "XXPERMDI $dst, $src, $src, 0 \t// Splat doubleword" %} |
14409 iRegLdst tmpL; |
14414 size(4); |
14410 iRegLdst tmp; |
14415 ins_encode %{ |
14411 vecX tmpV; |
14416 __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0); |
14412 immI8 zero %{ (int) 0 %} |
14417 %} |
14413 moveD2L_reg_stack(tmpS, src); |
14418 ins_pipe(pipe_class_default); |
14414 moveD2L_stack_reg(tmpL, tmpS); |
|
14415 mtvsrd(tmpV, tmpL); |
|
14416 xxpermdi(dst, tmpV, tmpV, zero); |
|
14417 %} |
|
14418 %} |
14419 %} |
14419 |
14420 |
14420 instruct repl2D_immI0(vecX dst, immI_0 zero) %{ |
14421 instruct repl2D_immI0(vecX dst, immI_0 zero) %{ |
14421 match(Set dst (ReplicateD zero)); |
14422 match(Set dst (ReplicateD zero)); |
14422 predicate(n->as_Vector()->length() == 2); |
14423 predicate(n->as_Vector()->length() == 2); |
14443 |
14444 |
14444 instruct mtvsrd(vecX dst, iRegLsrc src) %{ |
14445 instruct mtvsrd(vecX dst, iRegLsrc src) %{ |
14445 predicate(false); |
14446 predicate(false); |
14446 effect(DEF dst, USE src); |
14447 effect(DEF dst, USE src); |
14447 |
14448 |
14448 format %{ "MTVSRD $dst, $src \t// Move to 16-byte register"%} |
14449 format %{ "MTVSRD $dst, $src \t// Move to 16-byte register" %} |
14449 size(4); |
14450 size(4); |
14450 ins_encode %{ |
14451 ins_encode %{ |
14451 __ mtvsrd($dst$$VectorSRegister, $src$$Register); |
14452 __ mtvsrd($dst$$VectorSRegister, $src$$Register); |
14452 %} |
14453 %} |
14453 ins_pipe(pipe_class_default); |
14454 ins_pipe(pipe_class_default); |
14454 %} |
14455 %} |
14455 |
14456 |
14456 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{ |
14457 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{ |
14457 effect(DEF dst, USE src, USE zero); |
14458 effect(DEF dst, USE src, USE zero); |
14458 |
14459 |
14459 format %{ "XXSPLATD $dst, $src, $zero \t// Permute 16-byte register"%} |
14460 format %{ "XXSPLATD $dst, $src, $zero \t// Splat doubleword" %} |
14460 size(4); |
14461 size(4); |
14461 ins_encode %{ |
14462 ins_encode %{ |
14462 __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant); |
14463 __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant); |
14463 %} |
14464 %} |
14464 ins_pipe(pipe_class_default); |
14465 ins_pipe(pipe_class_default); |
14465 %} |
14466 %} |
14466 |
14467 |
14467 instruct xxpermdi(vecX dst, vecX src1, vecX src2, immI8 zero) %{ |
14468 instruct xxpermdi(vecX dst, vecX src1, vecX src2, immI8 zero) %{ |
14468 effect(DEF dst, USE src1, USE src2, USE zero); |
14469 effect(DEF dst, USE src1, USE src2, USE zero); |
14469 |
14470 |
14470 format %{ "XXPERMDI $dst, $src1, $src2, $zero \t// Permute 16-byte register"%} |
14471 format %{ "XXPERMDI $dst, $src1, $src2, $zero \t// Splat doubleword" %} |
14471 size(4); |
14472 size(4); |
14472 ins_encode %{ |
14473 ins_encode %{ |
14473 __ xxpermdi($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister, $zero$$constant); |
14474 __ xxpermdi($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister, $zero$$constant); |
14474 %} |
14475 %} |
14475 ins_pipe(pipe_class_default); |
14476 ins_pipe(pipe_class_default); |