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1 /* |
1 /* |
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2 * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. |
2 * Copyright (c) 2019, Red Hat Inc. All rights reserved. |
3 * Copyright (c) 2019, Red Hat Inc. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * |
5 * |
5 * This code is free software; you can redistribute it and/or modify it |
6 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as |
7 * under the terms of the GNU General Public License version 2 only, as |
92 * The actual value for this field is injected by the JVM. |
93 * The actual value for this field is injected by the JVM. |
93 */ |
94 */ |
94 |
95 |
95 static final boolean UNALIGNED_ACCESS; |
96 static final boolean UNALIGNED_ACCESS; |
96 |
97 |
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98 /** |
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99 * The size of an L1 data cache line which will be either a power |
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100 * of two or zero. |
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101 * |
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102 * <p>A non-zero value indicates that writeback to memory is |
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103 * enabled for the current processor. The value defines the |
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104 * natural alignment and size of any data cache line committed to |
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105 * memory by a single writeback operation. If data cache line |
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106 * writeback is not enabled for the current hardware the field |
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107 * will have value 0. |
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108 * |
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109 * @implNote |
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110 * The actual value for this field is injected by the JVM. |
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111 */ |
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112 |
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113 static final int DATA_CACHE_LINE_FLUSH_SIZE; |
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114 |
97 static { |
115 static { |
98 ADDRESS_SIZE0 = 0; |
116 ADDRESS_SIZE0 = 0; |
99 PAGE_SIZE = 0; |
117 PAGE_SIZE = 0; |
100 BIG_ENDIAN = false; |
118 BIG_ENDIAN = false; |
101 UNALIGNED_ACCESS = false; |
119 UNALIGNED_ACCESS = false; |
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120 DATA_CACHE_LINE_FLUSH_SIZE = 0; |
102 } |
121 } |
103 } |
122 } |