924     /**

   925      * Ensure writeback of a specified virtual memory address range

   926      * from cache to physical memory. All bytes in the address range

   927      * are guaranteed to have been written back to physical memory on

   928      * return from this call i.e. subsequently executed store

   929      * instructions are guaranteed not to be visible before the

   930      * writeback is completed.

   931      *

   932      * @param address

   933      *        the lowest byte address that must be guaranteed written

   934      *        back to memory. bytes at lower addresses may also be

   935      *        written back.

   936      *

   937      * @param length

   938      *        the length in bytes of the region starting at address

   939      *        that must be guaranteed written back to memory.

   940      *

   941      * @throws RuntimeException if memory writeback is not supported

   942      *         on the current hardware of if the arguments are invalid.

   943      *         (<em>Note:</em> after optimization, invalid inputs may

   944      *         go undetected, which will lead to unpredictable

   945      *         behavior)

   946      *

   947      * @since 14

   948      */

   949 

   950     public void writebackMemory(long address, long length) {

   951         checkWritebackEnabled();

   952         checkWritebackMemory(address, length);

   953 

   954         // perform any required pre-writeback barrier

   955         writebackPreSync0();

   956 

   957         // write back one cache line at a time

   958         long line = dataCacheLineAlignDown(address);

   959         long end = address + length;

   960         while (line < end) {

   961             writeback0(line);

   962             line += dataCacheLineFlushSize();

   963         }

   964 

   965         // perform any required post-writeback barrier

   966         writebackPostSync0();

   967     }

   968 

   969     /**

   970      * Validate the arguments to writebackMemory

   971      *

   972      * @throws RuntimeException if the arguments are invalid

   973      *         (<em>Note:</em> after optimization, invalid inputs may

   974      *         go undetected, which will lead to unpredictable

   975      *         behavior)

   976      */

   977     private void checkWritebackMemory(long address, long length) {

   978         checkNativeAddress(address);

   979         checkSize(length);

   980     }

   981 

   982     /**

   983      * Validate that the current hardware supports memory writeback.

   984      * (<em>Note:</em> this is a belt and braces check.  Clients are

   985      * expected to test whether writeback is enabled by calling

   986      * ({@link isWritebackEnabled #isWritebackEnabled} and avoid

   987      * calling method {@link writeback #writeback} if it is disabled).

   988      *

   989      *

   990      * @throws RuntimeException if memory writeback is not supported

   991      */

   992     private void checkWritebackEnabled() {

   993         if (!isWritebackEnabled()) {

   994             throw new RuntimeException("writebackMemory not enabled!");

   995         }

   996     }

   997 

   998     /**

   999      * force writeback of an individual cache line.

  1000      *

  1001      * @param address

  1002      *        the start address of the cache line to be written back

  1003      */

  1004     @HotSpotIntrinsicCandidate

  1005     private native void writeback0(long address);

  1006 

  1007      /**

  1008       * Serialize writeback operations relative to preceding memory writes.

  1009       */

  1010     @HotSpotIntrinsicCandidate

  1011     private native void writebackPreSync0();

  1012 

  1013      /**

  1014       * Serialize writeback operations relative to following memory writes.

  1015       */

  1016     @HotSpotIntrinsicCandidate

  1017     private native void writebackPostSync0();

  1018 

  1272 

  1273     /**

  1274      * Reports the size in bytes of a data cache line written back by

  1275      * the hardware cache line flush operation available to the JVM or

  1276      * 0 if data cache line flushing is not enabled.

  1277      */

  1278     public int dataCacheLineFlushSize() { return DATA_CACHE_LINE_FLUSH_SIZE; }

  1279 

  1280     /**

  1281      * Rounds down address to a data cache line boundary as

  1282      * determined by {@link #dataCacheLineFlushSize}

  1283      * @return the rounded down address

  1284      */

  1285     public long dataCacheLineAlignDown(long address) {

  1286         return (address & ~(DATA_CACHE_LINE_FLUSH_SIZE - 1));

  1287     }

  1288 

  1289     /**

  1290      * Returns true if data cache line writeback

  1291      */

  1292     public static boolean isWritebackEnabled() { return DATA_CACHE_LINE_FLUSH_SIZE != 0; }