1645 // cachewb node for guaranteeing writeback of the cache line at a

  1646 // given address to (non-volatile) RAM

  1647 class CacheWBNode : public Node {

  1648 public:

  1649   CacheWBNode(Node *ctrl, Node *mem, Node *addr) : Node(ctrl, mem, addr) {}

  1650   virtual int Opcode() const;

  1651   virtual uint ideal_reg() const { return NotAMachineReg; }

  1652   virtual uint match_edge(uint idx) const { return (idx == 2); }

  1653   virtual const TypePtr *adr_type() const { return TypePtr::BOTTOM; }

  1654   virtual const Type *bottom_type() const { return Type::MEMORY; }

  1655 };

  1656 

  1657 // cachewb pre sync node for ensuring that writebacks are serialised

  1658 // relative to preceding or following stores

  1659 class CacheWBPreSyncNode : public Node {

  1660 public:

  1661   CacheWBPreSyncNode(Node *ctrl, Node *mem) : Node(ctrl, mem) {}

  1662   virtual int Opcode() const;

  1663   virtual uint ideal_reg() const { return NotAMachineReg; }

  1664   virtual uint match_edge(uint idx) const { return false; }

  1665   virtual const TypePtr *adr_type() const { return TypePtr::BOTTOM; }

  1666   virtual const Type *bottom_type() const { return Type::MEMORY; }

  1667 };

  1668 

  1669 // cachewb pre sync node for ensuring that writebacks are serialised

  1670 // relative to preceding or following stores

  1671 class CacheWBPostSyncNode : public Node {

  1672 public:

  1673   CacheWBPostSyncNode(Node *ctrl, Node *mem) : Node(ctrl, mem) {}

  1674   virtual int Opcode() const;

  1675   virtual uint ideal_reg() const { return NotAMachineReg; }

  1676   virtual uint match_edge(uint idx) const { return false; }

  1677   virtual const TypePtr *adr_type() const { return TypePtr::BOTTOM; }

  1678   virtual const Type *bottom_type() const { return Type::MEMORY; }

  1679 };

  1680