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1 /* |
1 /* |
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * |
4 * |
5 * This code is free software; you can redistribute it and/or modify it |
5 * This code is free software; you can redistribute it and/or modify it |
6 * under the terms of the GNU General Public License version 2 only, as |
6 * under the terms of the GNU General Public License version 2 only, as |
7 * published by the Free Software Foundation. |
7 * published by the Free Software Foundation. |
20 * or visit www.oracle.com if you need additional information or have any |
20 * or visit www.oracle.com if you need additional information or have any |
21 * questions. |
21 * questions. |
22 * |
22 * |
23 */ |
23 */ |
24 |
24 |
25 #ifndef CPU_SPARC_VM_ICACHE_SPARC_HPP |
25 #ifndef CPU_SPARC_ICACHE_SPARC_HPP |
26 #define CPU_SPARC_VM_ICACHE_SPARC_HPP |
26 #define CPU_SPARC_ICACHE_SPARC_HPP |
27 |
27 |
28 // Interface for updating the instruction cache. Whenever the VM modifies |
28 // Interface for updating the instruction cache. Whenever the VM modifies |
29 // code, part of the processor instruction cache potentially has to be flushed. |
29 // code, part of the processor instruction cache potentially has to be flushed. |
30 |
30 |
31 |
31 |
38 }; |
38 }; |
39 |
39 |
40 // Use default implementation |
40 // Use default implementation |
41 }; |
41 }; |
42 |
42 |
43 #endif // CPU_SPARC_VM_ICACHE_SPARC_HPP |
43 #endif // CPU_SPARC_ICACHE_SPARC_HPP |