src/hotspot/cpu/ppc/c1_FrameMap_ppc.hpp
changeset 53244 9807daeb47c4
parent 47216 71c04702a3d5
equal deleted inserted replaced
53243:8bea4144b21c 53244:9807daeb47c4
     1 /*
     1 /*
     2  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
     2  * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
     3  * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     7  * under the terms of the GNU General Public License version 2 only, as
    21  * or visit www.oracle.com if you need additional information or have any
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    22  * questions.
    23  *
    23  *
    24  */
    24  */
    25 
    25 
    26 #ifndef CPU_PPC_VM_C1_FRAMEMAP_PPC_HPP
    26 #ifndef CPU_PPC_C1_FRAMEMAP_PPC_HPP
    27 #define CPU_PPC_VM_C1_FRAMEMAP_PPC_HPP
    27 #define CPU_PPC_C1_FRAMEMAP_PPC_HPP
    28 
    28 
    29  public:
    29  public:
    30 
    30 
    31   enum {
    31   enum {
    32     nof_reg_args = 8,   // Registers R3-R10 are available for parameter passing.
    32     nof_reg_args = 8,   // Registers R3-R10 are available for parameter passing.
   197   // R13: system thread id
   197   // R13: system thread id
   198   // R16: java thread
   198   // R16: java thread
   199   // R29: global TOC
   199   // R29: global TOC
   200   static bool reg_needs_save(Register r) { return r != R0 && r != R1 && r != R13 && r != R16 && r != R29; }
   200   static bool reg_needs_save(Register r) { return r != R0 && r != R1 && r != R13 && r != R16 && r != R29; }
   201 
   201 
   202 #endif // CPU_PPC_VM_C1_FRAMEMAP_PPC_HPP
   202 #endif // CPU_PPC_C1_FRAMEMAP_PPC_HPP