src/hotspot/cpu/aarch64/icache_aarch64.hpp
changeset 53244 9807daeb47c4
parent 47216 71c04702a3d5
equal deleted inserted replaced
53243:8bea4144b21c 53244:9807daeb47c4
     1 /*
     1 /*
     2  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
     2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
     3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     7  * under the terms of the GNU General Public License version 2 only, as
    21  * or visit www.oracle.com if you need additional information or have any
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    22  * questions.
    23  *
    23  *
    24  */
    24  */
    25 
    25 
    26 #ifndef CPU_AARCH64_VM_ICACHE_AARCH64_HPP
    26 #ifndef CPU_AARCH64_ICACHE_AARCH64_HPP
    27 #define CPU_AARCH64_VM_ICACHE_AARCH64_HPP
    27 #define CPU_AARCH64_ICACHE_AARCH64_HPP
    28 
    28 
    29 // Interface for updating the instruction cache.  Whenever the VM
    29 // Interface for updating the instruction cache.  Whenever the VM
    30 // modifies code, part of the processor instruction cache potentially
    30 // modifies code, part of the processor instruction cache potentially
    31 // has to be flushed.
    31 // has to be flushed.
    32 
    32 
    39   static void invalidate_range(address start, int nbytes) {
    39   static void invalidate_range(address start, int nbytes) {
    40     __clear_cache((char *)start, (char *)(start + nbytes));
    40     __clear_cache((char *)start, (char *)(start + nbytes));
    41   }
    41   }
    42 };
    42 };
    43 
    43 
    44 #endif // CPU_AARCH64_VM_ICACHE_AARCH64_HPP
    44 #endif // CPU_AARCH64_ICACHE_AARCH64_HPP