equal
deleted
inserted
replaced
472 // halves of T_LONG or T_DOUBLE |
472 // halves of T_LONG or T_DOUBLE |
473 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); |
473 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); |
474 regs[i].set_bad(); |
474 regs[i].set_bad(); |
475 break; |
475 break; |
476 case T_LONG: |
476 case T_LONG: |
477 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
477 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); |
478 // fall through |
478 // fall through |
479 case T_OBJECT: |
479 case T_OBJECT: |
480 case T_ARRAY: |
480 case T_ARRAY: |
481 case T_ADDRESS: |
481 case T_ADDRESS: |
482 if (int_args < Argument::n_int_register_parameters_j) { |
482 if (int_args < Argument::n_int_register_parameters_j) { |
493 regs[i].set1(VMRegImpl::stack2reg(stk_args)); |
493 regs[i].set1(VMRegImpl::stack2reg(stk_args)); |
494 stk_args += 2; |
494 stk_args += 2; |
495 } |
495 } |
496 break; |
496 break; |
497 case T_DOUBLE: |
497 case T_DOUBLE: |
498 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
498 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); |
499 if (fp_args < Argument::n_float_register_parameters_j) { |
499 if (fp_args < Argument::n_float_register_parameters_j) { |
500 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); |
500 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); |
501 } else { |
501 } else { |
502 regs[i].set2(VMRegImpl::stack2reg(stk_args)); |
502 regs[i].set2(VMRegImpl::stack2reg(stk_args)); |
503 stk_args += 2; |
503 stk_args += 2; |
1012 regs[i].set1(VMRegImpl::stack2reg(stk_args)); |
1012 regs[i].set1(VMRegImpl::stack2reg(stk_args)); |
1013 stk_args += 2; |
1013 stk_args += 2; |
1014 } |
1014 } |
1015 break; |
1015 break; |
1016 case T_LONG: |
1016 case T_LONG: |
1017 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
1017 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); |
1018 // fall through |
1018 // fall through |
1019 case T_OBJECT: |
1019 case T_OBJECT: |
1020 case T_ARRAY: |
1020 case T_ARRAY: |
1021 case T_ADDRESS: |
1021 case T_ADDRESS: |
1022 case T_METADATA: |
1022 case T_METADATA: |
1043 regs[i].set1(VMRegImpl::stack2reg(stk_args)); |
1043 regs[i].set1(VMRegImpl::stack2reg(stk_args)); |
1044 stk_args += 2; |
1044 stk_args += 2; |
1045 } |
1045 } |
1046 break; |
1046 break; |
1047 case T_DOUBLE: |
1047 case T_DOUBLE: |
1048 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
1048 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); |
1049 if (fp_args < Argument::n_float_register_parameters_c) { |
1049 if (fp_args < Argument::n_float_register_parameters_c) { |
1050 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); |
1050 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); |
1051 #ifdef _WIN64 |
1051 #ifdef _WIN64 |
1052 int_args++; |
1052 int_args++; |
1053 // Allocate slots for callee to stuff register args the stack. |
1053 // Allocate slots for callee to stuff register args the stack. |