equal
deleted
inserted
replaced
778 RegMask rm = lrgs(lr1).mask(); |
778 RegMask rm = lrgs(lr1).mask(); |
779 rm.AND(lrgs(lr2).mask()); |
779 rm.AND(lrgs(lr2).mask()); |
780 // Number of bits free |
780 // Number of bits free |
781 uint rm_size = rm.Size(); |
781 uint rm_size = rm.Size(); |
782 |
782 |
|
783 if (UseFPUForSpilling && rm.is_AllStack() ) { |
|
784 // Don't coalesce when frequency difference is large |
|
785 Block *dst_b = _phc._cfg._bbs[dst_copy->_idx]; |
|
786 Block *src_def_b = _phc._cfg._bbs[src_def->_idx]; |
|
787 if (src_def_b->_freq > 10*dst_b->_freq ) |
|
788 return false; |
|
789 } |
|
790 |
783 // If we can use any stack slot, then effective size is infinite |
791 // If we can use any stack slot, then effective size is infinite |
784 if( rm.is_AllStack() ) rm_size += 1000000; |
792 if( rm.is_AllStack() ) rm_size += 1000000; |
785 // Incompatible masks, no way to coalesce |
793 // Incompatible masks, no way to coalesce |
786 if( rm_size == 0 ) return false; |
794 if( rm_size == 0 ) return false; |
787 |
795 |