equal
deleted
inserted
replaced
1313 } |
1313 } |
1314 } |
1314 } |
1315 |
1315 |
1316 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
1316 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
1317 Register reg = addr->base()->as_register(); |
1317 Register reg = addr->base()->as_register(); |
1318 return Address(reg, addr->disp()); |
1318 LIR_Opr index = addr->index(); |
|
1319 if (index->is_illegal()) { |
|
1320 return Address(reg, addr->disp()); |
|
1321 } else { |
|
1322 assert (addr->disp() == 0, "unsupported address mode"); |
|
1323 return Address(reg, index->as_pointer_register()); |
|
1324 } |
1319 } |
1325 } |
1320 |
1326 |
1321 |
1327 |
1322 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
1328 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { |
1323 switch (type) { |
1329 switch (type) { |
3436 } |
3442 } |
3437 } |
3443 } |
3438 } |
3444 } |
3439 } |
3445 } |
3440 |
3446 |
3441 |
3447 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { |
3442 |
3448 LIR_Address* addr = src->as_address_ptr(); |
|
3449 |
|
3450 assert(data == dest, "swap uses only 2 operands"); |
|
3451 assert (code == lir_xchg, "no xadd on sparc"); |
|
3452 |
|
3453 if (data->type() == T_INT) { |
|
3454 __ swap(as_Address(addr), data->as_register()); |
|
3455 } else if (data->is_oop()) { |
|
3456 Register obj = data->as_register(); |
|
3457 Register narrow = tmp->as_register(); |
|
3458 #ifdef _LP64 |
|
3459 assert(UseCompressedOops, "swap is 32bit only"); |
|
3460 __ encode_heap_oop(obj, narrow); |
|
3461 __ swap(as_Address(addr), narrow); |
|
3462 __ decode_heap_oop(narrow, obj); |
|
3463 #else |
|
3464 __ swap(as_Address(addr), obj); |
|
3465 #endif |
|
3466 } else { |
|
3467 ShouldNotReachHere(); |
|
3468 } |
|
3469 } |
3443 |
3470 |
3444 #undef __ |
3471 #undef __ |