equal
deleted
inserted
replaced
13279 |
13279 |
13280 ins_encode %{ |
13280 ins_encode %{ |
13281 __ fmovs($dst$$Register, as_FloatRegister($src$$reg)); |
13281 __ fmovs($dst$$Register, as_FloatRegister($src$$reg)); |
13282 %} |
13282 %} |
13283 |
13283 |
13284 ins_pipe(pipe_class_memory); |
13284 ins_pipe(fp_f2i); |
13285 |
13285 |
13286 %} |
13286 %} |
13287 |
13287 |
13288 instruct MoveI2F_reg_reg(vRegF dst, iRegI src) %{ |
13288 instruct MoveI2F_reg_reg(vRegF dst, iRegI src) %{ |
13289 |
13289 |
13297 |
13297 |
13298 ins_encode %{ |
13298 ins_encode %{ |
13299 __ fmovs(as_FloatRegister($dst$$reg), $src$$Register); |
13299 __ fmovs(as_FloatRegister($dst$$reg), $src$$Register); |
13300 %} |
13300 %} |
13301 |
13301 |
13302 ins_pipe(pipe_class_memory); |
13302 ins_pipe(fp_i2f); |
13303 |
13303 |
13304 %} |
13304 %} |
13305 |
13305 |
13306 instruct MoveD2L_reg_reg(iRegLNoSp dst, vRegD src) %{ |
13306 instruct MoveD2L_reg_reg(iRegLNoSp dst, vRegD src) %{ |
13307 |
13307 |
13315 |
13315 |
13316 ins_encode %{ |
13316 ins_encode %{ |
13317 __ fmovd($dst$$Register, as_FloatRegister($src$$reg)); |
13317 __ fmovd($dst$$Register, as_FloatRegister($src$$reg)); |
13318 %} |
13318 %} |
13319 |
13319 |
13320 ins_pipe(pipe_class_memory); |
13320 ins_pipe(fp_d2l); |
13321 |
13321 |
13322 %} |
13322 %} |
13323 |
13323 |
13324 instruct MoveL2D_reg_reg(vRegD dst, iRegL src) %{ |
13324 instruct MoveL2D_reg_reg(vRegD dst, iRegL src) %{ |
13325 |
13325 |
13333 |
13333 |
13334 ins_encode %{ |
13334 ins_encode %{ |
13335 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register); |
13335 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register); |
13336 %} |
13336 %} |
13337 |
13337 |
13338 ins_pipe(pipe_class_memory); |
13338 ins_pipe(fp_l2d); |
13339 |
13339 |
13340 %} |
13340 %} |
13341 |
13341 |
13342 // ============================================================================ |
13342 // ============================================================================ |
13343 // clearing of an array |
13343 // clearing of an array |
16500 ins_encode %{ |
16500 ins_encode %{ |
16501 __ sshl(as_FloatRegister($dst$$reg), __ T2S, |
16501 __ sshl(as_FloatRegister($dst$$reg), __ T2S, |
16502 as_FloatRegister($src$$reg), |
16502 as_FloatRegister($src$$reg), |
16503 as_FloatRegister($shift$$reg)); |
16503 as_FloatRegister($shift$$reg)); |
16504 %} |
16504 %} |
16505 ins_pipe(vshift64_imm); |
16505 ins_pipe(vshift64); |
16506 %} |
16506 %} |
16507 |
16507 |
16508 instruct vsll4I(vecX dst, vecX src, vecX shift) %{ |
16508 instruct vsll4I(vecX dst, vecX src, vecX shift) %{ |
16509 predicate(n->as_Vector()->length() == 4); |
16509 predicate(n->as_Vector()->length() == 4); |
16510 match(Set dst (LShiftVI src shift)); |
16510 match(Set dst (LShiftVI src shift)); |
16514 ins_encode %{ |
16514 ins_encode %{ |
16515 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
16515 __ sshl(as_FloatRegister($dst$$reg), __ T4S, |
16516 as_FloatRegister($src$$reg), |
16516 as_FloatRegister($src$$reg), |
16517 as_FloatRegister($shift$$reg)); |
16517 as_FloatRegister($shift$$reg)); |
16518 %} |
16518 %} |
16519 ins_pipe(vshift128_imm); |
16519 ins_pipe(vshift128); |
16520 %} |
16520 %} |
16521 |
16521 |
16522 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{ |
16522 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{ |
16523 predicate(n->as_Vector()->length() == 2); |
16523 predicate(n->as_Vector()->length() == 2); |
16524 match(Set dst (URShiftVI src shift)); |
16524 match(Set dst (URShiftVI src shift)); |
16527 ins_encode %{ |
16527 ins_encode %{ |
16528 __ ushl(as_FloatRegister($dst$$reg), __ T2S, |
16528 __ ushl(as_FloatRegister($dst$$reg), __ T2S, |
16529 as_FloatRegister($src$$reg), |
16529 as_FloatRegister($src$$reg), |
16530 as_FloatRegister($shift$$reg)); |
16530 as_FloatRegister($shift$$reg)); |
16531 %} |
16531 %} |
16532 ins_pipe(vshift64_imm); |
16532 ins_pipe(vshift64); |
16533 %} |
16533 %} |
16534 |
16534 |
16535 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{ |
16535 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{ |
16536 predicate(n->as_Vector()->length() == 4); |
16536 predicate(n->as_Vector()->length() == 4); |
16537 match(Set dst (URShiftVI src shift)); |
16537 match(Set dst (URShiftVI src shift)); |
16540 ins_encode %{ |
16540 ins_encode %{ |
16541 __ ushl(as_FloatRegister($dst$$reg), __ T4S, |
16541 __ ushl(as_FloatRegister($dst$$reg), __ T4S, |
16542 as_FloatRegister($src$$reg), |
16542 as_FloatRegister($src$$reg), |
16543 as_FloatRegister($shift$$reg)); |
16543 as_FloatRegister($shift$$reg)); |
16544 %} |
16544 %} |
16545 ins_pipe(vshift128_imm); |
16545 ins_pipe(vshift128); |
16546 %} |
16546 %} |
16547 |
16547 |
16548 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{ |
16548 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{ |
16549 predicate(n->as_Vector()->length() == 2); |
16549 predicate(n->as_Vector()->length() == 2); |
16550 match(Set dst (LShiftVI src shift)); |
16550 match(Set dst (LShiftVI src shift)); |
16658 ins_encode %{ |
16658 ins_encode %{ |
16659 __ shl(as_FloatRegister($dst$$reg), __ T2D, |
16659 __ shl(as_FloatRegister($dst$$reg), __ T2D, |
16660 as_FloatRegister($src$$reg), |
16660 as_FloatRegister($src$$reg), |
16661 (int)$shift$$constant & 63); |
16661 (int)$shift$$constant & 63); |
16662 %} |
16662 %} |
16663 ins_pipe(vshift128); |
16663 ins_pipe(vshift128_imm); |
16664 %} |
16664 %} |
16665 |
16665 |
16666 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{ |
16666 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{ |
16667 predicate(n->as_Vector()->length() == 2); |
16667 predicate(n->as_Vector()->length() == 2); |
16668 match(Set dst (RShiftVL src shift)); |
16668 match(Set dst (RShiftVL src shift)); |