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src/hotspot/cpu/x86/x86_64.ad
changeset 51996 84743156e780
parent 51857 9978fea8a371
child 52142 ca0c25e01c5b
equal deleted inserted replaced
51995:f7babf9d1592 51996:84743156e780 
     1 //
 
     1 //
 
     2 // Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
 
     2 // Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
 
     3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 
     3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 
     4 //
 
     4 //
 
     5 // This code is free software; you can redistribute it and/or modify it
 
     5 // This code is free software; you can redistribute it and/or modify it
 
     6 // under the terms of the GNU General Public License version 2 only, as
 
     6 // under the terms of the GNU General Public License version 2 only, as
 
     7 // published by the Free Software Foundation.
 
     7 // published by the Free Software Foundation.
 
  2339     emit_d32(cbuf, 0x00);
 
  2339     emit_d32(cbuf, 0x00);
 
  2340   %}
 
  2340   %}
 
  2341 
  2341 
  2342   enc_class lock_prefix()
 
  2342   enc_class lock_prefix()
 
  2343   %{
 
  2343   %{
 
  2344     if (os::is_MP()) {
 
  2344     emit_opcode(cbuf, 0xF0); // lock
 
  2345       emit_opcode(cbuf, 0xF0); // lock
 
       
  2346     }
 
       
  2347   %}
 
  2345   %}
 
  2348 
  2346 
  2349   enc_class REX_mem(memory mem)
 
  2347   enc_class REX_mem(memory mem)
 
  2350   %{
 
  2348   %{
 
  2351     if ($mem$$base >= 8) {
 
  2349     if ($mem$$base >= 8) {
 
  6599   effect(KILL cr);
 
  6597   effect(KILL cr);
 
  6600   ins_cost(400);
 
  6598   ins_cost(400);
 
  6601 
  6599 
  6602   format %{
 
  6600   format %{
 
  6603     $$template
 
  6601     $$template
 
  6604     if (os::is_MP()) {
 
  6602     $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
 
  6605       $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
 
       
  6606     } else {
 
       
  6607       $$emit$$"MEMBAR-volatile ! (empty encoding)"
 
       
  6608     }
 
       
  6609   %}
 
  6603   %}
 
  6610   ins_encode %{
 
  6604   ins_encode %{
 
  6611     __ membar(Assembler::StoreLoad);
 
  6605     __ membar(Assembler::StoreLoad);
 
  6612   %}
 
  6606   %}
 
  6613   ins_pipe(pipe_slow);
 
  6607   ins_pipe(pipe_slow);
 
  7799   predicate(n->as_LoadStore()->result_not_used());
 
  7793   predicate(n->as_LoadStore()->result_not_used());
 
  7800   match(Set dummy (GetAndAddB mem add));
 
  7794   match(Set dummy (GetAndAddB mem add));
 
  7801   effect(KILL cr);
 
  7795   effect(KILL cr);
 
  7802   format %{ "ADDB  [$mem],$add" %}
 
  7796   format %{ "ADDB  [$mem],$add" %}
 
  7803   ins_encode %{
 
  7797   ins_encode %{
 
  7804     if (os::is_MP()) { __ lock(); }
 
  7798     __ lock();
 
  7805     __ addb($mem$$Address, $add$$constant);
 
  7799     __ addb($mem$$Address, $add$$constant);
 
  7806   %}
 
  7800   %}
 
  7807   ins_pipe( pipe_cmpxchg );
 
  7801   ins_pipe( pipe_cmpxchg );
 
  7808 %}
 
  7802 %}
 
  7809 
  7803 
  7810 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
 
  7804 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
 
  7811   match(Set newval (GetAndAddB mem newval));
 
  7805   match(Set newval (GetAndAddB mem newval));
 
  7812   effect(KILL cr);
 
  7806   effect(KILL cr);
 
  7813   format %{ "XADDB  [$mem],$newval" %}
 
  7807   format %{ "XADDB  [$mem],$newval" %}
 
  7814   ins_encode %{
 
  7808   ins_encode %{
 
  7815     if (os::is_MP()) { __ lock(); }
 
  7809     __ lock();
 
  7816     __ xaddb($mem$$Address, $newval$$Register);
 
  7810     __ xaddb($mem$$Address, $newval$$Register);
 
  7817   %}
 
  7811   %}
 
  7818   ins_pipe( pipe_cmpxchg );
 
  7812   ins_pipe( pipe_cmpxchg );
 
  7819 %}
 
  7813 %}
 
  7820 
  7814 
  7822   predicate(n->as_LoadStore()->result_not_used());
 
  7816   predicate(n->as_LoadStore()->result_not_used());
 
  7823   match(Set dummy (GetAndAddS mem add));
 
  7817   match(Set dummy (GetAndAddS mem add));
 
  7824   effect(KILL cr);
 
  7818   effect(KILL cr);
 
  7825   format %{ "ADDW  [$mem],$add" %}
 
  7819   format %{ "ADDW  [$mem],$add" %}
 
  7826   ins_encode %{
 
  7820   ins_encode %{
 
  7827     if (os::is_MP()) { __ lock(); }
 
  7821     __ lock();
 
  7828     __ addw($mem$$Address, $add$$constant);
 
  7822     __ addw($mem$$Address, $add$$constant);
 
  7829   %}
 
  7823   %}
 
  7830   ins_pipe( pipe_cmpxchg );
 
  7824   ins_pipe( pipe_cmpxchg );
 
  7831 %}
 
  7825 %}
 
  7832 
  7826 
  7833 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
 
  7827 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
 
  7834   match(Set newval (GetAndAddS mem newval));
 
  7828   match(Set newval (GetAndAddS mem newval));
 
  7835   effect(KILL cr);
 
  7829   effect(KILL cr);
 
  7836   format %{ "XADDW  [$mem],$newval" %}
 
  7830   format %{ "XADDW  [$mem],$newval" %}
 
  7837   ins_encode %{
 
  7831   ins_encode %{
 
  7838     if (os::is_MP()) { __ lock(); }
 
  7832     __ lock();
 
  7839     __ xaddw($mem$$Address, $newval$$Register);
 
  7833     __ xaddw($mem$$Address, $newval$$Register);
 
  7840   %}
 
  7834   %}
 
  7841   ins_pipe( pipe_cmpxchg );
 
  7835   ins_pipe( pipe_cmpxchg );
 
  7842 %}
 
  7836 %}
 
  7843 
  7837 
  7845   predicate(n->as_LoadStore()->result_not_used());
 
  7839   predicate(n->as_LoadStore()->result_not_used());
 
  7846   match(Set dummy (GetAndAddI mem add));
 
  7840   match(Set dummy (GetAndAddI mem add));
 
  7847   effect(KILL cr);
 
  7841   effect(KILL cr);
 
  7848   format %{ "ADDL  [$mem],$add" %}
 
  7842   format %{ "ADDL  [$mem],$add" %}
 
  7849   ins_encode %{
 
  7843   ins_encode %{
 
  7850     if (os::is_MP()) { __ lock(); }
 
  7844     __ lock();
 
  7851     __ addl($mem$$Address, $add$$constant);
 
  7845     __ addl($mem$$Address, $add$$constant);
 
  7852   %}
 
  7846   %}
 
  7853   ins_pipe( pipe_cmpxchg );
 
  7847   ins_pipe( pipe_cmpxchg );
 
  7854 %}
 
  7848 %}
 
  7855 
  7849 
  7856 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
 
  7850 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
 
  7857   match(Set newval (GetAndAddI mem newval));
 
  7851   match(Set newval (GetAndAddI mem newval));
 
  7858   effect(KILL cr);
 
  7852   effect(KILL cr);
 
  7859   format %{ "XADDL  [$mem],$newval" %}
 
  7853   format %{ "XADDL  [$mem],$newval" %}
 
  7860   ins_encode %{
 
  7854   ins_encode %{
 
  7861     if (os::is_MP()) { __ lock(); }
 
  7855     __ lock();
 
  7862     __ xaddl($mem$$Address, $newval$$Register);
 
  7856     __ xaddl($mem$$Address, $newval$$Register);
 
  7863   %}
 
  7857   %}
 
  7864   ins_pipe( pipe_cmpxchg );
 
  7858   ins_pipe( pipe_cmpxchg );
 
  7865 %}
 
  7859 %}
 
  7866 
  7860 
  7868   predicate(n->as_LoadStore()->result_not_used());
 
  7862   predicate(n->as_LoadStore()->result_not_used());
 
  7869   match(Set dummy (GetAndAddL mem add));
 
  7863   match(Set dummy (GetAndAddL mem add));
 
  7870   effect(KILL cr);
 
  7864   effect(KILL cr);
 
  7871   format %{ "ADDQ  [$mem],$add" %}
 
  7865   format %{ "ADDQ  [$mem],$add" %}
 
  7872   ins_encode %{
 
  7866   ins_encode %{
 
  7873     if (os::is_MP()) { __ lock(); }
 
  7867     __ lock();
 
  7874     __ addq($mem$$Address, $add$$constant);
 
  7868     __ addq($mem$$Address, $add$$constant);
 
  7875   %}
 
  7869   %}
 
  7876   ins_pipe( pipe_cmpxchg );
 
  7870   ins_pipe( pipe_cmpxchg );
 
  7877 %}
 
  7871 %}
 
  7878 
  7872 
  7879 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
 
  7873 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
 
  7880   match(Set newval (GetAndAddL mem newval));
 
  7874   match(Set newval (GetAndAddL mem newval));
 
  7881   effect(KILL cr);
 
  7875   effect(KILL cr);
 
  7882   format %{ "XADDQ  [$mem],$newval" %}
 
  7876   format %{ "XADDQ  [$mem],$newval" %}
 
  7883   ins_encode %{
 
  7877   ins_encode %{
 
  7884     if (os::is_MP()) { __ lock(); }
 
  7878     __ lock();
 
  7885     __ xaddq($mem$$Address, $newval$$Register);
 
  7879     __ xaddq($mem$$Address, $newval$$Register);
 
  7886   %}
 
  7880   %}
 
  7887   ins_pipe( pipe_cmpxchg );
 
  7881   ins_pipe( pipe_cmpxchg );
 
  7888 %}
 
  7882 %}
 
  7889 
  7883 
 10896                  $tmp$$XMMRegister, false);
 
 10890                  $tmp$$XMMRegister, false);
 
 10897   %}
 
 10891   %}
 
 10898   ins_pipe(pipe_slow);
 
 10892   ins_pipe(pipe_slow);
 
 10899 %}
 
 10893 %}
 
 10900 
 10894 
 10901 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero, 
 10895 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
 
 10902                         Universe dummy, rFlagsReg cr)
 
 10896                         Universe dummy, rFlagsReg cr)
 
 10903 %{
 
 10897 %{
 
 10904   predicate(((ClearArrayNode*)n)->is_large());
 
 10898   predicate(((ClearArrayNode*)n)->is_large());
 
 10905   match(Set dummy (ClearArray cnt base));
 
 10899   match(Set dummy (ClearArray cnt base));
 
 10906   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
 
 10900   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
 
 10940        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
 
 10934        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
 
 10941        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
 
 10935        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
 
 10942     }
 
 10936     }
 
 10943   %}
 
 10937   %}
 
 10944   ins_encode %{
 
 10938   ins_encode %{
 
 10945     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, 
 10939     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
 
 10946                  $tmp$$XMMRegister, true);
 
 10940                  $tmp$$XMMRegister, true);
 
 10947   %}
 
 10941   %}
 
 10948   ins_pipe(pipe_slow);
 
 10942   ins_pipe(pipe_slow);
 
 10949 %}
 
 10943 %}
 
 10950 
 10944
jdk-sandbox