1878     Register reg1 = as_reg(opr1);

  1878     Register reg1 = as_reg(opr1);

  1879     if (opr2->is_single_cpu()) {

  1879     if (opr2->is_single_cpu()) {

  1880       // cpu register - cpu register

  1880       // cpu register - cpu register

  1881       Register reg2 = opr2->as_register();

  1881       Register reg2 = opr2->as_register();

  1882       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {

  1882       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {

  1884       } else {

  1884       } else {

  1885         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");

  1885         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");

  1886         __ cmpw(reg1, reg2);

  1886         __ cmpw(reg1, reg2);

  1887       }

  1887       }

  1888       return;

  1888       return;

  1909       case T_ADDRESS:

  1909       case T_ADDRESS:

  1910         imm = opr2->as_constant_ptr()->as_jint();

  1910         imm = opr2->as_constant_ptr()->as_jint();

  1911         break;

  1911         break;

  1912       case T_OBJECT:

  1912       case T_OBJECT:

  1913       case T_ARRAY:

  1913       case T_ARRAY:

  1916       default:

  1917       default:

  1917         ShouldNotReachHere();

  1918         ShouldNotReachHere();

  1918         imm = 0;  // unreachable

  1919         imm = 0;  // unreachable

  1919         break;

  1920         break;

  1920       }

  1921       }