1 /*

     2  * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    24 

    25 #ifndef OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_HPP

    26 #define OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_HPP

    27 

    28 // Included in orderAccess.hpp header file.

    29 

    30 // Compiler version last used for testing: gcc 4.8.2

    31 // Please update this information when this file changes

    32 

    33 // Implementation of class OrderAccess.

    34 

    35 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions

    36 static inline void compiler_barrier() {

    37   __asm__ volatile ("" : : : "memory");

    38 }

    39 

    40 inline void OrderAccess::loadload()   { compiler_barrier(); }

    41 inline void OrderAccess::storestore() { compiler_barrier(); }

    42 inline void OrderAccess::loadstore()  { compiler_barrier(); }

    43 inline void OrderAccess::storeload()  { fence();            }

    44 

    45 inline void OrderAccess::acquire()    { compiler_barrier(); }

    46 inline void OrderAccess::release()    { compiler_barrier(); }

    47 

    48 inline void OrderAccess::fence() {

    49    // always use locked addl since mfence is sometimes expensive

    50 #ifdef AMD64

    51   __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");

    52 #else

    53   __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");

    54 #endif

    55   compiler_barrier();

    56 }

    57 

    58 template<>

    59 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE>

    60 {

    61   template <typename T>

    62   void operator()(T v, volatile T* p) const {

    63     __asm__ volatile (  "xchgb (%2),%0"

    64                       : "=q" (v)

    65                       : "0" (v), "r" (p)

    66                       : "memory");

    67   }

    68 };

    69 

    70 template<>

    71 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE>

    72 {

    73   template <typename T>

    74   void operator()(T v, volatile T* p) const {

    75     __asm__ volatile (  "xchgw (%2),%0"

    76                       : "=r" (v)

    77                       : "0" (v), "r" (p)

    78                       : "memory");

    79   }

    80 };

    81 

    82 template<>

    83 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE>

    84 {

    85   template <typename T>

    86   void operator()(T v, volatile T* p) const {

    87     __asm__ volatile (  "xchgl (%2),%0"

    88                       : "=r" (v)

    89                       : "0" (v), "r" (p)

    90                       : "memory");

    91   }

    92 };

    93 

    94 #ifdef AMD64

    95 template<>

    96 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE>

    97 {

    98   template <typename T>

    99   void operator()(T v, volatile T* p) const {

   100     __asm__ volatile (  "xchgq (%2), %0"

   101                       : "=r" (v)

   102                       : "0" (v), "r" (p)

   103                       : "memory");

   104   }

   105 };

   106 #endif // AMD64

   107 

   108 #endif // OS_CPU_LINUX_X86_VM_ORDERACCESS_LINUX_X86_HPP