src/hotspot/os_cpu/linux_arm/orderAccess_linux_arm.inline.hpp
changeset 50429 83aec1d357d4
parent 50428 8c88df2e8a78
child 50430 6659a8f57d78
equal deleted inserted replaced
50428:8c88df2e8a78 50429:83aec1d357d4
     1 /*
       
     2  * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
       
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
       
     4  *
       
     5  * This code is free software; you can redistribute it and/or modify it
       
     6  * under the terms of the GNU General Public License version 2 only, as
       
     7  * published by the Free Software Foundation.
       
     8  *
       
     9  * This code is distributed in the hope that it will be useful, but WITHOUT
       
    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
       
    12  * version 2 for more details (a copy is included in the LICENSE file that
       
    13  * accompanied this code).
       
    14  *
       
    15  * You should have received a copy of the GNU General Public License version
       
    16  * 2 along with this work; if not, write to the Free Software Foundation,
       
    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
       
    18  *
       
    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
       
    20  * or visit www.oracle.com if you need additional information or have any
       
    21  * questions.
       
    22  *
       
    23  */
       
    24 
       
    25 #ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
       
    26 #define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP
       
    27 
       
    28 #include "runtime/orderAccess.hpp"
       
    29 #include "runtime/os.hpp"
       
    30 #include "vm_version_arm.hpp"
       
    31 
       
    32 // Implementation of class OrderAccess.
       
    33 // - we define the high level barriers below and use the general
       
    34 //   implementation in orderAccess.inline.hpp, with customizations
       
    35 //   on AARCH64 via the specialized_* template functions
       
    36 
       
    37 // Memory Ordering on ARM is weak.
       
    38 //
       
    39 // Implement all 4 memory ordering barriers by DMB, since it is a
       
    40 // lighter version of DSB.
       
    41 // dmb_sy implies full system shareability domain. RD/WR access type.
       
    42 // dmb_st implies full system shareability domain. WR only access type.
       
    43 //
       
    44 // NOP on < ARMv6 (MP not supported)
       
    45 //
       
    46 // Non mcr instructions can be used if we build for armv7 or higher arch
       
    47 //    __asm__ __volatile__ ("dmb" : : : "memory");
       
    48 //    __asm__ __volatile__ ("dsb" : : : "memory");
       
    49 //
       
    50 // inline void _OrderAccess_dsb() {
       
    51 //    volatile intptr_t dummy = 0;
       
    52 //    if (os::is_MP()) {
       
    53 //      __asm__ volatile (
       
    54 //        "mcr p15, 0, %0, c7, c10, 4"
       
    55 //        : : "r" (dummy) : "memory");
       
    56 //   }
       
    57 // }
       
    58 
       
    59 inline static void dmb_sy() {
       
    60    if (!os::is_MP()) {
       
    61      return;
       
    62    }
       
    63 #ifdef AARCH64
       
    64    __asm__ __volatile__ ("dmb sy" : : : "memory");
       
    65 #else
       
    66    if (VM_Version::arm_arch() >= 7) {
       
    67 #ifdef __thumb__
       
    68      __asm__ volatile (
       
    69      "dmb sy": : : "memory");
       
    70 #else
       
    71      __asm__ volatile (
       
    72      ".word 0xF57FF050 | 0xf" : : : "memory");
       
    73 #endif
       
    74    } else {
       
    75      intptr_t zero = 0;
       
    76      __asm__ volatile (
       
    77        "mcr p15, 0, %0, c7, c10, 5"
       
    78        : : "r" (zero) : "memory");
       
    79    }
       
    80 #endif
       
    81 }
       
    82 
       
    83 inline static void dmb_st() {
       
    84    if (!os::is_MP()) {
       
    85      return;
       
    86    }
       
    87 #ifdef AARCH64
       
    88    __asm__ __volatile__ ("dmb st" : : : "memory");
       
    89 #else
       
    90    if (VM_Version::arm_arch() >= 7) {
       
    91 #ifdef __thumb__
       
    92      __asm__ volatile (
       
    93      "dmb st": : : "memory");
       
    94 #else
       
    95      __asm__ volatile (
       
    96      ".word 0xF57FF050 | 0xe" : : : "memory");
       
    97 #endif
       
    98    } else {
       
    99      intptr_t zero = 0;
       
   100      __asm__ volatile (
       
   101        "mcr p15, 0, %0, c7, c10, 5"
       
   102        : : "r" (zero) : "memory");
       
   103    }
       
   104 #endif
       
   105 }
       
   106 
       
   107 // Load-Load/Store barrier
       
   108 inline static void dmb_ld() {
       
   109 #ifdef AARCH64
       
   110    if (!os::is_MP()) {
       
   111      return;
       
   112    }
       
   113    __asm__ __volatile__ ("dmb ld" : : : "memory");
       
   114 #else
       
   115    dmb_sy();
       
   116 #endif
       
   117 }
       
   118 
       
   119 
       
   120 inline void OrderAccess::loadload()   { dmb_ld(); }
       
   121 inline void OrderAccess::loadstore()  { dmb_ld(); }
       
   122 inline void OrderAccess::acquire()    { dmb_ld(); }
       
   123 inline void OrderAccess::storestore() { dmb_st(); }
       
   124 inline void OrderAccess::storeload()  { dmb_sy(); }
       
   125 inline void OrderAccess::release()    { dmb_sy(); }
       
   126 inline void OrderAccess::fence()      { dmb_sy(); }
       
   127 
       
   128 // specializations for Aarch64
       
   129 // TODO-AARCH64: evaluate effectiveness of ldar*/stlr* implementations compared to 32-bit ARM approach
       
   130 
       
   131 #ifdef AARCH64
       
   132 
       
   133 template<>
       
   134 struct OrderAccess::PlatformOrderedLoad<1, X_ACQUIRE>
       
   135 {
       
   136   template <typename T>
       
   137   T operator()(const volatile T* p) const {
       
   138     volatile T result;
       
   139     __asm__ volatile(
       
   140       "ldarb %w[res], [%[ptr]]"
       
   141       : [res] "=&r" (result)
       
   142       : [ptr] "r" (p)
       
   143       : "memory");
       
   144     return result;
       
   145   }
       
   146 };
       
   147 
       
   148 template<>
       
   149 struct OrderAccess::PlatformOrderedLoad<2, X_ACQUIRE>
       
   150 {
       
   151   template <typename T>
       
   152   T operator()(const volatile T* p) const {
       
   153     volatile T result;
       
   154     __asm__ volatile(
       
   155       "ldarh %w[res], [%[ptr]]"
       
   156       : [res] "=&r" (result)
       
   157       : [ptr] "r" (p)
       
   158       : "memory");
       
   159     return result;
       
   160   }
       
   161 };
       
   162 
       
   163 template<>
       
   164 struct OrderAccess::PlatformOrderedLoad<4, X_ACQUIRE>
       
   165 {
       
   166   template <typename T>
       
   167   T operator()(const volatile T* p) const {
       
   168     volatile T result;
       
   169     __asm__ volatile(
       
   170       "ldar %w[res], [%[ptr]]"
       
   171       : [res] "=&r" (result)
       
   172       : [ptr] "r" (p)
       
   173       : "memory");
       
   174     return result;
       
   175   }
       
   176 };
       
   177 
       
   178 template<>
       
   179 struct OrderAccess::PlatformOrderedLoad<8, X_ACQUIRE>
       
   180 {
       
   181   template <typename T>
       
   182   T operator()(const volatile T* p) const {
       
   183     volatile T result;
       
   184     __asm__ volatile(
       
   185       "ldar %[res], [%[ptr]]"
       
   186       : [res] "=&r" (result)
       
   187       : [ptr] "r" (p)
       
   188       : "memory");
       
   189     return result;
       
   190   }
       
   191 };
       
   192 
       
   193 template<>
       
   194 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE>
       
   195 {
       
   196   template <typename T>
       
   197   void operator()(T v, volatile T* p) const {
       
   198     __asm__ volatile(
       
   199       "stlrb %w[val], [%[ptr]]"
       
   200       :
       
   201       : [ptr] "r" (p), [val] "r" (v)
       
   202       : "memory");
       
   203   }
       
   204 };
       
   205 
       
   206 template<>
       
   207 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE>
       
   208 {
       
   209   template <typename T>
       
   210   void operator()(T v, volatile T* p) const {
       
   211     __asm__ volatile(
       
   212       "stlrh %w[val], [%[ptr]]"
       
   213       :
       
   214       : [ptr] "r" (p), [val] "r" (v)
       
   215       : "memory");
       
   216   }
       
   217 };
       
   218 
       
   219 template<>
       
   220 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE>
       
   221 {
       
   222   template <typename T>
       
   223   void operator()(T v, volatile T* p) const {
       
   224     __asm__ volatile(
       
   225       "stlr %w[val], [%[ptr]]"
       
   226       :
       
   227       : [ptr] "r" (p), [val] "r" (v)
       
   228       : "memory");
       
   229   }
       
   230 };
       
   231 
       
   232 template<>
       
   233 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE>
       
   234 {
       
   235   template <typename T>
       
   236   void operator()(T v, volatile T* p) const {
       
   237     __asm__ volatile(
       
   238       "stlr %[val], [%[ptr]]"
       
   239       :
       
   240       : [ptr] "r" (p), [val] "r" (v)
       
   241       : "memory");
       
   242   }
       
   243 };
       
   244 
       
   245 #endif // AARCH64
       
   246 
       
   247 #endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP