1 /* |
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2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP |
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26 #define OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP |
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27 |
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28 #include "runtime/orderAccess.hpp" |
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29 #include "runtime/os.hpp" |
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30 #include "vm_version_arm.hpp" |
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31 |
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32 // Implementation of class OrderAccess. |
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33 // - we define the high level barriers below and use the general |
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34 // implementation in orderAccess.inline.hpp, with customizations |
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35 // on AARCH64 via the specialized_* template functions |
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36 |
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37 // Memory Ordering on ARM is weak. |
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38 // |
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39 // Implement all 4 memory ordering barriers by DMB, since it is a |
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40 // lighter version of DSB. |
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41 // dmb_sy implies full system shareability domain. RD/WR access type. |
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42 // dmb_st implies full system shareability domain. WR only access type. |
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43 // |
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44 // NOP on < ARMv6 (MP not supported) |
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45 // |
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46 // Non mcr instructions can be used if we build for armv7 or higher arch |
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47 // __asm__ __volatile__ ("dmb" : : : "memory"); |
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48 // __asm__ __volatile__ ("dsb" : : : "memory"); |
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49 // |
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50 // inline void _OrderAccess_dsb() { |
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51 // volatile intptr_t dummy = 0; |
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52 // if (os::is_MP()) { |
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53 // __asm__ volatile ( |
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54 // "mcr p15, 0, %0, c7, c10, 4" |
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55 // : : "r" (dummy) : "memory"); |
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56 // } |
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57 // } |
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58 |
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59 inline static void dmb_sy() { |
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60 if (!os::is_MP()) { |
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61 return; |
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62 } |
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63 #ifdef AARCH64 |
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64 __asm__ __volatile__ ("dmb sy" : : : "memory"); |
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65 #else |
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66 if (VM_Version::arm_arch() >= 7) { |
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67 #ifdef __thumb__ |
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68 __asm__ volatile ( |
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69 "dmb sy": : : "memory"); |
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70 #else |
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71 __asm__ volatile ( |
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72 ".word 0xF57FF050 | 0xf" : : : "memory"); |
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73 #endif |
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74 } else { |
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75 intptr_t zero = 0; |
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76 __asm__ volatile ( |
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77 "mcr p15, 0, %0, c7, c10, 5" |
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78 : : "r" (zero) : "memory"); |
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79 } |
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80 #endif |
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81 } |
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82 |
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83 inline static void dmb_st() { |
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84 if (!os::is_MP()) { |
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85 return; |
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86 } |
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87 #ifdef AARCH64 |
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88 __asm__ __volatile__ ("dmb st" : : : "memory"); |
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89 #else |
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90 if (VM_Version::arm_arch() >= 7) { |
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91 #ifdef __thumb__ |
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92 __asm__ volatile ( |
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93 "dmb st": : : "memory"); |
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94 #else |
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95 __asm__ volatile ( |
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96 ".word 0xF57FF050 | 0xe" : : : "memory"); |
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97 #endif |
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98 } else { |
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99 intptr_t zero = 0; |
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100 __asm__ volatile ( |
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101 "mcr p15, 0, %0, c7, c10, 5" |
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102 : : "r" (zero) : "memory"); |
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103 } |
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104 #endif |
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105 } |
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106 |
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107 // Load-Load/Store barrier |
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108 inline static void dmb_ld() { |
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109 #ifdef AARCH64 |
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110 if (!os::is_MP()) { |
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111 return; |
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112 } |
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113 __asm__ __volatile__ ("dmb ld" : : : "memory"); |
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114 #else |
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115 dmb_sy(); |
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116 #endif |
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117 } |
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118 |
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119 |
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120 inline void OrderAccess::loadload() { dmb_ld(); } |
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121 inline void OrderAccess::loadstore() { dmb_ld(); } |
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122 inline void OrderAccess::acquire() { dmb_ld(); } |
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123 inline void OrderAccess::storestore() { dmb_st(); } |
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124 inline void OrderAccess::storeload() { dmb_sy(); } |
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125 inline void OrderAccess::release() { dmb_sy(); } |
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126 inline void OrderAccess::fence() { dmb_sy(); } |
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127 |
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128 // specializations for Aarch64 |
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129 // TODO-AARCH64: evaluate effectiveness of ldar*/stlr* implementations compared to 32-bit ARM approach |
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130 |
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131 #ifdef AARCH64 |
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132 |
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133 template<> |
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134 struct OrderAccess::PlatformOrderedLoad<1, X_ACQUIRE> |
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135 { |
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136 template <typename T> |
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137 T operator()(const volatile T* p) const { |
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138 volatile T result; |
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139 __asm__ volatile( |
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140 "ldarb %w[res], [%[ptr]]" |
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141 : [res] "=&r" (result) |
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142 : [ptr] "r" (p) |
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143 : "memory"); |
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144 return result; |
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145 } |
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146 }; |
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147 |
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148 template<> |
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149 struct OrderAccess::PlatformOrderedLoad<2, X_ACQUIRE> |
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150 { |
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151 template <typename T> |
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152 T operator()(const volatile T* p) const { |
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153 volatile T result; |
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154 __asm__ volatile( |
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155 "ldarh %w[res], [%[ptr]]" |
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156 : [res] "=&r" (result) |
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157 : [ptr] "r" (p) |
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158 : "memory"); |
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159 return result; |
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160 } |
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161 }; |
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162 |
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163 template<> |
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164 struct OrderAccess::PlatformOrderedLoad<4, X_ACQUIRE> |
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165 { |
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166 template <typename T> |
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167 T operator()(const volatile T* p) const { |
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168 volatile T result; |
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169 __asm__ volatile( |
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170 "ldar %w[res], [%[ptr]]" |
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171 : [res] "=&r" (result) |
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172 : [ptr] "r" (p) |
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173 : "memory"); |
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174 return result; |
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175 } |
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176 }; |
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177 |
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178 template<> |
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179 struct OrderAccess::PlatformOrderedLoad<8, X_ACQUIRE> |
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180 { |
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181 template <typename T> |
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182 T operator()(const volatile T* p) const { |
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183 volatile T result; |
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184 __asm__ volatile( |
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185 "ldar %[res], [%[ptr]]" |
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186 : [res] "=&r" (result) |
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187 : [ptr] "r" (p) |
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188 : "memory"); |
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189 return result; |
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190 } |
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191 }; |
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192 |
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193 template<> |
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194 struct OrderAccess::PlatformOrderedStore<1, RELEASE_X_FENCE> |
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195 { |
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196 template <typename T> |
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197 void operator()(T v, volatile T* p) const { |
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198 __asm__ volatile( |
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199 "stlrb %w[val], [%[ptr]]" |
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200 : |
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201 : [ptr] "r" (p), [val] "r" (v) |
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202 : "memory"); |
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203 } |
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204 }; |
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205 |
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206 template<> |
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207 struct OrderAccess::PlatformOrderedStore<2, RELEASE_X_FENCE> |
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208 { |
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209 template <typename T> |
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210 void operator()(T v, volatile T* p) const { |
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211 __asm__ volatile( |
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212 "stlrh %w[val], [%[ptr]]" |
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213 : |
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214 : [ptr] "r" (p), [val] "r" (v) |
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215 : "memory"); |
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216 } |
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217 }; |
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218 |
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219 template<> |
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220 struct OrderAccess::PlatformOrderedStore<4, RELEASE_X_FENCE> |
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221 { |
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222 template <typename T> |
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223 void operator()(T v, volatile T* p) const { |
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224 __asm__ volatile( |
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225 "stlr %w[val], [%[ptr]]" |
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226 : |
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227 : [ptr] "r" (p), [val] "r" (v) |
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228 : "memory"); |
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229 } |
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230 }; |
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231 |
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232 template<> |
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233 struct OrderAccess::PlatformOrderedStore<8, RELEASE_X_FENCE> |
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234 { |
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235 template <typename T> |
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236 void operator()(T v, volatile T* p) const { |
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237 __asm__ volatile( |
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238 "stlr %[val], [%[ptr]]" |
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239 : |
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240 : [ptr] "r" (p), [val] "r" (v) |
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241 : "memory"); |
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242 } |
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243 }; |
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244 |
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245 #endif // AARCH64 |
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246 |
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247 #endif // OS_CPU_LINUX_ARM_VM_ORDERACCESS_LINUX_ARM_INLINE_HPP |
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