equal
deleted
inserted
replaced
23 */ |
23 */ |
24 |
24 |
25 #ifndef SHARE_VM_C1_C1_LIR_HPP |
25 #ifndef SHARE_VM_C1_C1_LIR_HPP |
26 #define SHARE_VM_C1_C1_LIR_HPP |
26 #define SHARE_VM_C1_C1_LIR_HPP |
27 |
27 |
|
28 #include "c1/c1_Defs.hpp" |
28 #include "c1/c1_ValueType.hpp" |
29 #include "c1/c1_ValueType.hpp" |
29 #include "oops/method.hpp" |
30 #include "oops/method.hpp" |
30 |
31 |
31 class BlockBegin; |
32 class BlockBegin; |
32 class BlockList; |
33 class BlockList; |
559 |
560 |
560 virtual LIR_Address* as_address() { return this; } |
561 virtual LIR_Address* as_address() { return this; } |
561 virtual BasicType type() const { return _type; } |
562 virtual BasicType type() const { return _type; } |
562 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN; |
563 virtual void print_value_on(outputStream* out) const PRODUCT_RETURN; |
563 |
564 |
564 void verify() const PRODUCT_RETURN; |
565 void verify0() const PRODUCT_RETURN; |
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566 #if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT) |
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567 void pd_verify() const; |
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568 void verify() const { pd_verify(); } |
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569 #else |
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570 void verify() const { verify0(); } |
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571 #endif |
565 |
572 |
566 static Scale scale(BasicType type); |
573 static Scale scale(BasicType type); |
567 }; |
574 }; |
568 |
575 |
569 |
576 |
608 |
615 |
609 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
616 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | |
610 LIR_OprDesc::float_type | |
617 LIR_OprDesc::float_type | |
611 LIR_OprDesc::fpu_register | |
618 LIR_OprDesc::fpu_register | |
612 LIR_OprDesc::single_size); } |
619 LIR_OprDesc::single_size); } |
613 #if defined(ARM) |
620 #if defined(ARM32) |
614 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } |
621 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } |
615 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); } |
622 static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); } |
616 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); } |
623 static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); } |
617 #endif |
624 #endif |
618 #ifdef SPARC |
625 #ifdef SPARC |