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288 // appears mostly impossible on Intel to simply invalidate other |
288 // appears mostly impossible on Intel to simply invalidate other |
289 // processors caches and since they may do aggressive prefetch it's |
289 // processors caches and since they may do aggressive prefetch it's |
290 // very hard to make a guess about what code might be in the icache. |
290 // very hard to make a guess about what code might be in the icache. |
291 // Force the instruction to be double word aligned so that it |
291 // Force the instruction to be double word aligned so that it |
292 // doesn't span a cache line. |
292 // doesn't span a cache line. |
293 masm->align(round_to(NativeGeneralJump::instruction_size, wordSize)); |
293 masm->align(align_up((int)NativeGeneralJump::instruction_size, wordSize)); |
294 } |
294 } |
295 |
295 |
296 void PatchingStub::emit_code(LIR_Assembler* ce) { |
296 void PatchingStub::emit_code(LIR_Assembler* ce) { |
297 assert(NativeCall::instruction_size <= _bytes_to_copy && _bytes_to_copy <= 0xFF, "not enough room for call"); |
297 assert(NativeCall::instruction_size <= _bytes_to_copy && _bytes_to_copy <= 0xFF, "not enough room for call"); |
298 |
298 |