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1 /* |
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2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_X86_VM_C1_DEFS_X86_HPP |
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26 #define CPU_X86_VM_C1_DEFS_X86_HPP |
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27 |
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28 // native word offsets from memory address (little endian) |
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29 enum { |
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30 pd_lo_word_offset_in_bytes = 0, |
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31 pd_hi_word_offset_in_bytes = BytesPerWord |
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32 }; |
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33 |
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34 // explicit rounding operations are required to implement the strictFP mode |
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35 enum { |
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36 pd_strict_fp_requires_explicit_rounding = true |
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37 }; |
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38 |
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39 |
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40 // registers |
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41 enum { |
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42 pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission |
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43 pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission |
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44 pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission |
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45 |
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46 #ifdef _LP64 |
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47 #define UNALLOCATED 4 // rsp, rbp, r15, r10 |
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48 #else |
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49 #define UNALLOCATED 2 // rsp, rbp |
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50 #endif // LP64 |
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51 |
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52 pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls |
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53 pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls |
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54 pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls |
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55 |
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56 pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator |
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57 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator |
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58 |
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59 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan |
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60 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan |
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61 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan |
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62 pd_first_cpu_reg = 0, |
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63 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11), |
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64 pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0), |
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65 pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11), |
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66 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, |
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67 pd_last_fpu_reg = pd_first_fpu_reg + 7, |
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68 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, |
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69 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1 |
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70 }; |
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71 |
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72 |
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73 // encoding of float value in debug info: |
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74 enum { |
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75 pd_float_saved_as_double = true |
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76 }; |
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77 |
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78 #endif // CPU_X86_VM_C1_DEFS_X86_HPP |