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1 /* |
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2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP |
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26 #define CPU_SPARC_VM_REGISTER_SPARC_HPP |
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27 |
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28 #include "asm/register.hpp" |
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29 |
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30 // forward declaration |
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31 class Address; |
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32 class VMRegImpl; |
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33 typedef VMRegImpl* VMReg; |
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34 |
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35 |
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36 // Use Register as shortcut |
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37 class RegisterImpl; |
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38 typedef RegisterImpl* Register; |
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39 |
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40 |
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41 inline Register as_Register(int encoding) { |
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42 return (Register)(intptr_t) encoding; |
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43 } |
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44 |
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45 // The implementation of integer registers for the SPARC architecture |
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46 class RegisterImpl: public AbstractRegisterImpl { |
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47 public: |
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48 enum { |
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49 log_set_size = 3, // the number of bits to encode the set register number |
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50 number_of_sets = 4, // the number of registers sets (in, local, out, global) |
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51 number_of_registers = number_of_sets << log_set_size, |
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52 |
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53 iset_no = 3, ibase = iset_no << log_set_size, // the in register set |
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54 lset_no = 2, lbase = lset_no << log_set_size, // the local register set |
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55 oset_no = 1, obase = oset_no << log_set_size, // the output register set |
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56 gset_no = 0, gbase = gset_no << log_set_size // the global register set |
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57 }; |
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58 |
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59 |
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60 friend Register as_Register(int encoding); |
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61 // set specific construction |
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62 friend Register as_iRegister(int number); |
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63 friend Register as_lRegister(int number); |
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64 friend Register as_oRegister(int number); |
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65 friend Register as_gRegister(int number); |
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66 |
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67 inline VMReg as_VMReg(); |
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68 |
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69 // accessors |
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70 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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71 const char* name() const; |
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72 |
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73 // testers |
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74 bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); } |
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75 bool is_even() const { return (encoding() & 1) == 0; } |
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76 bool is_in() const { return (encoding() >> log_set_size) == iset_no; } |
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77 bool is_local() const { return (encoding() >> log_set_size) == lset_no; } |
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78 bool is_out() const { return (encoding() >> log_set_size) == oset_no; } |
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79 bool is_global() const { return (encoding() >> log_set_size) == gset_no; } |
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80 |
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81 // derived registers, offsets, and addresses |
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82 Register successor() const { return as_Register(encoding() + 1); } |
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83 |
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84 int input_number() const { |
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85 assert(is_in(), "must be input register"); |
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86 return encoding() - ibase; |
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87 } |
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88 |
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89 Register after_save() const { |
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90 assert(is_out() || is_global(), "register not visible after save"); |
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91 return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this; |
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92 } |
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93 |
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94 Register after_restore() const { |
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95 assert(is_in() || is_global(), "register not visible after restore"); |
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96 return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this; |
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97 } |
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98 |
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99 int sp_offset_in_saved_window() const { |
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100 assert(is_in() || is_local(), "only i and l registers are saved in frame"); |
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101 return encoding() - lbase; |
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102 } |
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103 |
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104 inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp |
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105 }; |
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106 |
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107 |
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108 // set specific construction |
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109 inline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); } |
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110 inline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); } |
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111 inline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); } |
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112 inline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); } |
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113 |
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114 // The integer registers of the SPARC architecture |
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115 |
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116 CONSTANT_REGISTER_DECLARATION(Register, noreg , (-1)); |
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117 |
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118 CONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0)); |
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119 CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1)); |
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120 CONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2)); |
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121 CONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3)); |
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122 CONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4)); |
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123 CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5)); |
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124 CONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6)); |
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125 CONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7)); |
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126 |
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127 CONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0)); |
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128 CONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1)); |
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129 CONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2)); |
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130 CONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3)); |
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131 CONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4)); |
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132 CONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5)); |
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133 CONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6)); |
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134 CONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7)); |
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135 |
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136 CONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0)); |
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137 CONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1)); |
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138 CONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2)); |
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139 CONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3)); |
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140 CONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4)); |
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141 CONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5)); |
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142 CONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6)); |
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143 CONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7)); |
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144 |
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145 CONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0)); |
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146 CONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1)); |
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147 CONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2)); |
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148 CONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3)); |
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149 CONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4)); |
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150 CONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5)); |
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151 CONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6)); |
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152 CONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7)); |
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153 |
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154 CONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6)); |
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155 CONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6)); |
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156 |
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157 // |
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158 // Because sparc has so many registers, #define'ing values for the is |
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159 // beneficial in code size and the cost of some of the dangers of |
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160 // defines. We don't use them on Intel because win32 uses asm |
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161 // directives which use the same names for registers as Hotspot does, |
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162 // so #defines would screw up the inline assembly. If a particular |
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163 // file has a problem with these defines then it's possible to turn |
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164 // them off in that file by defining DONT_USE_REGISTER_DEFINES. |
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165 // register_definition_sparc.cpp does that so that it's able to |
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166 // provide real definitions of these registers for use in debuggers |
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167 // and such. |
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168 // |
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169 |
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170 #ifndef DONT_USE_REGISTER_DEFINES |
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171 #define noreg ((Register)(noreg_RegisterEnumValue)) |
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172 |
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173 #define G0 ((Register)(G0_RegisterEnumValue)) |
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174 #define G1 ((Register)(G1_RegisterEnumValue)) |
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175 #define G2 ((Register)(G2_RegisterEnumValue)) |
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176 #define G3 ((Register)(G3_RegisterEnumValue)) |
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177 #define G4 ((Register)(G4_RegisterEnumValue)) |
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178 #define G5 ((Register)(G5_RegisterEnumValue)) |
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179 #define G6 ((Register)(G6_RegisterEnumValue)) |
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180 #define G7 ((Register)(G7_RegisterEnumValue)) |
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181 |
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182 #define O0 ((Register)(O0_RegisterEnumValue)) |
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183 #define O1 ((Register)(O1_RegisterEnumValue)) |
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184 #define O2 ((Register)(O2_RegisterEnumValue)) |
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185 #define O3 ((Register)(O3_RegisterEnumValue)) |
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186 #define O4 ((Register)(O4_RegisterEnumValue)) |
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187 #define O5 ((Register)(O5_RegisterEnumValue)) |
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188 #define O6 ((Register)(O6_RegisterEnumValue)) |
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189 #define O7 ((Register)(O7_RegisterEnumValue)) |
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190 |
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191 #define L0 ((Register)(L0_RegisterEnumValue)) |
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192 #define L1 ((Register)(L1_RegisterEnumValue)) |
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193 #define L2 ((Register)(L2_RegisterEnumValue)) |
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194 #define L3 ((Register)(L3_RegisterEnumValue)) |
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195 #define L4 ((Register)(L4_RegisterEnumValue)) |
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196 #define L5 ((Register)(L5_RegisterEnumValue)) |
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197 #define L6 ((Register)(L6_RegisterEnumValue)) |
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198 #define L7 ((Register)(L7_RegisterEnumValue)) |
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199 |
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200 #define I0 ((Register)(I0_RegisterEnumValue)) |
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201 #define I1 ((Register)(I1_RegisterEnumValue)) |
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202 #define I2 ((Register)(I2_RegisterEnumValue)) |
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203 #define I3 ((Register)(I3_RegisterEnumValue)) |
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204 #define I4 ((Register)(I4_RegisterEnumValue)) |
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205 #define I5 ((Register)(I5_RegisterEnumValue)) |
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206 #define I6 ((Register)(I6_RegisterEnumValue)) |
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207 #define I7 ((Register)(I7_RegisterEnumValue)) |
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208 |
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209 #define FP ((Register)(FP_RegisterEnumValue)) |
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210 #define SP ((Register)(SP_RegisterEnumValue)) |
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211 #endif // DONT_USE_REGISTER_DEFINES |
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212 |
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213 // Use FloatRegister as shortcut |
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214 class FloatRegisterImpl; |
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215 typedef FloatRegisterImpl* FloatRegister; |
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216 |
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217 |
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218 // construction |
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219 inline FloatRegister as_FloatRegister(int encoding) { |
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220 return (FloatRegister)(intptr_t)encoding; |
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221 } |
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222 |
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223 // The implementation of float registers for the SPARC architecture |
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224 |
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225 class FloatRegisterImpl: public AbstractRegisterImpl { |
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226 public: |
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227 enum { |
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228 number_of_registers = 64 |
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229 }; |
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230 |
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231 enum Width { |
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232 S = 1, D = 2, Q = 3 |
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233 }; |
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234 |
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235 // construction |
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236 inline VMReg as_VMReg( ); |
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237 |
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238 // accessors |
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239 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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240 |
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241 public: |
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242 int encoding(Width w) const { |
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243 const int c = encoding(); |
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244 switch (w) { |
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245 case S: |
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246 assert(c < 32, "bad single float register"); |
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247 return c; |
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248 |
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249 case D: |
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250 assert(c < 64 && (c & 1) == 0, "bad double float register"); |
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251 return (c & 0x1e) | ((c & 0x20) >> 5); |
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252 |
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253 case Q: |
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254 assert(c < 64 && (c & 3) == 0, "bad quad float register"); |
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255 return (c & 0x1c) | ((c & 0x20) >> 5); |
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256 } |
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257 ShouldNotReachHere(); |
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258 return -1; |
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259 } |
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260 |
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261 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } |
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262 const char* name() const; |
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263 |
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264 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } |
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265 }; |
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266 |
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267 |
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268 // The float registers of the SPARC architecture |
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269 |
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270 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1)); |
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271 |
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272 CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0)); |
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273 CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1)); |
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274 CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2)); |
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275 CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3)); |
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276 CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4)); |
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277 CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5)); |
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278 CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6)); |
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279 CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7)); |
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280 CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8)); |
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281 CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9)); |
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282 CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10)); |
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283 CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11)); |
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284 CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12)); |
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285 CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13)); |
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286 CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14)); |
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287 CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15)); |
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288 CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16)); |
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289 CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17)); |
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290 CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18)); |
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291 CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19)); |
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292 CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20)); |
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293 CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21)); |
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294 CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22)); |
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295 CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23)); |
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296 CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24)); |
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297 CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25)); |
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298 CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26)); |
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299 CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27)); |
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300 CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28)); |
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301 CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29)); |
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302 CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30)); |
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303 CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31)); |
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304 |
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305 CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32)); |
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306 CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34)); |
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307 CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36)); |
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308 CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38)); |
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309 CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40)); |
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310 CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42)); |
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311 CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44)); |
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312 CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46)); |
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313 CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48)); |
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314 CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50)); |
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315 CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52)); |
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316 CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54)); |
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317 CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56)); |
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318 CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58)); |
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319 CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60)); |
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320 CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62)); |
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321 |
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322 |
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323 #ifndef DONT_USE_REGISTER_DEFINES |
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324 #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue)) |
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325 #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue)) |
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326 #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue)) |
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327 #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue)) |
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328 #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue)) |
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329 #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue)) |
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330 #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue)) |
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331 #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue)) |
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332 #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue)) |
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333 #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue)) |
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334 #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue)) |
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335 #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue)) |
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336 #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue)) |
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337 #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue)) |
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338 #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue)) |
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339 #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue)) |
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340 #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue)) |
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341 #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue)) |
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342 #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue)) |
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343 #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue)) |
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344 #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue)) |
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345 #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue)) |
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346 #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue)) |
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347 #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue)) |
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348 #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue)) |
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349 #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue)) |
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350 #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue)) |
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351 #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue)) |
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352 #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue)) |
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353 #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue)) |
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354 #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue)) |
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355 #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue)) |
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356 #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue)) |
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357 #define F32 ((FloatRegister)( F32_FloatRegisterEnumValue)) |
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358 #define F34 ((FloatRegister)( F34_FloatRegisterEnumValue)) |
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359 #define F36 ((FloatRegister)( F36_FloatRegisterEnumValue)) |
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360 #define F38 ((FloatRegister)( F38_FloatRegisterEnumValue)) |
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361 #define F40 ((FloatRegister)( F40_FloatRegisterEnumValue)) |
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362 #define F42 ((FloatRegister)( F42_FloatRegisterEnumValue)) |
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363 #define F44 ((FloatRegister)( F44_FloatRegisterEnumValue)) |
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364 #define F46 ((FloatRegister)( F46_FloatRegisterEnumValue)) |
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365 #define F48 ((FloatRegister)( F48_FloatRegisterEnumValue)) |
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366 #define F50 ((FloatRegister)( F50_FloatRegisterEnumValue)) |
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367 #define F52 ((FloatRegister)( F52_FloatRegisterEnumValue)) |
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368 #define F54 ((FloatRegister)( F54_FloatRegisterEnumValue)) |
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369 #define F56 ((FloatRegister)( F56_FloatRegisterEnumValue)) |
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370 #define F58 ((FloatRegister)( F58_FloatRegisterEnumValue)) |
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371 #define F60 ((FloatRegister)( F60_FloatRegisterEnumValue)) |
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372 #define F62 ((FloatRegister)( F62_FloatRegisterEnumValue)) |
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373 #endif // DONT_USE_REGISTER_DEFINES |
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374 |
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375 // Maximum number of incoming arguments that can be passed in i registers. |
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376 const int SPARC_ARGS_IN_REGS_NUM = 6; |
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377 |
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378 class ConcreteRegisterImpl : public AbstractRegisterImpl { |
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379 public: |
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380 enum { |
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381 // This number must be large enough to cover REG_COUNT (defined by c2) registers. |
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382 // There is no requirement that any ordering here matches any ordering c2 gives |
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383 // it's optoregs. |
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384 number_of_registers = 2*RegisterImpl::number_of_registers + |
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385 FloatRegisterImpl::number_of_registers + |
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386 1 + // ccr |
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387 4 // fcc |
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388 }; |
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389 static const int max_gpr; |
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390 static const int max_fpr; |
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391 |
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392 }; |
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393 |
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394 // Single, Double and Quad fp reg classes. These exist to map the ADLC |
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395 // encoding for a floating point register, to the FloatRegister number |
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396 // desired by the macroassembler. A FloatRegister is a number between |
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397 // 0 and 63 passed around as a pointer. For ADLC, an fp register encoding |
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398 // is the actual bit encoding used by the sparc hardware. When ADLC used |
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399 // the macroassembler to generate an instruction that references, e.g., a |
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400 // double fp reg, it passed the bit encoding to the macroassembler via |
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401 // as_FloatRegister, which, for double regs > 30, returns an illegal |
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402 // register number. |
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403 // |
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404 // Therefore we provide the following classes for use by ADLC. Their |
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405 // sole purpose is to convert from sparc register encodings to FloatRegisters. |
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406 // At some future time, we might replace FloatRegister with these classes, |
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407 // hence the definitions of as_xxxFloatRegister as class methods rather |
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408 // than as external inline routines. |
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409 |
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410 class SingleFloatRegisterImpl; |
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411 typedef SingleFloatRegisterImpl *SingleFloatRegister; |
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412 |
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413 inline FloatRegister as_SingleFloatRegister(int encoding); |
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414 class SingleFloatRegisterImpl { |
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415 public: |
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416 friend inline FloatRegister as_SingleFloatRegister(int encoding) { |
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417 assert(encoding < 32, "bad single float register encoding"); |
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418 return as_FloatRegister(encoding); |
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419 } |
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420 }; |
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421 |
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422 |
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423 class DoubleFloatRegisterImpl; |
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424 typedef DoubleFloatRegisterImpl *DoubleFloatRegister; |
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425 |
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426 inline FloatRegister as_DoubleFloatRegister(int encoding); |
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427 class DoubleFloatRegisterImpl { |
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428 public: |
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429 friend inline FloatRegister as_DoubleFloatRegister(int encoding) { |
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430 assert(encoding < 32, "bad double float register encoding"); |
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431 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) ); |
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432 } |
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433 }; |
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434 |
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435 |
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436 class QuadFloatRegisterImpl; |
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437 typedef QuadFloatRegisterImpl *QuadFloatRegister; |
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438 |
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439 class QuadFloatRegisterImpl { |
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440 public: |
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441 friend FloatRegister as_QuadFloatRegister(int encoding) { |
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442 assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding"); |
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443 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) ); |
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444 } |
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445 }; |
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446 |
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447 #endif // CPU_SPARC_VM_REGISTER_SPARC_HPP |