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1 /* |
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2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 * |
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23 */ |
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24 |
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25 #ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP |
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26 #define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP |
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27 |
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28 private: |
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29 |
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30 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
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31 // |
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32 // Sparc load/store emission |
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33 // |
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34 // The sparc ld/st instructions cannot accomodate displacements > 13 bits long. |
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35 // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode |
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36 // by allowing 32 bit displacements: |
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37 // |
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38 // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]). |
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39 // When disp > 13 bits long, code is emitted to set the displacement into the O7 register, |
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40 // and then a load or store is emitted with ([O7] + [d]). |
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41 // |
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42 |
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43 int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned); |
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44 int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide); |
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45 |
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46 int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned); |
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47 int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide); |
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48 |
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49 void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no); |
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50 |
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51 int shift_amount(BasicType t); |
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52 |
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53 static bool is_single_instruction(LIR_Op* op); |
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54 |
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55 // Record the type of the receiver in ReceiverTypeData |
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56 void type_profile_helper(Register mdo, int mdo_offset_bias, |
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57 ciMethodData *md, ciProfileData *data, |
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58 Register recv, Register tmp1, Label* update_done); |
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59 // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot. |
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60 void setup_md_access(ciMethod* method, int bci, |
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61 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias); |
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62 |
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63 enum { |
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64 _call_stub_size = 68, |
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65 _call_aot_stub_size = 0, |
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66 _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(128), |
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67 _deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(64) |
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68 }; |
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69 |
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70 public: |
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71 void pack64(LIR_Opr src, LIR_Opr dst); |
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72 void unpack64(LIR_Opr src, LIR_Opr dst); |
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73 |
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74 #endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP |