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1 /* |
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2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright (c) 2012, 2017 SAP SE. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #ifndef CPU_PPC_VM_REGISTER_PPC_HPP |
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27 #define CPU_PPC_VM_REGISTER_PPC_HPP |
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28 |
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29 #include "asm/register.hpp" |
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30 |
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31 // forward declaration |
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32 class Address; |
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33 class VMRegImpl; |
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34 typedef VMRegImpl* VMReg; |
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35 |
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36 // PPC64 registers |
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37 // |
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38 // See "64-bit PowerPC ELF ABI Supplement 1.7", IBM Corp. (2003-10-29). |
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39 // (http://math-atlas.sourceforge.net/devel/assembly/PPC-elf64abi-1.7.pdf) |
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40 // |
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41 // r0 Register used in function prologs (volatile) |
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42 // r1 Stack pointer (nonvolatile) |
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43 // r2 TOC pointer (volatile) |
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44 // r3 Parameter and return value (volatile) |
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45 // r4-r10 Function parameters (volatile) |
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46 // r11 Register used in calls by pointer and as an environment pointer for languages which require one (volatile) |
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47 // r12 Register used for exception handling and glink code (volatile) |
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48 // r13 Reserved for use as system thread ID |
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49 // r14-r31 Local variables (nonvolatile) |
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50 // |
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51 // f0 Scratch register (volatile) |
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52 // f1-f4 Floating point parameters and return value (volatile) |
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53 // f5-f13 Floating point parameters (volatile) |
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54 // f14-f31 Floating point values (nonvolatile) |
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55 // |
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56 // LR Link register for return address (volatile) |
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57 // CTR Loop counter (volatile) |
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58 // XER Fixed point exception register (volatile) |
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59 // FPSCR Floating point status and control register (volatile) |
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60 // |
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61 // CR0-CR1 Condition code fields (volatile) |
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62 // CR2-CR4 Condition code fields (nonvolatile) |
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63 // CR5-CR7 Condition code fields (volatile) |
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64 // |
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65 // ---------------------------------------------- |
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66 // On processors with the VMX feature: |
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67 // v0-v1 Volatile scratch registers |
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68 // v2-v13 Volatile vector parameters registers |
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69 // v14-v19 Volatile scratch registers |
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70 // v20-v31 Non-volatile registers |
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71 // vrsave Non-volatile 32-bit register |
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72 |
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73 |
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74 // Use Register as shortcut |
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75 class RegisterImpl; |
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76 typedef RegisterImpl* Register; |
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77 |
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78 inline Register as_Register(int encoding) { |
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79 assert(encoding >= -1 && encoding < 32, "bad register encoding"); |
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80 return (Register)(intptr_t)encoding; |
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81 } |
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82 |
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83 // The implementation of integer registers for the Power architecture |
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84 class RegisterImpl: public AbstractRegisterImpl { |
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85 public: |
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86 enum { |
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87 number_of_registers = 32 |
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88 }; |
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89 |
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90 // general construction |
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91 inline friend Register as_Register(int encoding); |
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92 |
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93 // accessors |
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94 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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95 inline VMReg as_VMReg(); |
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96 Register successor() const { return as_Register(encoding() + 1); } |
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97 |
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98 // testers |
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99 bool is_valid() const { return ( 0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); } |
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100 bool is_volatile() const { return ( 0 <= (value()&0x7F) && (value()&0x7F) <= 13 ); } |
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101 bool is_nonvolatile() const { return (14 <= (value()&0x7F) && (value()&0x7F) <= 31 ); } |
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102 |
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103 const char* name() const; |
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104 }; |
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105 |
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106 // The integer registers of the PPC architecture |
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107 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); |
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108 |
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109 CONSTANT_REGISTER_DECLARATION(Register, R0, (0)); |
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110 CONSTANT_REGISTER_DECLARATION(Register, R1, (1)); |
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111 CONSTANT_REGISTER_DECLARATION(Register, R2, (2)); |
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112 CONSTANT_REGISTER_DECLARATION(Register, R3, (3)); |
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113 CONSTANT_REGISTER_DECLARATION(Register, R4, (4)); |
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114 CONSTANT_REGISTER_DECLARATION(Register, R5, (5)); |
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115 CONSTANT_REGISTER_DECLARATION(Register, R6, (6)); |
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116 CONSTANT_REGISTER_DECLARATION(Register, R7, (7)); |
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117 CONSTANT_REGISTER_DECLARATION(Register, R8, (8)); |
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118 CONSTANT_REGISTER_DECLARATION(Register, R9, (9)); |
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119 CONSTANT_REGISTER_DECLARATION(Register, R10, (10)); |
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120 CONSTANT_REGISTER_DECLARATION(Register, R11, (11)); |
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121 CONSTANT_REGISTER_DECLARATION(Register, R12, (12)); |
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122 CONSTANT_REGISTER_DECLARATION(Register, R13, (13)); |
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123 CONSTANT_REGISTER_DECLARATION(Register, R14, (14)); |
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124 CONSTANT_REGISTER_DECLARATION(Register, R15, (15)); |
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125 CONSTANT_REGISTER_DECLARATION(Register, R16, (16)); |
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126 CONSTANT_REGISTER_DECLARATION(Register, R17, (17)); |
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127 CONSTANT_REGISTER_DECLARATION(Register, R18, (18)); |
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128 CONSTANT_REGISTER_DECLARATION(Register, R19, (19)); |
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129 CONSTANT_REGISTER_DECLARATION(Register, R20, (20)); |
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130 CONSTANT_REGISTER_DECLARATION(Register, R21, (21)); |
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131 CONSTANT_REGISTER_DECLARATION(Register, R22, (22)); |
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132 CONSTANT_REGISTER_DECLARATION(Register, R23, (23)); |
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133 CONSTANT_REGISTER_DECLARATION(Register, R24, (24)); |
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134 CONSTANT_REGISTER_DECLARATION(Register, R25, (25)); |
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135 CONSTANT_REGISTER_DECLARATION(Register, R26, (26)); |
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136 CONSTANT_REGISTER_DECLARATION(Register, R27, (27)); |
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137 CONSTANT_REGISTER_DECLARATION(Register, R28, (28)); |
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138 CONSTANT_REGISTER_DECLARATION(Register, R29, (29)); |
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139 CONSTANT_REGISTER_DECLARATION(Register, R30, (30)); |
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140 CONSTANT_REGISTER_DECLARATION(Register, R31, (31)); |
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141 |
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142 |
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143 // |
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144 // Because Power has many registers, #define'ing values for them is |
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145 // beneficial in code size and is worth the cost of some of the |
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146 // dangers of defines. If a particular file has a problem with these |
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147 // defines then it's possible to turn them off in that file by |
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148 // defining DONT_USE_REGISTER_DEFINES. Register_definition_ppc.cpp |
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149 // does that so that it's able to provide real definitions of these |
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150 // registers for use in debuggers and such. |
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151 // |
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152 |
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153 #ifndef DONT_USE_REGISTER_DEFINES |
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154 #define noreg ((Register)(noreg_RegisterEnumValue)) |
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155 |
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156 #define R0 ((Register)(R0_RegisterEnumValue)) |
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157 #define R1 ((Register)(R1_RegisterEnumValue)) |
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158 #define R2 ((Register)(R2_RegisterEnumValue)) |
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159 #define R3 ((Register)(R3_RegisterEnumValue)) |
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160 #define R4 ((Register)(R4_RegisterEnumValue)) |
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161 #define R5 ((Register)(R5_RegisterEnumValue)) |
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162 #define R6 ((Register)(R6_RegisterEnumValue)) |
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163 #define R7 ((Register)(R7_RegisterEnumValue)) |
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164 #define R8 ((Register)(R8_RegisterEnumValue)) |
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165 #define R9 ((Register)(R9_RegisterEnumValue)) |
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166 #define R10 ((Register)(R10_RegisterEnumValue)) |
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167 #define R11 ((Register)(R11_RegisterEnumValue)) |
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168 #define R12 ((Register)(R12_RegisterEnumValue)) |
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169 #define R13 ((Register)(R13_RegisterEnumValue)) |
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170 #define R14 ((Register)(R14_RegisterEnumValue)) |
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171 #define R15 ((Register)(R15_RegisterEnumValue)) |
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172 #define R16 ((Register)(R16_RegisterEnumValue)) |
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173 #define R17 ((Register)(R17_RegisterEnumValue)) |
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174 #define R18 ((Register)(R18_RegisterEnumValue)) |
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175 #define R19 ((Register)(R19_RegisterEnumValue)) |
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176 #define R20 ((Register)(R20_RegisterEnumValue)) |
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177 #define R21 ((Register)(R21_RegisterEnumValue)) |
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178 #define R22 ((Register)(R22_RegisterEnumValue)) |
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179 #define R23 ((Register)(R23_RegisterEnumValue)) |
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180 #define R24 ((Register)(R24_RegisterEnumValue)) |
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181 #define R25 ((Register)(R25_RegisterEnumValue)) |
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182 #define R26 ((Register)(R26_RegisterEnumValue)) |
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183 #define R27 ((Register)(R27_RegisterEnumValue)) |
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184 #define R28 ((Register)(R28_RegisterEnumValue)) |
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185 #define R29 ((Register)(R29_RegisterEnumValue)) |
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186 #define R30 ((Register)(R30_RegisterEnumValue)) |
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187 #define R31 ((Register)(R31_RegisterEnumValue)) |
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188 #endif |
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189 |
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190 // Use ConditionRegister as shortcut |
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191 class ConditionRegisterImpl; |
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192 typedef ConditionRegisterImpl* ConditionRegister; |
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193 |
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194 inline ConditionRegister as_ConditionRegister(int encoding) { |
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195 assert(encoding >= 0 && encoding < 8, "bad condition register encoding"); |
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196 return (ConditionRegister)(intptr_t)encoding; |
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197 } |
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198 |
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199 // The implementation of condition register(s) for the PPC architecture |
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200 class ConditionRegisterImpl: public AbstractRegisterImpl { |
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201 public: |
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202 enum { |
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203 number_of_registers = 8 |
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204 }; |
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205 |
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206 // construction. |
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207 inline friend ConditionRegister as_ConditionRegister(int encoding); |
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208 |
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209 // accessors |
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210 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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211 inline VMReg as_VMReg(); |
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212 |
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213 // testers |
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214 bool is_valid() const { return (0 <= value() && value() < number_of_registers); } |
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215 bool is_nonvolatile() const { return (2 <= (value()&0x7F) && (value()&0x7F) <= 4 ); } |
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216 |
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217 const char* name() const; |
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218 }; |
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219 |
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220 // The (parts of the) condition register(s) of the PPC architecture |
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221 // sys/ioctl.h on AIX defines CR0-CR3, so I name these CCR. |
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222 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR0, (0)); |
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223 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR1, (1)); |
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224 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR2, (2)); |
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225 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR3, (3)); |
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226 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR4, (4)); |
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227 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR5, (5)); |
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228 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR6, (6)); |
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229 CONSTANT_REGISTER_DECLARATION(ConditionRegister, CCR7, (7)); |
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230 |
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231 #ifndef DONT_USE_REGISTER_DEFINES |
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232 |
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233 #define CCR0 ((ConditionRegister)(CCR0_ConditionRegisterEnumValue)) |
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234 #define CCR1 ((ConditionRegister)(CCR1_ConditionRegisterEnumValue)) |
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235 #define CCR2 ((ConditionRegister)(CCR2_ConditionRegisterEnumValue)) |
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236 #define CCR3 ((ConditionRegister)(CCR3_ConditionRegisterEnumValue)) |
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237 #define CCR4 ((ConditionRegister)(CCR4_ConditionRegisterEnumValue)) |
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238 #define CCR5 ((ConditionRegister)(CCR5_ConditionRegisterEnumValue)) |
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239 #define CCR6 ((ConditionRegister)(CCR6_ConditionRegisterEnumValue)) |
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240 #define CCR7 ((ConditionRegister)(CCR7_ConditionRegisterEnumValue)) |
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241 |
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242 #endif // DONT_USE_REGISTER_DEFINES |
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243 |
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244 |
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245 // Use FloatRegister as shortcut |
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246 class FloatRegisterImpl; |
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247 typedef FloatRegisterImpl* FloatRegister; |
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248 |
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249 inline FloatRegister as_FloatRegister(int encoding) { |
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250 assert(encoding >= -1 && encoding < 32, "bad float register encoding"); |
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251 return (FloatRegister)(intptr_t)encoding; |
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252 } |
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253 |
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254 // The implementation of float registers for the PPC architecture |
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255 class FloatRegisterImpl: public AbstractRegisterImpl { |
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256 public: |
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257 enum { |
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258 number_of_registers = 32 |
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259 }; |
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260 |
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261 // construction |
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262 inline friend FloatRegister as_FloatRegister(int encoding); |
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263 |
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264 // accessors |
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265 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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266 inline VMReg as_VMReg(); |
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267 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } |
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268 |
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269 // testers |
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270 bool is_valid() const { return (0 <= value() && value() < number_of_registers); } |
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271 |
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272 const char* name() const; |
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273 }; |
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274 |
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275 // The float registers of the PPC architecture |
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276 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, (-1)); |
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277 |
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278 CONSTANT_REGISTER_DECLARATION(FloatRegister, F0, ( 0)); |
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279 CONSTANT_REGISTER_DECLARATION(FloatRegister, F1, ( 1)); |
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280 CONSTANT_REGISTER_DECLARATION(FloatRegister, F2, ( 2)); |
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281 CONSTANT_REGISTER_DECLARATION(FloatRegister, F3, ( 3)); |
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282 CONSTANT_REGISTER_DECLARATION(FloatRegister, F4, ( 4)); |
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283 CONSTANT_REGISTER_DECLARATION(FloatRegister, F5, ( 5)); |
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284 CONSTANT_REGISTER_DECLARATION(FloatRegister, F6, ( 6)); |
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285 CONSTANT_REGISTER_DECLARATION(FloatRegister, F7, ( 7)); |
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286 CONSTANT_REGISTER_DECLARATION(FloatRegister, F8, ( 8)); |
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287 CONSTANT_REGISTER_DECLARATION(FloatRegister, F9, ( 9)); |
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288 CONSTANT_REGISTER_DECLARATION(FloatRegister, F10, (10)); |
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289 CONSTANT_REGISTER_DECLARATION(FloatRegister, F11, (11)); |
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290 CONSTANT_REGISTER_DECLARATION(FloatRegister, F12, (12)); |
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291 CONSTANT_REGISTER_DECLARATION(FloatRegister, F13, (13)); |
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292 CONSTANT_REGISTER_DECLARATION(FloatRegister, F14, (14)); |
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293 CONSTANT_REGISTER_DECLARATION(FloatRegister, F15, (15)); |
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294 CONSTANT_REGISTER_DECLARATION(FloatRegister, F16, (16)); |
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295 CONSTANT_REGISTER_DECLARATION(FloatRegister, F17, (17)); |
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296 CONSTANT_REGISTER_DECLARATION(FloatRegister, F18, (18)); |
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297 CONSTANT_REGISTER_DECLARATION(FloatRegister, F19, (19)); |
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298 CONSTANT_REGISTER_DECLARATION(FloatRegister, F20, (20)); |
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299 CONSTANT_REGISTER_DECLARATION(FloatRegister, F21, (21)); |
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300 CONSTANT_REGISTER_DECLARATION(FloatRegister, F22, (22)); |
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301 CONSTANT_REGISTER_DECLARATION(FloatRegister, F23, (23)); |
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302 CONSTANT_REGISTER_DECLARATION(FloatRegister, F24, (24)); |
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303 CONSTANT_REGISTER_DECLARATION(FloatRegister, F25, (25)); |
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304 CONSTANT_REGISTER_DECLARATION(FloatRegister, F26, (26)); |
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305 CONSTANT_REGISTER_DECLARATION(FloatRegister, F27, (27)); |
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306 CONSTANT_REGISTER_DECLARATION(FloatRegister, F28, (28)); |
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307 CONSTANT_REGISTER_DECLARATION(FloatRegister, F29, (29)); |
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308 CONSTANT_REGISTER_DECLARATION(FloatRegister, F30, (30)); |
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309 CONSTANT_REGISTER_DECLARATION(FloatRegister, F31, (31)); |
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310 |
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311 #ifndef DONT_USE_REGISTER_DEFINES |
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312 #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue)) |
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313 #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue)) |
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314 #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue)) |
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315 #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue)) |
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316 #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue)) |
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317 #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue)) |
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318 #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue)) |
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319 #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue)) |
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320 #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue)) |
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321 #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue)) |
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322 #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue)) |
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323 #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue)) |
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324 #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue)) |
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325 #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue)) |
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326 #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue)) |
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327 #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue)) |
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328 #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue)) |
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329 #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue)) |
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330 #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue)) |
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331 #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue)) |
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332 #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue)) |
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333 #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue)) |
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334 #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue)) |
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335 #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue)) |
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336 #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue)) |
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337 #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue)) |
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338 #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue)) |
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339 #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue)) |
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340 #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue)) |
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341 #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue)) |
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342 #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue)) |
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343 #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue)) |
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344 #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue)) |
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345 #endif // DONT_USE_REGISTER_DEFINES |
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346 |
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347 // Use SpecialRegister as shortcut |
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348 class SpecialRegisterImpl; |
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349 typedef SpecialRegisterImpl* SpecialRegister; |
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350 |
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351 inline SpecialRegister as_SpecialRegister(int encoding) { |
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352 return (SpecialRegister)(intptr_t)encoding; |
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353 } |
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354 |
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355 // The implementation of special registers for the Power architecture (LR, CTR and friends) |
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356 class SpecialRegisterImpl: public AbstractRegisterImpl { |
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357 public: |
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358 enum { |
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359 number_of_registers = 6 |
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360 }; |
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361 |
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362 // construction |
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363 inline friend SpecialRegister as_SpecialRegister(int encoding); |
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364 |
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365 // accessors |
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366 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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367 inline VMReg as_VMReg(); |
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368 |
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369 // testers |
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370 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } |
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371 |
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372 const char* name() const; |
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373 }; |
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374 |
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375 // The special registers of the PPC architecture |
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376 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_XER, (0)); |
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377 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_LR, (1)); |
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378 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_CTR, (2)); |
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379 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_VRSAVE, (3)); |
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380 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_SPEFSCR, (4)); |
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381 CONSTANT_REGISTER_DECLARATION(SpecialRegister, SR_PPR, (5)); |
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382 |
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383 #ifndef DONT_USE_REGISTER_DEFINES |
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384 #define SR_XER ((SpecialRegister)(SR_XER_SpecialRegisterEnumValue)) |
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385 #define SR_LR ((SpecialRegister)(SR_LR_SpecialRegisterEnumValue)) |
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386 #define SR_CTR ((SpecialRegister)(SR_CTR_SpecialRegisterEnumValue)) |
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387 #define SR_VRSAVE ((SpecialRegister)(SR_VRSAVE_SpecialRegisterEnumValue)) |
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388 #define SR_SPEFSCR ((SpecialRegister)(SR_SPEFSCR_SpecialRegisterEnumValue)) |
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389 #define SR_PPR ((SpecialRegister)(SR_PPR_SpecialRegisterEnumValue)) |
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390 #endif // DONT_USE_REGISTER_DEFINES |
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391 |
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392 |
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393 // Use VectorRegister as shortcut |
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394 class VectorRegisterImpl; |
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395 typedef VectorRegisterImpl* VectorRegister; |
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396 |
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397 inline VectorRegister as_VectorRegister(int encoding) { |
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398 return (VectorRegister)(intptr_t)encoding; |
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399 } |
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400 |
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401 // Forward declaration |
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402 // Use VectorSRegister as a shortcut. |
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403 class VectorSRegisterImpl; |
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404 typedef VectorSRegisterImpl* VectorSRegister; |
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405 |
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406 // The implementation of vector registers for the Power architecture |
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407 class VectorRegisterImpl: public AbstractRegisterImpl { |
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408 public: |
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409 enum { |
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410 number_of_registers = 32 |
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411 }; |
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412 |
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413 // construction |
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414 inline friend VectorRegister as_VectorRegister(int encoding); |
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415 |
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416 // accessors |
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417 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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418 |
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419 // testers |
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420 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } |
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421 |
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422 const char* name() const; |
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423 |
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424 // convert to VSR |
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425 VectorSRegister to_vsr() const; |
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426 }; |
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427 |
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428 // The Vector registers of the Power architecture |
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429 |
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430 CONSTANT_REGISTER_DECLARATION(VectorRegister, vnoreg, (-1)); |
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431 |
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432 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR0, ( 0)); |
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433 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR1, ( 1)); |
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434 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR2, ( 2)); |
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435 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR3, ( 3)); |
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436 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR4, ( 4)); |
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437 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR5, ( 5)); |
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438 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR6, ( 6)); |
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439 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR7, ( 7)); |
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440 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR8, ( 8)); |
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441 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR9, ( 9)); |
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442 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR10, (10)); |
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443 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR11, (11)); |
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444 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR12, (12)); |
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445 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR13, (13)); |
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446 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR14, (14)); |
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447 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR15, (15)); |
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448 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR16, (16)); |
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449 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR17, (17)); |
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450 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR18, (18)); |
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451 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR19, (19)); |
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452 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR20, (20)); |
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453 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR21, (21)); |
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454 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR22, (22)); |
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455 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR23, (23)); |
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456 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR24, (24)); |
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457 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR25, (25)); |
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458 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR26, (26)); |
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459 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR27, (27)); |
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460 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR28, (28)); |
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461 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR29, (29)); |
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462 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR30, (30)); |
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463 CONSTANT_REGISTER_DECLARATION(VectorRegister, VR31, (31)); |
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464 |
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465 #ifndef DONT_USE_REGISTER_DEFINES |
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466 #define vnoreg ((VectorRegister)(vnoreg_VectorRegisterEnumValue)) |
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467 #define VR0 ((VectorRegister)( VR0_VectorRegisterEnumValue)) |
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468 #define VR1 ((VectorRegister)( VR1_VectorRegisterEnumValue)) |
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469 #define VR2 ((VectorRegister)( VR2_VectorRegisterEnumValue)) |
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470 #define VR3 ((VectorRegister)( VR3_VectorRegisterEnumValue)) |
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471 #define VR4 ((VectorRegister)( VR4_VectorRegisterEnumValue)) |
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472 #define VR5 ((VectorRegister)( VR5_VectorRegisterEnumValue)) |
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473 #define VR6 ((VectorRegister)( VR6_VectorRegisterEnumValue)) |
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474 #define VR7 ((VectorRegister)( VR7_VectorRegisterEnumValue)) |
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475 #define VR8 ((VectorRegister)( VR8_VectorRegisterEnumValue)) |
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476 #define VR9 ((VectorRegister)( VR9_VectorRegisterEnumValue)) |
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477 #define VR10 ((VectorRegister)( VR10_VectorRegisterEnumValue)) |
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478 #define VR11 ((VectorRegister)( VR11_VectorRegisterEnumValue)) |
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479 #define VR12 ((VectorRegister)( VR12_VectorRegisterEnumValue)) |
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480 #define VR13 ((VectorRegister)( VR13_VectorRegisterEnumValue)) |
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481 #define VR14 ((VectorRegister)( VR14_VectorRegisterEnumValue)) |
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482 #define VR15 ((VectorRegister)( VR15_VectorRegisterEnumValue)) |
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483 #define VR16 ((VectorRegister)( VR16_VectorRegisterEnumValue)) |
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484 #define VR17 ((VectorRegister)( VR17_VectorRegisterEnumValue)) |
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485 #define VR18 ((VectorRegister)( VR18_VectorRegisterEnumValue)) |
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486 #define VR19 ((VectorRegister)( VR19_VectorRegisterEnumValue)) |
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487 #define VR20 ((VectorRegister)( VR20_VectorRegisterEnumValue)) |
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488 #define VR21 ((VectorRegister)( VR21_VectorRegisterEnumValue)) |
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489 #define VR22 ((VectorRegister)( VR22_VectorRegisterEnumValue)) |
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490 #define VR23 ((VectorRegister)( VR23_VectorRegisterEnumValue)) |
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491 #define VR24 ((VectorRegister)( VR24_VectorRegisterEnumValue)) |
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492 #define VR25 ((VectorRegister)( VR25_VectorRegisterEnumValue)) |
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493 #define VR26 ((VectorRegister)( VR26_VectorRegisterEnumValue)) |
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494 #define VR27 ((VectorRegister)( VR27_VectorRegisterEnumValue)) |
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495 #define VR28 ((VectorRegister)( VR28_VectorRegisterEnumValue)) |
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496 #define VR29 ((VectorRegister)( VR29_VectorRegisterEnumValue)) |
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497 #define VR30 ((VectorRegister)( VR30_VectorRegisterEnumValue)) |
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498 #define VR31 ((VectorRegister)( VR31_VectorRegisterEnumValue)) |
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499 #endif // DONT_USE_REGISTER_DEFINES |
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500 |
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501 |
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502 inline VectorSRegister as_VectorSRegister(int encoding) { |
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503 return (VectorSRegister)(intptr_t)encoding; |
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504 } |
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505 |
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506 // The implementation of Vector-Scalar (VSX) registers on POWER architecture. |
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507 class VectorSRegisterImpl: public AbstractRegisterImpl { |
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508 public: |
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509 enum { |
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510 number_of_registers = 64 |
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511 }; |
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512 |
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513 // construction |
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514 inline friend VectorSRegister as_VectorSRegister(int encoding); |
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515 |
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516 // accessors |
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517 int encoding() const { assert(is_valid(), "invalid register"); return value(); } |
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518 |
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519 // testers |
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520 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } |
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521 |
|
522 const char* name() const; |
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523 }; |
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524 |
|
525 // The Vector-Scalar (VSX) registers of the POWER architecture. |
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526 |
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527 CONSTANT_REGISTER_DECLARATION(VectorSRegister, vsnoreg, (-1)); |
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528 |
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529 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR0, ( 0)); |
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530 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR1, ( 1)); |
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531 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR2, ( 2)); |
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532 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR3, ( 3)); |
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533 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR4, ( 4)); |
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534 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR5, ( 5)); |
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535 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR6, ( 6)); |
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536 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR7, ( 7)); |
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537 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR8, ( 8)); |
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538 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR9, ( 9)); |
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539 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR10, (10)); |
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540 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR11, (11)); |
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541 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR12, (12)); |
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542 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR13, (13)); |
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543 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR14, (14)); |
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544 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR15, (15)); |
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545 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR16, (16)); |
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546 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR17, (17)); |
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547 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR18, (18)); |
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548 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR19, (19)); |
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549 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR20, (20)); |
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550 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR21, (21)); |
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551 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR22, (22)); |
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552 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR23, (23)); |
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553 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR24, (24)); |
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554 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR25, (25)); |
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555 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR26, (26)); |
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556 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR27, (27)); |
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557 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR28, (28)); |
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558 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR29, (29)); |
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559 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR30, (30)); |
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560 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR31, (31)); |
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561 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR32, (32)); |
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562 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR33, (33)); |
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563 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR34, (34)); |
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564 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR35, (35)); |
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565 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR36, (36)); |
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566 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR37, (37)); |
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567 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR38, (38)); |
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568 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR39, (39)); |
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569 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR40, (40)); |
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570 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR41, (41)); |
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571 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR42, (42)); |
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572 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR43, (43)); |
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573 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR44, (44)); |
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574 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR45, (45)); |
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575 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR46, (46)); |
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576 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR47, (47)); |
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577 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR48, (48)); |
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578 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR49, (49)); |
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579 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR50, (50)); |
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580 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR51, (51)); |
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581 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR52, (52)); |
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582 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR53, (53)); |
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583 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR54, (54)); |
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584 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR55, (55)); |
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585 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR56, (56)); |
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586 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR57, (57)); |
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587 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR58, (58)); |
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588 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR59, (59)); |
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589 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR60, (60)); |
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590 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR61, (61)); |
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591 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR62, (62)); |
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592 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR63, (63)); |
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593 |
|
594 #ifndef DONT_USE_REGISTER_DEFINES |
|
595 #define vsnoregi ((VectorSRegister)(vsnoreg_VectorSRegisterEnumValue)) |
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596 #define VSR0 ((VectorSRegister)( VSR0_VectorSRegisterEnumValue)) |
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597 #define VSR1 ((VectorSRegister)( VSR1_VectorSRegisterEnumValue)) |
|
598 #define VSR2 ((VectorSRegister)( VSR2_VectorSRegisterEnumValue)) |
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599 #define VSR3 ((VectorSRegister)( VSR3_VectorSRegisterEnumValue)) |
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600 #define VSR4 ((VectorSRegister)( VSR4_VectorSRegisterEnumValue)) |
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601 #define VSR5 ((VectorSRegister)( VSR5_VectorSRegisterEnumValue)) |
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602 #define VSR6 ((VectorSRegister)( VSR6_VectorSRegisterEnumValue)) |
|
603 #define VSR7 ((VectorSRegister)( VSR7_VectorSRegisterEnumValue)) |
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604 #define VSR8 ((VectorSRegister)( VSR8_VectorSRegisterEnumValue)) |
|
605 #define VSR9 ((VectorSRegister)( VSR9_VectorSRegisterEnumValue)) |
|
606 #define VSR10 ((VectorSRegister)( VSR10_VectorSRegisterEnumValue)) |
|
607 #define VSR11 ((VectorSRegister)( VSR11_VectorSRegisterEnumValue)) |
|
608 #define VSR12 ((VectorSRegister)( VSR12_VectorSRegisterEnumValue)) |
|
609 #define VSR13 ((VectorSRegister)( VSR13_VectorSRegisterEnumValue)) |
|
610 #define VSR14 ((VectorSRegister)( VSR14_VectorSRegisterEnumValue)) |
|
611 #define VSR15 ((VectorSRegister)( VSR15_VectorSRegisterEnumValue)) |
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612 #define VSR16 ((VectorSRegister)( VSR16_VectorSRegisterEnumValue)) |
|
613 #define VSR17 ((VectorSRegister)( VSR17_VectorSRegisterEnumValue)) |
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614 #define VSR18 ((VectorSRegister)( VSR18_VectorSRegisterEnumValue)) |
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615 #define VSR19 ((VectorSRegister)( VSR19_VectorSRegisterEnumValue)) |
|
616 #define VSR20 ((VectorSRegister)( VSR20_VectorSRegisterEnumValue)) |
|
617 #define VSR21 ((VectorSRegister)( VSR21_VectorSRegisterEnumValue)) |
|
618 #define VSR22 ((VectorSRegister)( VSR22_VectorSRegisterEnumValue)) |
|
619 #define VSR23 ((VectorSRegister)( VSR23_VectorSRegisterEnumValue)) |
|
620 #define VSR24 ((VectorSRegister)( VSR24_VectorSRegisterEnumValue)) |
|
621 #define VSR25 ((VectorSRegister)( VSR25_VectorSRegisterEnumValue)) |
|
622 #define VSR26 ((VectorSRegister)( VSR26_VectorSRegisterEnumValue)) |
|
623 #define VSR27 ((VectorSRegister)( VSR27_VectorSRegisterEnumValue)) |
|
624 #define VSR28 ((VectorSRegister)( VSR28_VectorSRegisterEnumValue)) |
|
625 #define VSR29 ((VectorSRegister)( VSR29_VectorSRegisterEnumValue)) |
|
626 #define VSR30 ((VectorSRegister)( VSR30_VectorSRegisterEnumValue)) |
|
627 #define VSR31 ((VectorSRegister)( VSR31_VectorSRegisterEnumValue)) |
|
628 #define VSR32 ((VectorSRegister)( VSR32_VectorSRegisterEnumValue)) |
|
629 #define VSR33 ((VectorSRegister)( VSR33_VectorSRegisterEnumValue)) |
|
630 #define VSR34 ((VectorSRegister)( VSR34_VectorSRegisterEnumValue)) |
|
631 #define VSR35 ((VectorSRegister)( VSR35_VectorSRegisterEnumValue)) |
|
632 #define VSR36 ((VectorSRegister)( VSR36_VectorSRegisterEnumValue)) |
|
633 #define VSR37 ((VectorSRegister)( VSR37_VectorSRegisterEnumValue)) |
|
634 #define VSR38 ((VectorSRegister)( VSR38_VectorSRegisterEnumValue)) |
|
635 #define VSR39 ((VectorSRegister)( VSR39_VectorSRegisterEnumValue)) |
|
636 #define VSR40 ((VectorSRegister)( VSR40_VectorSRegisterEnumValue)) |
|
637 #define VSR41 ((VectorSRegister)( VSR41_VectorSRegisterEnumValue)) |
|
638 #define VSR42 ((VectorSRegister)( VSR42_VectorSRegisterEnumValue)) |
|
639 #define VSR43 ((VectorSRegister)( VSR43_VectorSRegisterEnumValue)) |
|
640 #define VSR44 ((VectorSRegister)( VSR44_VectorSRegisterEnumValue)) |
|
641 #define VSR45 ((VectorSRegister)( VSR45_VectorSRegisterEnumValue)) |
|
642 #define VSR46 ((VectorSRegister)( VSR46_VectorSRegisterEnumValue)) |
|
643 #define VSR47 ((VectorSRegister)( VSR47_VectorSRegisterEnumValue)) |
|
644 #define VSR48 ((VectorSRegister)( VSR48_VectorSRegisterEnumValue)) |
|
645 #define VSR49 ((VectorSRegister)( VSR49_VectorSRegisterEnumValue)) |
|
646 #define VSR50 ((VectorSRegister)( VSR50_VectorSRegisterEnumValue)) |
|
647 #define VSR51 ((VectorSRegister)( VSR51_VectorSRegisterEnumValue)) |
|
648 #define VSR52 ((VectorSRegister)( VSR52_VectorSRegisterEnumValue)) |
|
649 #define VSR53 ((VectorSRegister)( VSR53_VectorSRegisterEnumValue)) |
|
650 #define VSR54 ((VectorSRegister)( VSR54_VectorSRegisterEnumValue)) |
|
651 #define VSR55 ((VectorSRegister)( VSR55_VectorSRegisterEnumValue)) |
|
652 #define VSR56 ((VectorSRegister)( VSR56_VectorSRegisterEnumValue)) |
|
653 #define VSR57 ((VectorSRegister)( VSR57_VectorSRegisterEnumValue)) |
|
654 #define VSR58 ((VectorSRegister)( VSR58_VectorSRegisterEnumValue)) |
|
655 #define VSR59 ((VectorSRegister)( VSR59_VectorSRegisterEnumValue)) |
|
656 #define VSR60 ((VectorSRegister)( VSR60_VectorSRegisterEnumValue)) |
|
657 #define VSR61 ((VectorSRegister)( VSR61_VectorSRegisterEnumValue)) |
|
658 #define VSR62 ((VectorSRegister)( VSR62_VectorSRegisterEnumValue)) |
|
659 #define VSR63 ((VectorSRegister)( VSR63_VectorSRegisterEnumValue)) |
|
660 #endif // DONT_USE_REGISTER_DEFINES |
|
661 |
|
662 // Maximum number of incoming arguments that can be passed in i registers. |
|
663 const int PPC_ARGS_IN_REGS_NUM = 8; |
|
664 |
|
665 |
|
666 // Need to know the total number of registers of all sorts for SharedInfo. |
|
667 // Define a class that exports it. |
|
668 class ConcreteRegisterImpl : public AbstractRegisterImpl { |
|
669 public: |
|
670 enum { |
|
671 // This number must be large enough to cover REG_COUNT (defined by c2) registers. |
|
672 // There is no requirement that any ordering here matches any ordering c2 gives |
|
673 // it's optoregs. |
|
674 number_of_registers = |
|
675 ( RegisterImpl::number_of_registers + |
|
676 FloatRegisterImpl::number_of_registers ) |
|
677 * 2 // register halves |
|
678 + ConditionRegisterImpl::number_of_registers // condition code registers |
|
679 + SpecialRegisterImpl::number_of_registers // special registers |
|
680 + VectorRegisterImpl::number_of_registers // VSX registers |
|
681 }; |
|
682 |
|
683 static const int max_gpr; |
|
684 static const int max_fpr; |
|
685 static const int max_cnd; |
|
686 }; |
|
687 |
|
688 // Common register declarations used in assembler code. |
|
689 REGISTER_DECLARATION(Register, R0_SCRATCH, R0); // volatile |
|
690 REGISTER_DECLARATION(Register, R1_SP, R1); // non-volatile |
|
691 REGISTER_DECLARATION(Register, R2_TOC, R2); // volatile |
|
692 REGISTER_DECLARATION(Register, R3_RET, R3); // volatile |
|
693 REGISTER_DECLARATION(Register, R3_ARG1, R3); // volatile |
|
694 REGISTER_DECLARATION(Register, R4_ARG2, R4); // volatile |
|
695 REGISTER_DECLARATION(Register, R5_ARG3, R5); // volatile |
|
696 REGISTER_DECLARATION(Register, R6_ARG4, R6); // volatile |
|
697 REGISTER_DECLARATION(Register, R7_ARG5, R7); // volatile |
|
698 REGISTER_DECLARATION(Register, R8_ARG6, R8); // volatile |
|
699 REGISTER_DECLARATION(Register, R9_ARG7, R9); // volatile |
|
700 REGISTER_DECLARATION(Register, R10_ARG8, R10); // volatile |
|
701 REGISTER_DECLARATION(FloatRegister, F0_SCRATCH, F0); // volatile |
|
702 REGISTER_DECLARATION(FloatRegister, F1_RET, F1); // volatile |
|
703 REGISTER_DECLARATION(FloatRegister, F1_ARG1, F1); // volatile |
|
704 REGISTER_DECLARATION(FloatRegister, F2_ARG2, F2); // volatile |
|
705 REGISTER_DECLARATION(FloatRegister, F3_ARG3, F3); // volatile |
|
706 REGISTER_DECLARATION(FloatRegister, F4_ARG4, F4); // volatile |
|
707 REGISTER_DECLARATION(FloatRegister, F5_ARG5, F5); // volatile |
|
708 REGISTER_DECLARATION(FloatRegister, F6_ARG6, F6); // volatile |
|
709 REGISTER_DECLARATION(FloatRegister, F7_ARG7, F7); // volatile |
|
710 REGISTER_DECLARATION(FloatRegister, F8_ARG8, F8); // volatile |
|
711 REGISTER_DECLARATION(FloatRegister, F9_ARG9, F9); // volatile |
|
712 REGISTER_DECLARATION(FloatRegister, F10_ARG10, F10); // volatile |
|
713 REGISTER_DECLARATION(FloatRegister, F11_ARG11, F11); // volatile |
|
714 REGISTER_DECLARATION(FloatRegister, F12_ARG12, F12); // volatile |
|
715 REGISTER_DECLARATION(FloatRegister, F13_ARG13, F13); // volatile |
|
716 |
|
717 #ifndef DONT_USE_REGISTER_DEFINES |
|
718 #define R0_SCRATCH AS_REGISTER(Register, R0) |
|
719 #define R1_SP AS_REGISTER(Register, R1) |
|
720 #define R2_TOC AS_REGISTER(Register, R2) |
|
721 #define R3_RET AS_REGISTER(Register, R3) |
|
722 #define R3_ARG1 AS_REGISTER(Register, R3) |
|
723 #define R4_ARG2 AS_REGISTER(Register, R4) |
|
724 #define R5_ARG3 AS_REGISTER(Register, R5) |
|
725 #define R6_ARG4 AS_REGISTER(Register, R6) |
|
726 #define R7_ARG5 AS_REGISTER(Register, R7) |
|
727 #define R8_ARG6 AS_REGISTER(Register, R8) |
|
728 #define R9_ARG7 AS_REGISTER(Register, R9) |
|
729 #define R10_ARG8 AS_REGISTER(Register, R10) |
|
730 #define F0_SCRATCH AS_REGISTER(FloatRegister, F0) |
|
731 #define F1_RET AS_REGISTER(FloatRegister, F1) |
|
732 #define F1_ARG1 AS_REGISTER(FloatRegister, F1) |
|
733 #define F2_ARG2 AS_REGISTER(FloatRegister, F2) |
|
734 #define F3_ARG3 AS_REGISTER(FloatRegister, F3) |
|
735 #define F4_ARG4 AS_REGISTER(FloatRegister, F4) |
|
736 #define F5_ARG5 AS_REGISTER(FloatRegister, F5) |
|
737 #define F6_ARG6 AS_REGISTER(FloatRegister, F6) |
|
738 #define F7_ARG7 AS_REGISTER(FloatRegister, F7) |
|
739 #define F8_ARG8 AS_REGISTER(FloatRegister, F8) |
|
740 #define F9_ARG9 AS_REGISTER(FloatRegister, F9) |
|
741 #define F10_ARG10 AS_REGISTER(FloatRegister, F10) |
|
742 #define F11_ARG11 AS_REGISTER(FloatRegister, F11) |
|
743 #define F12_ARG12 AS_REGISTER(FloatRegister, F12) |
|
744 #define F13_ARG13 AS_REGISTER(FloatRegister, F13) |
|
745 #endif |
|
746 |
|
747 // Register declarations to be used in frame manager assembly code. |
|
748 // Use only non-volatile registers in order to keep values across C-calls. |
|
749 REGISTER_DECLARATION(Register, R14_bcp, R14); |
|
750 REGISTER_DECLARATION(Register, R15_esp, R15); |
|
751 REGISTER_DECLARATION(FloatRegister, F15_ftos, F15); |
|
752 REGISTER_DECLARATION(Register, R16_thread, R16); // address of current thread |
|
753 REGISTER_DECLARATION(Register, R17_tos, R17); // address of Java tos (prepushed). |
|
754 REGISTER_DECLARATION(Register, R18_locals, R18); // address of first param slot (receiver). |
|
755 REGISTER_DECLARATION(Register, R19_method, R19); // address of current method |
|
756 #ifndef DONT_USE_REGISTER_DEFINES |
|
757 #define R14_bcp AS_REGISTER(Register, R14) |
|
758 #define R15_esp AS_REGISTER(Register, R15) |
|
759 #define F15_ftos AS_REGISTER(FloatRegister, F15) |
|
760 #define R16_thread AS_REGISTER(Register, R16) |
|
761 #define R17_tos AS_REGISTER(Register, R17) |
|
762 #define R18_locals AS_REGISTER(Register, R18) |
|
763 #define R19_method AS_REGISTER(Register, R19) |
|
764 #define R21_sender_SP AS_REGISTER(Register, R21) |
|
765 #define R23_method_handle AS_REGISTER(Register, R23) |
|
766 #endif |
|
767 |
|
768 // Temporary registers to be used within frame manager. We can use |
|
769 // the non-volatiles because the call stub has saved them. |
|
770 // Use only non-volatile registers in order to keep values across C-calls. |
|
771 REGISTER_DECLARATION(Register, R21_tmp1, R21); |
|
772 REGISTER_DECLARATION(Register, R22_tmp2, R22); |
|
773 REGISTER_DECLARATION(Register, R23_tmp3, R23); |
|
774 REGISTER_DECLARATION(Register, R24_tmp4, R24); |
|
775 REGISTER_DECLARATION(Register, R25_tmp5, R25); |
|
776 REGISTER_DECLARATION(Register, R26_tmp6, R26); |
|
777 REGISTER_DECLARATION(Register, R27_tmp7, R27); |
|
778 REGISTER_DECLARATION(Register, R28_tmp8, R28); |
|
779 REGISTER_DECLARATION(Register, R29_tmp9, R29); |
|
780 REGISTER_DECLARATION(Register, R24_dispatch_addr, R24); |
|
781 REGISTER_DECLARATION(Register, R25_templateTableBase, R25); |
|
782 REGISTER_DECLARATION(Register, R26_monitor, R26); |
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783 REGISTER_DECLARATION(Register, R27_constPoolCache, R27); |
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784 REGISTER_DECLARATION(Register, R28_mdx, R28); |
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785 |
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786 REGISTER_DECLARATION(Register, R19_inline_cache_reg, R19); |
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787 REGISTER_DECLARATION(Register, R29_TOC, R29); |
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788 |
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789 #ifndef DONT_USE_REGISTER_DEFINES |
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790 #define R21_tmp1 AS_REGISTER(Register, R21) |
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791 #define R22_tmp2 AS_REGISTER(Register, R22) |
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792 #define R23_tmp3 AS_REGISTER(Register, R23) |
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793 #define R24_tmp4 AS_REGISTER(Register, R24) |
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794 #define R25_tmp5 AS_REGISTER(Register, R25) |
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795 #define R26_tmp6 AS_REGISTER(Register, R26) |
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796 #define R27_tmp7 AS_REGISTER(Register, R27) |
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797 #define R28_tmp8 AS_REGISTER(Register, R28) |
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798 #define R29_tmp9 AS_REGISTER(Register, R29) |
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799 // Lmonitors : monitor pointer |
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800 // LcpoolCache: constant pool cache |
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801 // mdx: method data index |
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802 #define R24_dispatch_addr AS_REGISTER(Register, R24) |
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803 #define R25_templateTableBase AS_REGISTER(Register, R25) |
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804 #define R26_monitor AS_REGISTER(Register, R26) |
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805 #define R27_constPoolCache AS_REGISTER(Register, R27) |
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806 #define R28_mdx AS_REGISTER(Register, R28) |
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807 |
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808 #define R19_inline_cache_reg AS_REGISTER(Register, R19) |
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809 #define R29_TOC AS_REGISTER(Register, R29) |
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810 #endif |
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811 |
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812 // Scratch registers are volatile. |
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813 REGISTER_DECLARATION(Register, R11_scratch1, R11); |
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814 REGISTER_DECLARATION(Register, R12_scratch2, R12); |
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815 #ifndef DONT_USE_REGISTER_DEFINES |
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816 #define R11_scratch1 AS_REGISTER(Register, R11) |
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817 #define R12_scratch2 AS_REGISTER(Register, R12) |
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818 #endif |
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819 |
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820 #endif // CPU_PPC_VM_REGISTER_PPC_HPP |